1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2b066303fSPaul Burton /* 3b066303fSPaul Burton * Ingenic SoC CGU driver 4b066303fSPaul Burton * 5b066303fSPaul Burton * Copyright (c) 2013-2015 Imagination Technologies 6fb615d61SPaul Burton * Author: Paul Burton <paul.burton@mips.com> 7b066303fSPaul Burton */ 8b066303fSPaul Burton 9b066303fSPaul Burton #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 10b066303fSPaul Burton #define __DRIVERS_CLK_INGENIC_CGU_H__ 11b066303fSPaul Burton 12b066303fSPaul Burton #include <linux/bitops.h> 13dbc38ad0SPaul Cercueil #include <linux/clk-provider.h> 14b066303fSPaul Burton #include <linux/of.h> 15b066303fSPaul Burton #include <linux/spinlock.h> 16b066303fSPaul Burton 17b066303fSPaul Burton /** 18b066303fSPaul Burton * struct ingenic_cgu_pll_info - information about a PLL 19b066303fSPaul Burton * @reg: the offset of the PLL's control register within the CGU 209d9cc58aS周琰杰 (Zhou Yanjie) * @rate_multiplier: the multiplier needed by pll rate calculation 21b066303fSPaul Burton * @m_shift: the number of bits to shift the multiplier value by (ie. the 22b066303fSPaul Burton * index of the lowest bit of the multiplier value in the PLL's 23b066303fSPaul Burton * control register) 24b066303fSPaul Burton * @m_bits: the size of the multiplier field in bits 25b066303fSPaul Burton * @m_offset: the multiplier value which encodes to 0 in the PLL's control 26b066303fSPaul Burton * register 27b066303fSPaul Burton * @n_shift: the number of bits to shift the divider value by (ie. the 28b066303fSPaul Burton * index of the lowest bit of the divider value in the PLL's 29b066303fSPaul Burton * control register) 30b066303fSPaul Burton * @n_bits: the size of the divider field in bits 31b066303fSPaul Burton * @n_offset: the divider value which encodes to 0 in the PLL's control 32b066303fSPaul Burton * register 33b066303fSPaul Burton * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 34b066303fSPaul Burton * the index of the lowest bit of the post-VCO divider value in 35b066303fSPaul Burton * the PLL's control register) 3683b975b5SAidan MacDonald * @od_bits: the size of the post-VCO divider field in bits, or 0 if no 3783b975b5SAidan MacDonald * OD field exists (then the OD is fixed to 1) 38b066303fSPaul Burton * @od_max: the maximum post-VCO divider value 39b066303fSPaul Burton * @od_encoding: a pointer to an array mapping post-VCO divider values to 40b066303fSPaul Burton * their encoded values in the PLL control register, or -1 for 41b066303fSPaul Burton * unsupported values 429d9cc58aS周琰杰 (Zhou Yanjie) * @bypass_reg: the offset of the bypass control register within the CGU 43037f1ffdSPaul Cercueil * @bypass_bit: the index of the bypass bit in the PLL control register, or 44037f1ffdSPaul Cercueil * -1 if there is no bypass bit 45d84bf9d6SAidan MacDonald * @enable_bit: the index of the enable bit in the PLL control register, or 46d84bf9d6SAidan MacDonald * -1 if there is no enable bit (ie, the PLL is always on) 47d84bf9d6SAidan MacDonald * @stable_bit: the index of the stable bit in the PLL control register, or 48d84bf9d6SAidan MacDonald * -1 if there is no stable bit 49*c799a777SAidan MacDonald * @set_rate_hook: hook called immediately after updating the CGU register, 50*c799a777SAidan MacDonald * before releasing the spinlock 51b066303fSPaul Burton */ 52b066303fSPaul Burton struct ingenic_cgu_pll_info { 53b066303fSPaul Burton unsigned reg; 549d9cc58aS周琰杰 (Zhou Yanjie) unsigned rate_multiplier; 55b066303fSPaul Burton const s8 *od_encoding; 56b066303fSPaul Burton u8 m_shift, m_bits, m_offset; 57b066303fSPaul Burton u8 n_shift, n_bits, n_offset; 58b066303fSPaul Burton u8 od_shift, od_bits, od_max; 599d9cc58aS周琰杰 (Zhou Yanjie) unsigned bypass_reg; 60037f1ffdSPaul Cercueil s8 bypass_bit; 61d84bf9d6SAidan MacDonald s8 enable_bit; 62d84bf9d6SAidan MacDonald s8 stable_bit; 63b60b0b55SPaul Cercueil void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 64b60b0b55SPaul Cercueil unsigned long rate, unsigned long parent_rate, 65b60b0b55SPaul Cercueil unsigned int *m, unsigned int *n, unsigned int *od); 66*c799a777SAidan MacDonald void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info, 67*c799a777SAidan MacDonald unsigned long rate, unsigned long parent_rate); 68b066303fSPaul Burton }; 69b066303fSPaul Burton 70b066303fSPaul Burton /** 71b066303fSPaul Burton * struct ingenic_cgu_mux_info - information about a clock mux 72b066303fSPaul Burton * @reg: offset of the mux control register within the CGU 73b066303fSPaul Burton * @shift: number of bits to shift the mux value by (ie. the index of 74b066303fSPaul Burton * the lowest bit of the mux value within its control register) 75b066303fSPaul Burton * @bits: the size of the mux value in bits 76b066303fSPaul Burton */ 77b066303fSPaul Burton struct ingenic_cgu_mux_info { 78b066303fSPaul Burton unsigned reg; 79b066303fSPaul Burton u8 shift; 80b066303fSPaul Burton u8 bits; 81b066303fSPaul Burton }; 82b066303fSPaul Burton 83b066303fSPaul Burton /** 84b066303fSPaul Burton * struct ingenic_cgu_div_info - information about a divider 85b066303fSPaul Burton * @reg: offset of the divider control register within the CGU 864afe2d1aSHarvey Hunt * @shift: number of bits to left shift the divide value by (ie. the index of 87b066303fSPaul Burton * the lowest bit of the divide value within its control register) 887ca4c922SPaul Cercueil * @div: number to divide the divider value by (i.e. if the 894afe2d1aSHarvey Hunt * effective divider value is the value written to the register 904afe2d1aSHarvey Hunt * multiplied by some constant) 91b066303fSPaul Burton * @bits: the size of the divide value in bits 92b066303fSPaul Burton * @ce_bit: the index of the change enable bit within reg, or -1 if there 93b066303fSPaul Burton * isn't one 94b066303fSPaul Burton * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 95b066303fSPaul Burton * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 96249592bfSPaul Cercueil * @bypass_mask: mask of parent clocks for which the divider does not apply 97a9fa2893SPaul Cercueil * @div_table: optional table to map the value read from the register to the 98a9fa2893SPaul Cercueil * actual divider value 99b066303fSPaul Burton */ 100b066303fSPaul Burton struct ingenic_cgu_div_info { 101b066303fSPaul Burton unsigned reg; 102b066303fSPaul Burton u8 shift; 1034afe2d1aSHarvey Hunt u8 div; 104b066303fSPaul Burton u8 bits; 105b066303fSPaul Burton s8 ce_bit; 106b066303fSPaul Burton s8 busy_bit; 107b066303fSPaul Burton s8 stop_bit; 108249592bfSPaul Cercueil u8 bypass_mask; 109a9fa2893SPaul Cercueil const u8 *div_table; 110b066303fSPaul Burton }; 111b066303fSPaul Burton 112b066303fSPaul Burton /** 113b066303fSPaul Burton * struct ingenic_cgu_fixdiv_info - information about a fixed divider 114b066303fSPaul Burton * @div: the divider applied to the parent clock 115b066303fSPaul Burton */ 116b066303fSPaul Burton struct ingenic_cgu_fixdiv_info { 117b066303fSPaul Burton unsigned div; 118b066303fSPaul Burton }; 119b066303fSPaul Burton 120b066303fSPaul Burton /** 121b066303fSPaul Burton * struct ingenic_cgu_gate_info - information about a clock gate 122b066303fSPaul Burton * @reg: offset of the gate control register within the CGU 123b066303fSPaul Burton * @bit: offset of the bit in the register that controls the gate 1247ef3844fSPaul Cercueil * @clear_to_gate: if set, the clock is gated when the bit is cleared 125261a831fSPaul Cercueil * @delay_us: delay in microseconds after which the clock is considered stable 126b066303fSPaul Burton */ 127b066303fSPaul Burton struct ingenic_cgu_gate_info { 128b066303fSPaul Burton unsigned reg; 129b066303fSPaul Burton u8 bit; 1307ef3844fSPaul Cercueil bool clear_to_gate; 131261a831fSPaul Cercueil u16 delay_us; 132b066303fSPaul Burton }; 133b066303fSPaul Burton 134b066303fSPaul Burton /** 135b066303fSPaul Burton * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 136b066303fSPaul Burton * @clk_ops: custom clock operation callbacks 137b066303fSPaul Burton */ 138b066303fSPaul Burton struct ingenic_cgu_custom_info { 139ee1f9df2SPaul Cercueil const struct clk_ops *clk_ops; 140b066303fSPaul Burton }; 141b066303fSPaul Burton 142b066303fSPaul Burton /** 143b066303fSPaul Burton * struct ingenic_cgu_clk_info - information about a clock 144b066303fSPaul Burton * @name: name of the clock 145b066303fSPaul Burton * @type: a bitmask formed from CGU_CLK_* values 146bacf743eSAidan MacDonald * @flags: common clock flags to set on this clock 147b066303fSPaul Burton * @parents: an array of the indices of potential parents of this clock 148b066303fSPaul Burton * within the clock_info array of the CGU, or -1 in entries 149b066303fSPaul Burton * which correspond to no valid parent 150b066303fSPaul Burton * @pll: information valid if type includes CGU_CLK_PLL 151b066303fSPaul Burton * @gate: information valid if type includes CGU_CLK_GATE 152b066303fSPaul Burton * @mux: information valid if type includes CGU_CLK_MUX 153b066303fSPaul Burton * @div: information valid if type includes CGU_CLK_DIV 154b066303fSPaul Burton * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 155b066303fSPaul Burton * @custom: information valid if type includes CGU_CLK_CUSTOM 156b066303fSPaul Burton */ 157b066303fSPaul Burton struct ingenic_cgu_clk_info { 158b066303fSPaul Burton const char *name; 159b066303fSPaul Burton 160b066303fSPaul Burton enum { 161b066303fSPaul Burton CGU_CLK_NONE = 0, 162b066303fSPaul Burton CGU_CLK_EXT = BIT(0), 163b066303fSPaul Burton CGU_CLK_PLL = BIT(1), 164b066303fSPaul Burton CGU_CLK_GATE = BIT(2), 165b066303fSPaul Burton CGU_CLK_MUX = BIT(3), 166b066303fSPaul Burton CGU_CLK_MUX_GLITCHFREE = BIT(4), 167b066303fSPaul Burton CGU_CLK_DIV = BIT(5), 168b066303fSPaul Burton CGU_CLK_FIXDIV = BIT(6), 169b066303fSPaul Burton CGU_CLK_CUSTOM = BIT(7), 170b066303fSPaul Burton } type; 171b066303fSPaul Burton 172bacf743eSAidan MacDonald unsigned long flags; 173bacf743eSAidan MacDonald 174b066303fSPaul Burton int parents[4]; 175b066303fSPaul Burton 176b066303fSPaul Burton union { 177b066303fSPaul Burton struct ingenic_cgu_pll_info pll; 178b066303fSPaul Burton 179b066303fSPaul Burton struct { 180b066303fSPaul Burton struct ingenic_cgu_gate_info gate; 181b066303fSPaul Burton struct ingenic_cgu_mux_info mux; 182b066303fSPaul Burton struct ingenic_cgu_div_info div; 183b066303fSPaul Burton struct ingenic_cgu_fixdiv_info fixdiv; 184b066303fSPaul Burton }; 185b066303fSPaul Burton 186b066303fSPaul Burton struct ingenic_cgu_custom_info custom; 187b066303fSPaul Burton }; 188b066303fSPaul Burton }; 189b066303fSPaul Burton 190b066303fSPaul Burton /** 191b066303fSPaul Burton * struct ingenic_cgu - data about the CGU 192b066303fSPaul Burton * @np: the device tree node that caused the CGU to be probed 193b066303fSPaul Burton * @base: the ioremap'ed base address of the CGU registers 194b066303fSPaul Burton * @clock_info: an array containing information about implemented clocks 195b066303fSPaul Burton * @clocks: used to provide clocks to DT, allows lookup of struct clk* 196b066303fSPaul Burton * @lock: lock to be held whilst manipulating CGU registers 197b066303fSPaul Burton */ 198b066303fSPaul Burton struct ingenic_cgu { 199b066303fSPaul Burton struct device_node *np; 200b066303fSPaul Burton void __iomem *base; 201b066303fSPaul Burton 202b066303fSPaul Burton const struct ingenic_cgu_clk_info *clock_info; 203b066303fSPaul Burton struct clk_onecell_data clocks; 204b066303fSPaul Burton 205b066303fSPaul Burton spinlock_t lock; 206b066303fSPaul Burton }; 207b066303fSPaul Burton 208b066303fSPaul Burton /** 209b066303fSPaul Burton * struct ingenic_clk - private data for a clock 2105fb94e9cSMauro Carvalho Chehab * @hw: see Documentation/driver-api/clk.rst 211b066303fSPaul Burton * @cgu: a pointer to the CGU data 212b066303fSPaul Burton * @idx: the index of this clock in cgu->clock_info 213b066303fSPaul Burton */ 214b066303fSPaul Burton struct ingenic_clk { 215b066303fSPaul Burton struct clk_hw hw; 216b066303fSPaul Burton struct ingenic_cgu *cgu; 217b066303fSPaul Burton unsigned idx; 218b066303fSPaul Burton }; 219b066303fSPaul Burton 220b066303fSPaul Burton #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 221b066303fSPaul Burton 222b066303fSPaul Burton /** 223b066303fSPaul Burton * ingenic_cgu_new() - create a new CGU instance 224b066303fSPaul Burton * @clock_info: an array of clock information structures describing the clocks 225b066303fSPaul Burton * which are implemented by the CGU 226b066303fSPaul Burton * @num_clocks: the number of entries in clock_info 227b066303fSPaul Burton * @np: the device tree node which causes this CGU to be probed 228b066303fSPaul Burton * 229b066303fSPaul Burton * Return: a pointer to the CGU instance if initialisation is successful, 230b066303fSPaul Burton * otherwise NULL. 231b066303fSPaul Burton */ 232b066303fSPaul Burton struct ingenic_cgu * 233b066303fSPaul Burton ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 234b066303fSPaul Burton unsigned num_clocks, struct device_node *np); 235b066303fSPaul Burton 236b066303fSPaul Burton /** 237b066303fSPaul Burton * ingenic_cgu_register_clocks() - Registers the clocks 238b066303fSPaul Burton * @cgu: pointer to cgu data 239b066303fSPaul Burton * 240b066303fSPaul Burton * Register the clocks described by the CGU with the common clock framework. 241b066303fSPaul Burton * 242b066303fSPaul Burton * Return: 0 on success or -errno if unsuccesful. 243b066303fSPaul Burton */ 244b066303fSPaul Burton int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 245b066303fSPaul Burton 246b066303fSPaul Burton #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 247