1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk.h> 3 #include <linux/clk-provider.h> 4 #include <linux/err.h> 5 #include <linux/io.h> 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/slab.h> 9 #include <linux/spinlock.h> 10 #include "clk.h" 11 12 #define CCM_CCDR 0x4 13 #define CCDR_MMDC_CH0_MASK BIT(17) 14 #define CCDR_MMDC_CH1_MASK BIT(16) 15 16 DEFINE_SPINLOCK(imx_ccm_lock); 17 EXPORT_SYMBOL_GPL(imx_ccm_lock); 18 19 void imx_unregister_clocks(struct clk *clks[], unsigned int count) 20 { 21 unsigned int i; 22 23 for (i = 0; i < count; i++) 24 clk_unregister(clks[i]); 25 } 26 27 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count) 28 { 29 unsigned int i; 30 31 for (i = 0; i < count; i++) 32 clk_hw_unregister(hws[i]); 33 } 34 EXPORT_SYMBOL_GPL(imx_unregister_hw_clocks); 35 36 void imx_mmdc_mask_handshake(void __iomem *ccm_base, 37 unsigned int chn) 38 { 39 unsigned int reg; 40 41 reg = readl_relaxed(ccm_base + CCM_CCDR); 42 reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK; 43 writel_relaxed(reg, ccm_base + CCM_CCDR); 44 } 45 46 void imx_check_clocks(struct clk *clks[], unsigned int count) 47 { 48 unsigned i; 49 50 for (i = 0; i < count; i++) 51 if (IS_ERR(clks[i])) 52 pr_err("i.MX clk %u: register failed with %ld\n", 53 i, PTR_ERR(clks[i])); 54 } 55 56 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) 57 { 58 unsigned int i; 59 60 for (i = 0; i < count; i++) 61 if (IS_ERR(clks[i])) 62 pr_err("i.MX clk %u: register failed with %ld\n", 63 i, PTR_ERR(clks[i])); 64 } 65 EXPORT_SYMBOL_GPL(imx_check_clk_hws); 66 67 static struct clk *imx_obtain_fixed_clock_from_dt(const char *name) 68 { 69 struct of_phandle_args phandle; 70 struct clk *clk = ERR_PTR(-ENODEV); 71 char *path; 72 73 path = kasprintf(GFP_KERNEL, "/clocks/%s", name); 74 if (!path) 75 return ERR_PTR(-ENOMEM); 76 77 phandle.np = of_find_node_by_path(path); 78 kfree(path); 79 80 if (phandle.np) { 81 clk = of_clk_get_from_provider(&phandle); 82 of_node_put(phandle.np); 83 } 84 return clk; 85 } 86 87 struct clk *imx_obtain_fixed_clock( 88 const char *name, unsigned long rate) 89 { 90 struct clk *clk; 91 92 clk = imx_obtain_fixed_clock_from_dt(name); 93 if (IS_ERR(clk)) 94 clk = imx_clk_fixed(name, rate); 95 return clk; 96 } 97 98 struct clk_hw *imx_obtain_fixed_clock_hw( 99 const char *name, unsigned long rate) 100 { 101 struct clk *clk; 102 103 clk = imx_obtain_fixed_clock_from_dt(name); 104 if (IS_ERR(clk)) 105 clk = imx_clk_fixed(name, rate); 106 return __clk_get_hw(clk); 107 } 108 109 struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, 110 const char *name) 111 { 112 struct clk *clk; 113 114 clk = of_clk_get_by_name(np, name); 115 if (IS_ERR(clk)) 116 return ERR_PTR(-ENOENT); 117 118 return __clk_get_hw(clk); 119 } 120 EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw); 121 122 /* 123 * This fixups the register CCM_CSCMR1 write value. 124 * The write/read/divider values of the aclk_podf field 125 * of that register have the relationship described by 126 * the following table: 127 * 128 * write value read value divider 129 * 3b'000 3b'110 7 130 * 3b'001 3b'111 8 131 * 3b'010 3b'100 5 132 * 3b'011 3b'101 6 133 * 3b'100 3b'010 3 134 * 3b'101 3b'011 4 135 * 3b'110 3b'000 1 136 * 3b'111 3b'001 2(default) 137 * 138 * That's why we do the xor operation below. 139 */ 140 #define CSCMR1_FIXUP 0x00600000 141 142 void imx_cscmr1_fixup(u32 *val) 143 { 144 *val ^= CSCMR1_FIXUP; 145 return; 146 } 147 148 #ifndef MODULE 149 static int imx_keep_uart_clocks; 150 static struct clk ** const *imx_uart_clocks; 151 152 static int __init imx_keep_uart_clocks_param(char *str) 153 { 154 imx_keep_uart_clocks = 1; 155 156 return 0; 157 } 158 __setup_param("earlycon", imx_keep_uart_earlycon, 159 imx_keep_uart_clocks_param, 0); 160 __setup_param("earlyprintk", imx_keep_uart_earlyprintk, 161 imx_keep_uart_clocks_param, 0); 162 163 void imx_register_uart_clocks(struct clk ** const clks[]) 164 { 165 if (imx_keep_uart_clocks) { 166 int i; 167 168 imx_uart_clocks = clks; 169 for (i = 0; imx_uart_clocks[i]; i++) 170 clk_prepare_enable(*imx_uart_clocks[i]); 171 } 172 } 173 174 static int __init imx_clk_disable_uart(void) 175 { 176 if (imx_keep_uart_clocks && imx_uart_clocks) { 177 int i; 178 179 for (i = 0; imx_uart_clocks[i]; i++) 180 clk_disable_unprepare(*imx_uart_clocks[i]); 181 } 182 183 return 0; 184 } 185 late_initcall_sync(imx_clk_disable_uart); 186 #endif 187 188 MODULE_LICENSE("GPL v2"); 189