1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2012 Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/slab.h> 12 #include <linux/jiffies.h> 13 #include <linux/err.h> 14 #include "clk.h" 15 16 #define PLL_NUM_OFFSET 0x10 17 #define PLL_DENOM_OFFSET 0x20 18 #define PLL_IMX7_NUM_OFFSET 0x20 19 #define PLL_IMX7_DENOM_OFFSET 0x30 20 21 #define PLL_VF610_NUM_OFFSET 0x20 22 #define PLL_VF610_DENOM_OFFSET 0x30 23 24 #define BM_PLL_POWER (0x1 << 12) 25 #define BM_PLL_LOCK (0x1 << 31) 26 #define IMX7_ENET_PLL_POWER (0x1 << 5) 27 #define IMX7_DDR_PLL_POWER (0x1 << 20) 28 29 #define PLL_LOCK_TIMEOUT 10000 30 31 /** 32 * struct clk_pllv3 - IMX PLL clock version 3 33 * @clk_hw: clock source 34 * @base: base address of PLL registers 35 * @power_bit: pll power bit mask 36 * @powerup_set: set power_bit to power up the PLL 37 * @div_mask: mask of divider bits 38 * @div_shift: shift of divider bits 39 * 40 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 41 * is actually a multiplier, and always sits at bit 0. 42 */ 43 struct clk_pllv3 { 44 struct clk_hw hw; 45 void __iomem *base; 46 u32 power_bit; 47 bool powerup_set; 48 u32 div_mask; 49 u32 div_shift; 50 unsigned long ref_clock; 51 u32 num_offset; 52 u32 denom_offset; 53 }; 54 55 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 56 57 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 58 { 59 u32 val = readl_relaxed(pll->base) & pll->power_bit; 60 61 /* No need to wait for lock when pll is not powered up */ 62 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 63 return 0; 64 65 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, 66 500, PLL_LOCK_TIMEOUT); 67 } 68 69 static int clk_pllv3_prepare(struct clk_hw *hw) 70 { 71 struct clk_pllv3 *pll = to_clk_pllv3(hw); 72 u32 val; 73 74 val = readl_relaxed(pll->base); 75 if (pll->powerup_set) 76 val |= pll->power_bit; 77 else 78 val &= ~pll->power_bit; 79 writel_relaxed(val, pll->base); 80 81 return clk_pllv3_wait_lock(pll); 82 } 83 84 static void clk_pllv3_unprepare(struct clk_hw *hw) 85 { 86 struct clk_pllv3 *pll = to_clk_pllv3(hw); 87 u32 val; 88 89 val = readl_relaxed(pll->base); 90 if (pll->powerup_set) 91 val &= ~pll->power_bit; 92 else 93 val |= pll->power_bit; 94 writel_relaxed(val, pll->base); 95 } 96 97 static int clk_pllv3_is_prepared(struct clk_hw *hw) 98 { 99 struct clk_pllv3 *pll = to_clk_pllv3(hw); 100 101 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 102 return 1; 103 104 return 0; 105 } 106 107 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 108 unsigned long parent_rate) 109 { 110 struct clk_pllv3 *pll = to_clk_pllv3(hw); 111 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 112 113 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 114 } 115 116 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, 117 unsigned long *prate) 118 { 119 unsigned long parent_rate = *prate; 120 121 return (rate >= parent_rate * 22) ? parent_rate * 22 : 122 parent_rate * 20; 123 } 124 125 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 126 unsigned long parent_rate) 127 { 128 struct clk_pllv3 *pll = to_clk_pllv3(hw); 129 u32 val, div; 130 131 if (rate == parent_rate * 22) 132 div = 1; 133 else if (rate == parent_rate * 20) 134 div = 0; 135 else 136 return -EINVAL; 137 138 val = readl_relaxed(pll->base); 139 val &= ~(pll->div_mask << pll->div_shift); 140 val |= (div << pll->div_shift); 141 writel_relaxed(val, pll->base); 142 143 return clk_pllv3_wait_lock(pll); 144 } 145 146 static const struct clk_ops clk_pllv3_ops = { 147 .prepare = clk_pllv3_prepare, 148 .unprepare = clk_pllv3_unprepare, 149 .is_prepared = clk_pllv3_is_prepared, 150 .recalc_rate = clk_pllv3_recalc_rate, 151 .round_rate = clk_pllv3_round_rate, 152 .set_rate = clk_pllv3_set_rate, 153 }; 154 155 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, 156 unsigned long parent_rate) 157 { 158 struct clk_pllv3 *pll = to_clk_pllv3(hw); 159 u32 div = readl_relaxed(pll->base) & pll->div_mask; 160 161 return parent_rate * div / 2; 162 } 163 164 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, 165 unsigned long *prate) 166 { 167 unsigned long parent_rate = *prate; 168 unsigned long min_rate = parent_rate * 54 / 2; 169 unsigned long max_rate = parent_rate * 108 / 2; 170 u32 div; 171 172 if (rate > max_rate) 173 rate = max_rate; 174 else if (rate < min_rate) 175 rate = min_rate; 176 div = rate * 2 / parent_rate; 177 178 return parent_rate * div / 2; 179 } 180 181 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, 182 unsigned long parent_rate) 183 { 184 struct clk_pllv3 *pll = to_clk_pllv3(hw); 185 unsigned long min_rate = parent_rate * 54 / 2; 186 unsigned long max_rate = parent_rate * 108 / 2; 187 u32 val, div; 188 189 if (rate < min_rate || rate > max_rate) 190 return -EINVAL; 191 192 div = rate * 2 / parent_rate; 193 val = readl_relaxed(pll->base); 194 val &= ~pll->div_mask; 195 val |= div; 196 writel_relaxed(val, pll->base); 197 198 return clk_pllv3_wait_lock(pll); 199 } 200 201 static const struct clk_ops clk_pllv3_sys_ops = { 202 .prepare = clk_pllv3_prepare, 203 .unprepare = clk_pllv3_unprepare, 204 .is_prepared = clk_pllv3_is_prepared, 205 .recalc_rate = clk_pllv3_sys_recalc_rate, 206 .round_rate = clk_pllv3_sys_round_rate, 207 .set_rate = clk_pllv3_sys_set_rate, 208 }; 209 210 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 211 unsigned long parent_rate) 212 { 213 struct clk_pllv3 *pll = to_clk_pllv3(hw); 214 u32 mfn = readl_relaxed(pll->base + pll->num_offset); 215 u32 mfd = readl_relaxed(pll->base + pll->denom_offset); 216 u32 div = readl_relaxed(pll->base) & pll->div_mask; 217 u64 temp64 = (u64)parent_rate; 218 219 temp64 *= mfn; 220 do_div(temp64, mfd); 221 222 return parent_rate * div + (unsigned long)temp64; 223 } 224 225 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 226 unsigned long *prate) 227 { 228 unsigned long parent_rate = *prate; 229 unsigned long min_rate = parent_rate * 27; 230 unsigned long max_rate = parent_rate * 54; 231 u32 div; 232 u32 mfn, mfd = 1000000; 233 u32 max_mfd = 0x3FFFFFFF; 234 u64 temp64; 235 236 if (rate > max_rate) 237 rate = max_rate; 238 else if (rate < min_rate) 239 rate = min_rate; 240 241 if (parent_rate <= max_mfd) 242 mfd = parent_rate; 243 244 div = rate / parent_rate; 245 temp64 = (u64) (rate - div * parent_rate); 246 temp64 *= mfd; 247 do_div(temp64, parent_rate); 248 mfn = temp64; 249 250 temp64 = (u64)parent_rate; 251 temp64 *= mfn; 252 do_div(temp64, mfd); 253 254 return parent_rate * div + (unsigned long)temp64; 255 } 256 257 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 258 unsigned long parent_rate) 259 { 260 struct clk_pllv3 *pll = to_clk_pllv3(hw); 261 unsigned long min_rate = parent_rate * 27; 262 unsigned long max_rate = parent_rate * 54; 263 u32 val, div; 264 u32 mfn, mfd = 1000000; 265 u32 max_mfd = 0x3FFFFFFF; 266 u64 temp64; 267 268 if (rate < min_rate || rate > max_rate) 269 return -EINVAL; 270 271 if (parent_rate <= max_mfd) 272 mfd = parent_rate; 273 274 div = rate / parent_rate; 275 temp64 = (u64) (rate - div * parent_rate); 276 temp64 *= mfd; 277 do_div(temp64, parent_rate); 278 mfn = temp64; 279 280 val = readl_relaxed(pll->base); 281 val &= ~pll->div_mask; 282 val |= div; 283 writel_relaxed(val, pll->base); 284 writel_relaxed(mfn, pll->base + pll->num_offset); 285 writel_relaxed(mfd, pll->base + pll->denom_offset); 286 287 return clk_pllv3_wait_lock(pll); 288 } 289 290 static const struct clk_ops clk_pllv3_av_ops = { 291 .prepare = clk_pllv3_prepare, 292 .unprepare = clk_pllv3_unprepare, 293 .is_prepared = clk_pllv3_is_prepared, 294 .recalc_rate = clk_pllv3_av_recalc_rate, 295 .round_rate = clk_pllv3_av_round_rate, 296 .set_rate = clk_pllv3_av_set_rate, 297 }; 298 299 struct clk_pllv3_vf610_mf { 300 u32 mfi; /* integer part, can be 20 or 22 */ 301 u32 mfn; /* numerator, 30-bit value */ 302 u32 mfd; /* denominator, 30-bit value, must be less than mfn */ 303 }; 304 305 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate, 306 struct clk_pllv3_vf610_mf mf) 307 { 308 u64 temp64; 309 310 temp64 = parent_rate; 311 temp64 *= mf.mfn; 312 do_div(temp64, mf.mfd); 313 314 return (parent_rate * mf.mfi) + temp64; 315 } 316 317 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( 318 unsigned long parent_rate, unsigned long rate) 319 { 320 struct clk_pllv3_vf610_mf mf; 321 u64 temp64; 322 323 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20; 324 mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */ 325 326 if (rate <= parent_rate * mf.mfi) 327 mf.mfn = 0; 328 else if (rate >= parent_rate * (mf.mfi + 1)) 329 mf.mfn = mf.mfd - 1; 330 else { 331 /* rate = parent_rate * (mfi + mfn/mfd) */ 332 temp64 = rate - parent_rate * mf.mfi; 333 temp64 *= mf.mfd; 334 do_div(temp64, parent_rate); 335 mf.mfn = temp64; 336 } 337 338 return mf; 339 } 340 341 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, 342 unsigned long parent_rate) 343 { 344 struct clk_pllv3 *pll = to_clk_pllv3(hw); 345 struct clk_pllv3_vf610_mf mf; 346 347 mf.mfn = readl_relaxed(pll->base + pll->num_offset); 348 mf.mfd = readl_relaxed(pll->base + pll->denom_offset); 349 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; 350 351 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf); 352 } 353 354 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate, 355 unsigned long *prate) 356 { 357 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate); 358 359 return clk_pllv3_vf610_mf_to_rate(*prate, mf); 360 } 361 362 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, 363 unsigned long parent_rate) 364 { 365 struct clk_pllv3 *pll = to_clk_pllv3(hw); 366 struct clk_pllv3_vf610_mf mf = 367 clk_pllv3_vf610_rate_to_mf(parent_rate, rate); 368 u32 val; 369 370 val = readl_relaxed(pll->base); 371 if (mf.mfi == 20) 372 val &= ~pll->div_mask; /* clear bit for mfi=20 */ 373 else 374 val |= pll->div_mask; /* set bit for mfi=22 */ 375 writel_relaxed(val, pll->base); 376 377 writel_relaxed(mf.mfn, pll->base + pll->num_offset); 378 writel_relaxed(mf.mfd, pll->base + pll->denom_offset); 379 380 return clk_pllv3_wait_lock(pll); 381 } 382 383 static const struct clk_ops clk_pllv3_vf610_ops = { 384 .prepare = clk_pllv3_prepare, 385 .unprepare = clk_pllv3_unprepare, 386 .is_prepared = clk_pllv3_is_prepared, 387 .recalc_rate = clk_pllv3_vf610_recalc_rate, 388 .round_rate = clk_pllv3_vf610_round_rate, 389 .set_rate = clk_pllv3_vf610_set_rate, 390 }; 391 392 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 393 unsigned long parent_rate) 394 { 395 struct clk_pllv3 *pll = to_clk_pllv3(hw); 396 397 return pll->ref_clock; 398 } 399 400 static const struct clk_ops clk_pllv3_enet_ops = { 401 .prepare = clk_pllv3_prepare, 402 .unprepare = clk_pllv3_unprepare, 403 .is_prepared = clk_pllv3_is_prepared, 404 .recalc_rate = clk_pllv3_enet_recalc_rate, 405 }; 406 407 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, 408 const char *parent_name, void __iomem *base, 409 u32 div_mask) 410 { 411 struct clk_pllv3 *pll; 412 const struct clk_ops *ops; 413 struct clk_hw *hw; 414 struct clk_init_data init; 415 int ret; 416 417 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 418 if (!pll) 419 return ERR_PTR(-ENOMEM); 420 421 pll->power_bit = BM_PLL_POWER; 422 pll->num_offset = PLL_NUM_OFFSET; 423 pll->denom_offset = PLL_DENOM_OFFSET; 424 425 switch (type) { 426 case IMX_PLLV3_SYS: 427 ops = &clk_pllv3_sys_ops; 428 break; 429 case IMX_PLLV3_SYS_VF610: 430 ops = &clk_pllv3_vf610_ops; 431 pll->num_offset = PLL_VF610_NUM_OFFSET; 432 pll->denom_offset = PLL_VF610_DENOM_OFFSET; 433 break; 434 case IMX_PLLV3_USB_VF610: 435 pll->div_shift = 1; 436 fallthrough; 437 case IMX_PLLV3_USB: 438 ops = &clk_pllv3_ops; 439 pll->powerup_set = true; 440 break; 441 case IMX_PLLV3_AV_IMX7: 442 pll->num_offset = PLL_IMX7_NUM_OFFSET; 443 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 444 fallthrough; 445 case IMX_PLLV3_AV: 446 ops = &clk_pllv3_av_ops; 447 break; 448 case IMX_PLLV3_ENET_IMX7: 449 pll->power_bit = IMX7_ENET_PLL_POWER; 450 pll->ref_clock = 1000000000; 451 ops = &clk_pllv3_enet_ops; 452 break; 453 case IMX_PLLV3_ENET: 454 pll->ref_clock = 500000000; 455 ops = &clk_pllv3_enet_ops; 456 break; 457 case IMX_PLLV3_DDR_IMX7: 458 pll->power_bit = IMX7_DDR_PLL_POWER; 459 pll->num_offset = PLL_IMX7_NUM_OFFSET; 460 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 461 ops = &clk_pllv3_av_ops; 462 break; 463 default: 464 ops = &clk_pllv3_ops; 465 } 466 pll->base = base; 467 pll->div_mask = div_mask; 468 469 init.name = name; 470 init.ops = ops; 471 init.flags = 0; 472 init.parent_names = &parent_name; 473 init.num_parents = 1; 474 475 pll->hw.init = &init; 476 hw = &pll->hw; 477 478 ret = clk_hw_register(NULL, hw); 479 if (ret) { 480 kfree(pll); 481 return ERR_PTR(ret); 482 } 483 484 return hw; 485 } 486