1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Copyright 2012 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/slab.h> 17 #include <linux/jiffies.h> 18 #include <linux/err.h> 19 #include "clk.h" 20 21 #define PLL_NUM_OFFSET 0x10 22 #define PLL_DENOM_OFFSET 0x20 23 #define PLL_IMX7_NUM_OFFSET 0x20 24 #define PLL_IMX7_DENOM_OFFSET 0x30 25 26 #define PLL_VF610_NUM_OFFSET 0x20 27 #define PLL_VF610_DENOM_OFFSET 0x30 28 29 #define BM_PLL_POWER (0x1 << 12) 30 #define BM_PLL_LOCK (0x1 << 31) 31 #define IMX7_ENET_PLL_POWER (0x1 << 5) 32 #define IMX7_DDR_PLL_POWER (0x1 << 20) 33 34 /** 35 * struct clk_pllv3 - IMX PLL clock version 3 36 * @clk_hw: clock source 37 * @base: base address of PLL registers 38 * @power_bit: pll power bit mask 39 * @powerup_set: set power_bit to power up the PLL 40 * @div_mask: mask of divider bits 41 * @div_shift: shift of divider bits 42 * 43 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 44 * is actually a multiplier, and always sits at bit 0. 45 */ 46 struct clk_pllv3 { 47 struct clk_hw hw; 48 void __iomem *base; 49 u32 power_bit; 50 bool powerup_set; 51 u32 div_mask; 52 u32 div_shift; 53 unsigned long ref_clock; 54 u32 num_offset; 55 u32 denom_offset; 56 }; 57 58 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 59 60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 61 { 62 unsigned long timeout = jiffies + msecs_to_jiffies(10); 63 u32 val = readl_relaxed(pll->base) & pll->power_bit; 64 65 /* No need to wait for lock when pll is not powered up */ 66 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 67 return 0; 68 69 /* Wait for PLL to lock */ 70 do { 71 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 72 break; 73 if (time_after(jiffies, timeout)) 74 break; 75 usleep_range(50, 500); 76 } while (1); 77 78 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; 79 } 80 81 static int clk_pllv3_prepare(struct clk_hw *hw) 82 { 83 struct clk_pllv3 *pll = to_clk_pllv3(hw); 84 u32 val; 85 86 val = readl_relaxed(pll->base); 87 if (pll->powerup_set) 88 val |= pll->power_bit; 89 else 90 val &= ~pll->power_bit; 91 writel_relaxed(val, pll->base); 92 93 return clk_pllv3_wait_lock(pll); 94 } 95 96 static void clk_pllv3_unprepare(struct clk_hw *hw) 97 { 98 struct clk_pllv3 *pll = to_clk_pllv3(hw); 99 u32 val; 100 101 val = readl_relaxed(pll->base); 102 if (pll->powerup_set) 103 val &= ~pll->power_bit; 104 else 105 val |= pll->power_bit; 106 writel_relaxed(val, pll->base); 107 } 108 109 static int clk_pllv3_is_prepared(struct clk_hw *hw) 110 { 111 struct clk_pllv3 *pll = to_clk_pllv3(hw); 112 113 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 114 return 1; 115 116 return 0; 117 } 118 119 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 120 unsigned long parent_rate) 121 { 122 struct clk_pllv3 *pll = to_clk_pllv3(hw); 123 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 124 125 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 126 } 127 128 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, 129 unsigned long *prate) 130 { 131 unsigned long parent_rate = *prate; 132 133 return (rate >= parent_rate * 22) ? parent_rate * 22 : 134 parent_rate * 20; 135 } 136 137 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 138 unsigned long parent_rate) 139 { 140 struct clk_pllv3 *pll = to_clk_pllv3(hw); 141 u32 val, div; 142 143 if (rate == parent_rate * 22) 144 div = 1; 145 else if (rate == parent_rate * 20) 146 div = 0; 147 else 148 return -EINVAL; 149 150 val = readl_relaxed(pll->base); 151 val &= ~(pll->div_mask << pll->div_shift); 152 val |= (div << pll->div_shift); 153 writel_relaxed(val, pll->base); 154 155 return clk_pllv3_wait_lock(pll); 156 } 157 158 static const struct clk_ops clk_pllv3_ops = { 159 .prepare = clk_pllv3_prepare, 160 .unprepare = clk_pllv3_unprepare, 161 .is_prepared = clk_pllv3_is_prepared, 162 .recalc_rate = clk_pllv3_recalc_rate, 163 .round_rate = clk_pllv3_round_rate, 164 .set_rate = clk_pllv3_set_rate, 165 }; 166 167 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, 168 unsigned long parent_rate) 169 { 170 struct clk_pllv3 *pll = to_clk_pllv3(hw); 171 u32 div = readl_relaxed(pll->base) & pll->div_mask; 172 173 return parent_rate * div / 2; 174 } 175 176 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, 177 unsigned long *prate) 178 { 179 unsigned long parent_rate = *prate; 180 unsigned long min_rate = parent_rate * 54 / 2; 181 unsigned long max_rate = parent_rate * 108 / 2; 182 u32 div; 183 184 if (rate > max_rate) 185 rate = max_rate; 186 else if (rate < min_rate) 187 rate = min_rate; 188 div = rate * 2 / parent_rate; 189 190 return parent_rate * div / 2; 191 } 192 193 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, 194 unsigned long parent_rate) 195 { 196 struct clk_pllv3 *pll = to_clk_pllv3(hw); 197 unsigned long min_rate = parent_rate * 54 / 2; 198 unsigned long max_rate = parent_rate * 108 / 2; 199 u32 val, div; 200 201 if (rate < min_rate || rate > max_rate) 202 return -EINVAL; 203 204 div = rate * 2 / parent_rate; 205 val = readl_relaxed(pll->base); 206 val &= ~pll->div_mask; 207 val |= div; 208 writel_relaxed(val, pll->base); 209 210 return clk_pllv3_wait_lock(pll); 211 } 212 213 static const struct clk_ops clk_pllv3_sys_ops = { 214 .prepare = clk_pllv3_prepare, 215 .unprepare = clk_pllv3_unprepare, 216 .is_prepared = clk_pllv3_is_prepared, 217 .recalc_rate = clk_pllv3_sys_recalc_rate, 218 .round_rate = clk_pllv3_sys_round_rate, 219 .set_rate = clk_pllv3_sys_set_rate, 220 }; 221 222 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 223 unsigned long parent_rate) 224 { 225 struct clk_pllv3 *pll = to_clk_pllv3(hw); 226 u32 mfn = readl_relaxed(pll->base + pll->num_offset); 227 u32 mfd = readl_relaxed(pll->base + pll->denom_offset); 228 u32 div = readl_relaxed(pll->base) & pll->div_mask; 229 u64 temp64 = (u64)parent_rate; 230 231 temp64 *= mfn; 232 do_div(temp64, mfd); 233 234 return parent_rate * div + (unsigned long)temp64; 235 } 236 237 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 238 unsigned long *prate) 239 { 240 unsigned long parent_rate = *prate; 241 unsigned long min_rate = parent_rate * 27; 242 unsigned long max_rate = parent_rate * 54; 243 u32 div; 244 u32 mfn, mfd = 1000000; 245 u32 max_mfd = 0x3FFFFFFF; 246 u64 temp64; 247 248 if (rate > max_rate) 249 rate = max_rate; 250 else if (rate < min_rate) 251 rate = min_rate; 252 253 if (parent_rate <= max_mfd) 254 mfd = parent_rate; 255 256 div = rate / parent_rate; 257 temp64 = (u64) (rate - div * parent_rate); 258 temp64 *= mfd; 259 do_div(temp64, parent_rate); 260 mfn = temp64; 261 262 temp64 = (u64)parent_rate; 263 temp64 *= mfn; 264 do_div(temp64, mfd); 265 266 return parent_rate * div + (unsigned long)temp64; 267 } 268 269 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 270 unsigned long parent_rate) 271 { 272 struct clk_pllv3 *pll = to_clk_pllv3(hw); 273 unsigned long min_rate = parent_rate * 27; 274 unsigned long max_rate = parent_rate * 54; 275 u32 val, div; 276 u32 mfn, mfd = 1000000; 277 u32 max_mfd = 0x3FFFFFFF; 278 u64 temp64; 279 280 if (rate < min_rate || rate > max_rate) 281 return -EINVAL; 282 283 if (parent_rate <= max_mfd) 284 mfd = parent_rate; 285 286 div = rate / parent_rate; 287 temp64 = (u64) (rate - div * parent_rate); 288 temp64 *= mfd; 289 do_div(temp64, parent_rate); 290 mfn = temp64; 291 292 val = readl_relaxed(pll->base); 293 val &= ~pll->div_mask; 294 val |= div; 295 writel_relaxed(val, pll->base); 296 writel_relaxed(mfn, pll->base + pll->num_offset); 297 writel_relaxed(mfd, pll->base + pll->denom_offset); 298 299 return clk_pllv3_wait_lock(pll); 300 } 301 302 static const struct clk_ops clk_pllv3_av_ops = { 303 .prepare = clk_pllv3_prepare, 304 .unprepare = clk_pllv3_unprepare, 305 .is_prepared = clk_pllv3_is_prepared, 306 .recalc_rate = clk_pllv3_av_recalc_rate, 307 .round_rate = clk_pllv3_av_round_rate, 308 .set_rate = clk_pllv3_av_set_rate, 309 }; 310 311 struct clk_pllv3_vf610_mf { 312 u32 mfi; /* integer part, can be 20 or 22 */ 313 u32 mfn; /* numerator, 30-bit value */ 314 u32 mfd; /* denominator, 30-bit value, must be less than mfn */ 315 }; 316 317 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate, 318 struct clk_pllv3_vf610_mf mf) 319 { 320 u64 temp64; 321 322 temp64 = parent_rate; 323 temp64 *= mf.mfn; 324 do_div(temp64, mf.mfd); 325 326 return (parent_rate * mf.mfi) + temp64; 327 } 328 329 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf( 330 unsigned long parent_rate, unsigned long rate) 331 { 332 struct clk_pllv3_vf610_mf mf; 333 u64 temp64; 334 335 mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20; 336 mf.mfd = 0x3fffffff; /* use max supported value for best accuracy */ 337 338 if (rate <= parent_rate * mf.mfi) 339 mf.mfn = 0; 340 else if (rate >= parent_rate * (mf.mfi + 1)) 341 mf.mfn = mf.mfd - 1; 342 else { 343 /* rate = parent_rate * (mfi + mfn/mfd) */ 344 temp64 = rate - parent_rate * mf.mfi; 345 temp64 *= mf.mfd; 346 do_div(temp64, parent_rate); 347 mf.mfn = temp64; 348 } 349 350 return mf; 351 } 352 353 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, 354 unsigned long parent_rate) 355 { 356 struct clk_pllv3 *pll = to_clk_pllv3(hw); 357 struct clk_pllv3_vf610_mf mf; 358 359 mf.mfn = readl_relaxed(pll->base + pll->num_offset); 360 mf.mfd = readl_relaxed(pll->base + pll->denom_offset); 361 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; 362 363 return clk_pllv3_vf610_mf_to_rate(parent_rate, mf); 364 } 365 366 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate, 367 unsigned long *prate) 368 { 369 struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate); 370 371 return clk_pllv3_vf610_mf_to_rate(*prate, mf); 372 } 373 374 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, 375 unsigned long parent_rate) 376 { 377 struct clk_pllv3 *pll = to_clk_pllv3(hw); 378 struct clk_pllv3_vf610_mf mf = 379 clk_pllv3_vf610_rate_to_mf(parent_rate, rate); 380 u32 val; 381 382 val = readl_relaxed(pll->base); 383 if (mf.mfi == 20) 384 val &= ~pll->div_mask; /* clear bit for mfi=20 */ 385 else 386 val |= pll->div_mask; /* set bit for mfi=22 */ 387 writel_relaxed(val, pll->base); 388 389 writel_relaxed(mf.mfn, pll->base + pll->num_offset); 390 writel_relaxed(mf.mfd, pll->base + pll->denom_offset); 391 392 return clk_pllv3_wait_lock(pll); 393 } 394 395 static const struct clk_ops clk_pllv3_vf610_ops = { 396 .prepare = clk_pllv3_prepare, 397 .unprepare = clk_pllv3_unprepare, 398 .is_prepared = clk_pllv3_is_prepared, 399 .recalc_rate = clk_pllv3_vf610_recalc_rate, 400 .round_rate = clk_pllv3_vf610_round_rate, 401 .set_rate = clk_pllv3_vf610_set_rate, 402 }; 403 404 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 405 unsigned long parent_rate) 406 { 407 struct clk_pllv3 *pll = to_clk_pllv3(hw); 408 409 return pll->ref_clock; 410 } 411 412 static const struct clk_ops clk_pllv3_enet_ops = { 413 .prepare = clk_pllv3_prepare, 414 .unprepare = clk_pllv3_unprepare, 415 .is_prepared = clk_pllv3_is_prepared, 416 .recalc_rate = clk_pllv3_enet_recalc_rate, 417 }; 418 419 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 420 const char *parent_name, void __iomem *base, 421 u32 div_mask) 422 { 423 struct clk_pllv3 *pll; 424 const struct clk_ops *ops; 425 struct clk *clk; 426 struct clk_init_data init; 427 428 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 429 if (!pll) 430 return ERR_PTR(-ENOMEM); 431 432 pll->power_bit = BM_PLL_POWER; 433 pll->num_offset = PLL_NUM_OFFSET; 434 pll->denom_offset = PLL_DENOM_OFFSET; 435 436 switch (type) { 437 case IMX_PLLV3_SYS: 438 ops = &clk_pllv3_sys_ops; 439 break; 440 case IMX_PLLV3_SYS_VF610: 441 ops = &clk_pllv3_vf610_ops; 442 pll->num_offset = PLL_VF610_NUM_OFFSET; 443 pll->denom_offset = PLL_VF610_DENOM_OFFSET; 444 break; 445 case IMX_PLLV3_USB_VF610: 446 pll->div_shift = 1; 447 /* fall through */ 448 case IMX_PLLV3_USB: 449 ops = &clk_pllv3_ops; 450 pll->powerup_set = true; 451 break; 452 case IMX_PLLV3_AV_IMX7: 453 pll->num_offset = PLL_IMX7_NUM_OFFSET; 454 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 455 /* fall through */ 456 case IMX_PLLV3_AV: 457 ops = &clk_pllv3_av_ops; 458 break; 459 case IMX_PLLV3_ENET_IMX7: 460 pll->power_bit = IMX7_ENET_PLL_POWER; 461 pll->ref_clock = 1000000000; 462 ops = &clk_pllv3_enet_ops; 463 break; 464 case IMX_PLLV3_ENET: 465 pll->ref_clock = 500000000; 466 ops = &clk_pllv3_enet_ops; 467 break; 468 case IMX_PLLV3_DDR_IMX7: 469 pll->power_bit = IMX7_DDR_PLL_POWER; 470 pll->num_offset = PLL_IMX7_NUM_OFFSET; 471 pll->denom_offset = PLL_IMX7_DENOM_OFFSET; 472 ops = &clk_pllv3_av_ops; 473 break; 474 default: 475 ops = &clk_pllv3_ops; 476 } 477 pll->base = base; 478 pll->div_mask = div_mask; 479 480 init.name = name; 481 init.ops = ops; 482 init.flags = 0; 483 init.parent_names = &parent_name; 484 init.num_parents = 1; 485 486 pll->hw.init = &init; 487 488 clk = clk_register(NULL, &pll->hw); 489 if (IS_ERR(clk)) 490 kfree(pll); 491 492 return clk; 493 } 494