1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Copyright 2012 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/slab.h> 17 #include <linux/jiffies.h> 18 #include <linux/err.h> 19 #include "clk.h" 20 21 #define PLL_NUM_OFFSET 0x10 22 #define PLL_DENOM_OFFSET 0x20 23 24 #define BM_PLL_POWER (0x1 << 12) 25 #define BM_PLL_LOCK (0x1 << 31) 26 #define IMX7_ENET_PLL_POWER (0x1 << 5) 27 28 /** 29 * struct clk_pllv3 - IMX PLL clock version 3 30 * @clk_hw: clock source 31 * @base: base address of PLL registers 32 * @powerup_set: set POWER bit to power up the PLL 33 * @powerdown: pll powerdown offset bit 34 * @div_mask: mask of divider bits 35 * @div_shift: shift of divider bits 36 * 37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 38 * is actually a multiplier, and always sits at bit 0. 39 */ 40 struct clk_pllv3 { 41 struct clk_hw hw; 42 void __iomem *base; 43 bool powerup_set; 44 u32 powerdown; 45 u32 div_mask; 46 u32 div_shift; 47 unsigned long ref_clock; 48 }; 49 50 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 51 52 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 53 { 54 unsigned long timeout = jiffies + msecs_to_jiffies(10); 55 u32 val = readl_relaxed(pll->base) & pll->powerdown; 56 57 /* No need to wait for lock when pll is not powered up */ 58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 59 return 0; 60 61 /* Wait for PLL to lock */ 62 do { 63 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 64 break; 65 if (time_after(jiffies, timeout)) 66 break; 67 usleep_range(50, 500); 68 } while (1); 69 70 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; 71 } 72 73 static int clk_pllv3_prepare(struct clk_hw *hw) 74 { 75 struct clk_pllv3 *pll = to_clk_pllv3(hw); 76 u32 val; 77 78 val = readl_relaxed(pll->base); 79 if (pll->powerup_set) 80 val |= BM_PLL_POWER; 81 else 82 val &= ~BM_PLL_POWER; 83 writel_relaxed(val, pll->base); 84 85 return clk_pllv3_wait_lock(pll); 86 } 87 88 static void clk_pllv3_unprepare(struct clk_hw *hw) 89 { 90 struct clk_pllv3 *pll = to_clk_pllv3(hw); 91 u32 val; 92 93 val = readl_relaxed(pll->base); 94 if (pll->powerup_set) 95 val &= ~BM_PLL_POWER; 96 else 97 val |= BM_PLL_POWER; 98 writel_relaxed(val, pll->base); 99 } 100 101 static int clk_pllv3_is_prepared(struct clk_hw *hw) 102 { 103 struct clk_pllv3 *pll = to_clk_pllv3(hw); 104 105 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 106 return 1; 107 108 return 0; 109 } 110 111 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 112 unsigned long parent_rate) 113 { 114 struct clk_pllv3 *pll = to_clk_pllv3(hw); 115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 116 117 return (div == 1) ? parent_rate * 22 : parent_rate * 20; 118 } 119 120 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, 121 unsigned long *prate) 122 { 123 unsigned long parent_rate = *prate; 124 125 return (rate >= parent_rate * 22) ? parent_rate * 22 : 126 parent_rate * 20; 127 } 128 129 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 130 unsigned long parent_rate) 131 { 132 struct clk_pllv3 *pll = to_clk_pllv3(hw); 133 u32 val, div; 134 135 if (rate == parent_rate * 22) 136 div = 1; 137 else if (rate == parent_rate * 20) 138 div = 0; 139 else 140 return -EINVAL; 141 142 val = readl_relaxed(pll->base); 143 val &= ~(pll->div_mask << pll->div_shift); 144 val |= (div << pll->div_shift); 145 writel_relaxed(val, pll->base); 146 147 return clk_pllv3_wait_lock(pll); 148 } 149 150 static const struct clk_ops clk_pllv3_ops = { 151 .prepare = clk_pllv3_prepare, 152 .unprepare = clk_pllv3_unprepare, 153 .is_prepared = clk_pllv3_is_prepared, 154 .recalc_rate = clk_pllv3_recalc_rate, 155 .round_rate = clk_pllv3_round_rate, 156 .set_rate = clk_pllv3_set_rate, 157 }; 158 159 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, 160 unsigned long parent_rate) 161 { 162 struct clk_pllv3 *pll = to_clk_pllv3(hw); 163 u32 div = readl_relaxed(pll->base) & pll->div_mask; 164 165 return parent_rate * div / 2; 166 } 167 168 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, 169 unsigned long *prate) 170 { 171 unsigned long parent_rate = *prate; 172 unsigned long min_rate = parent_rate * 54 / 2; 173 unsigned long max_rate = parent_rate * 108 / 2; 174 u32 div; 175 176 if (rate > max_rate) 177 rate = max_rate; 178 else if (rate < min_rate) 179 rate = min_rate; 180 div = rate * 2 / parent_rate; 181 182 return parent_rate * div / 2; 183 } 184 185 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, 186 unsigned long parent_rate) 187 { 188 struct clk_pllv3 *pll = to_clk_pllv3(hw); 189 unsigned long min_rate = parent_rate * 54 / 2; 190 unsigned long max_rate = parent_rate * 108 / 2; 191 u32 val, div; 192 193 if (rate < min_rate || rate > max_rate) 194 return -EINVAL; 195 196 div = rate * 2 / parent_rate; 197 val = readl_relaxed(pll->base); 198 val &= ~pll->div_mask; 199 val |= div; 200 writel_relaxed(val, pll->base); 201 202 return clk_pllv3_wait_lock(pll); 203 } 204 205 static const struct clk_ops clk_pllv3_sys_ops = { 206 .prepare = clk_pllv3_prepare, 207 .unprepare = clk_pllv3_unprepare, 208 .is_prepared = clk_pllv3_is_prepared, 209 .recalc_rate = clk_pllv3_sys_recalc_rate, 210 .round_rate = clk_pllv3_sys_round_rate, 211 .set_rate = clk_pllv3_sys_set_rate, 212 }; 213 214 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 215 unsigned long parent_rate) 216 { 217 struct clk_pllv3 *pll = to_clk_pllv3(hw); 218 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); 219 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); 220 u32 div = readl_relaxed(pll->base) & pll->div_mask; 221 222 return (parent_rate * div) + ((parent_rate / mfd) * mfn); 223 } 224 225 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 226 unsigned long *prate) 227 { 228 unsigned long parent_rate = *prate; 229 unsigned long min_rate = parent_rate * 27; 230 unsigned long max_rate = parent_rate * 54; 231 u32 div; 232 u32 mfn, mfd = 1000000; 233 u64 temp64; 234 235 if (rate > max_rate) 236 rate = max_rate; 237 else if (rate < min_rate) 238 rate = min_rate; 239 240 div = rate / parent_rate; 241 temp64 = (u64) (rate - div * parent_rate); 242 temp64 *= mfd; 243 do_div(temp64, parent_rate); 244 mfn = temp64; 245 246 return parent_rate * div + parent_rate / mfd * mfn; 247 } 248 249 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 250 unsigned long parent_rate) 251 { 252 struct clk_pllv3 *pll = to_clk_pllv3(hw); 253 unsigned long min_rate = parent_rate * 27; 254 unsigned long max_rate = parent_rate * 54; 255 u32 val, div; 256 u32 mfn, mfd = 1000000; 257 u64 temp64; 258 259 if (rate < min_rate || rate > max_rate) 260 return -EINVAL; 261 262 div = rate / parent_rate; 263 temp64 = (u64) (rate - div * parent_rate); 264 temp64 *= mfd; 265 do_div(temp64, parent_rate); 266 mfn = temp64; 267 268 val = readl_relaxed(pll->base); 269 val &= ~pll->div_mask; 270 val |= div; 271 writel_relaxed(val, pll->base); 272 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); 273 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); 274 275 return clk_pllv3_wait_lock(pll); 276 } 277 278 static const struct clk_ops clk_pllv3_av_ops = { 279 .prepare = clk_pllv3_prepare, 280 .unprepare = clk_pllv3_unprepare, 281 .is_prepared = clk_pllv3_is_prepared, 282 .recalc_rate = clk_pllv3_av_recalc_rate, 283 .round_rate = clk_pllv3_av_round_rate, 284 .set_rate = clk_pllv3_av_set_rate, 285 }; 286 287 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, 288 unsigned long parent_rate) 289 { 290 struct clk_pllv3 *pll = to_clk_pllv3(hw); 291 292 return pll->ref_clock; 293 } 294 295 static const struct clk_ops clk_pllv3_enet_ops = { 296 .prepare = clk_pllv3_prepare, 297 .unprepare = clk_pllv3_unprepare, 298 .is_prepared = clk_pllv3_is_prepared, 299 .recalc_rate = clk_pllv3_enet_recalc_rate, 300 }; 301 302 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 303 const char *parent_name, void __iomem *base, 304 u32 div_mask) 305 { 306 struct clk_pllv3 *pll; 307 const struct clk_ops *ops; 308 struct clk *clk; 309 struct clk_init_data init; 310 311 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 312 if (!pll) 313 return ERR_PTR(-ENOMEM); 314 315 pll->powerdown = BM_PLL_POWER; 316 317 switch (type) { 318 case IMX_PLLV3_SYS: 319 ops = &clk_pllv3_sys_ops; 320 break; 321 case IMX_PLLV3_USB_VF610: 322 pll->div_shift = 1; 323 case IMX_PLLV3_USB: 324 ops = &clk_pllv3_ops; 325 pll->powerup_set = true; 326 break; 327 case IMX_PLLV3_AV: 328 ops = &clk_pllv3_av_ops; 329 break; 330 case IMX_PLLV3_ENET_IMX7: 331 pll->powerdown = IMX7_ENET_PLL_POWER; 332 pll->ref_clock = 1000000000; 333 ops = &clk_pllv3_enet_ops; 334 break; 335 case IMX_PLLV3_ENET: 336 pll->ref_clock = 500000000; 337 ops = &clk_pllv3_enet_ops; 338 break; 339 default: 340 ops = &clk_pllv3_ops; 341 } 342 pll->base = base; 343 pll->div_mask = div_mask; 344 345 init.name = name; 346 init.ops = ops; 347 init.flags = 0; 348 init.parent_names = &parent_name; 349 init.num_parents = 1; 350 351 pll->hw.init = &init; 352 353 clk = clk_register(NULL, &pll->hw); 354 if (IS_ERR(clk)) 355 kfree(pll); 356 357 return clk; 358 } 359