1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017-2018 NXP. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/slab.h> 12 #include <linux/jiffies.h> 13 14 #include "clk.h" 15 16 #define GNRL_CTL 0x0 17 #define DIV_CTL 0x4 18 #define LOCK_STATUS BIT(31) 19 #define LOCK_SEL_MASK BIT(29) 20 #define CLKE_MASK BIT(11) 21 #define RST_MASK BIT(9) 22 #define BYPASS_MASK BIT(4) 23 #define MDIV_SHIFT 12 24 #define MDIV_MASK GENMASK(21, 12) 25 #define PDIV_SHIFT 4 26 #define PDIV_MASK GENMASK(9, 4) 27 #define SDIV_SHIFT 0 28 #define SDIV_MASK GENMASK(2, 0) 29 #define KDIV_SHIFT 0 30 #define KDIV_MASK GENMASK(15, 0) 31 32 #define LOCK_TIMEOUT_US 10000 33 34 struct clk_pll14xx { 35 struct clk_hw hw; 36 void __iomem *base; 37 enum imx_pll14xx_type type; 38 const struct imx_pll14xx_rate_table *rate_table; 39 int rate_count; 40 }; 41 42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) 43 44 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { 45 PLL_1416X_RATE(1800000000U, 225, 3, 0), 46 PLL_1416X_RATE(1600000000U, 200, 3, 0), 47 PLL_1416X_RATE(1500000000U, 375, 3, 1), 48 PLL_1416X_RATE(1400000000U, 350, 3, 1), 49 PLL_1416X_RATE(1200000000U, 300, 3, 1), 50 PLL_1416X_RATE(1000000000U, 250, 3, 1), 51 PLL_1416X_RATE(800000000U, 200, 3, 1), 52 PLL_1416X_RATE(750000000U, 250, 2, 2), 53 PLL_1416X_RATE(700000000U, 350, 3, 2), 54 PLL_1416X_RATE(600000000U, 300, 3, 2), 55 }; 56 57 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { 58 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384), 59 PLL_1443X_RATE(650000000U, 325, 3, 2, 0), 60 PLL_1443X_RATE(594000000U, 198, 2, 2, 0), 61 PLL_1443X_RATE(519750000U, 173, 2, 2, 16384), 62 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), 63 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), 64 }; 65 66 struct imx_pll14xx_clk imx_1443x_pll = { 67 .type = PLL_1443X, 68 .rate_table = imx_pll1443x_tbl, 69 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), 70 }; 71 72 struct imx_pll14xx_clk imx_1443x_dram_pll = { 73 .type = PLL_1443X, 74 .rate_table = imx_pll1443x_tbl, 75 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), 76 .flags = CLK_GET_RATE_NOCACHE, 77 }; 78 79 struct imx_pll14xx_clk imx_1416x_pll = { 80 .type = PLL_1416X, 81 .rate_table = imx_pll1416x_tbl, 82 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), 83 }; 84 85 static const struct imx_pll14xx_rate_table *imx_get_pll_settings( 86 struct clk_pll14xx *pll, unsigned long rate) 87 { 88 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; 89 int i; 90 91 for (i = 0; i < pll->rate_count; i++) 92 if (rate == rate_table[i].rate) 93 return &rate_table[i]; 94 95 return NULL; 96 } 97 98 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, 99 unsigned long *prate) 100 { 101 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 102 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; 103 int i; 104 105 /* Assumming rate_table is in descending order */ 106 for (i = 0; i < pll->rate_count; i++) 107 if (rate >= rate_table[i].rate) 108 return rate_table[i].rate; 109 110 /* return minimum supported value */ 111 return rate_table[i - 1].rate; 112 } 113 114 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, 115 unsigned long parent_rate) 116 { 117 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 118 u32 mdiv, pdiv, sdiv, pll_div; 119 u64 fvco = parent_rate; 120 121 pll_div = readl_relaxed(pll->base + 4); 122 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; 123 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; 124 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; 125 126 fvco *= mdiv; 127 do_div(fvco, pdiv << sdiv); 128 129 return fvco; 130 } 131 132 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, 133 unsigned long parent_rate) 134 { 135 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 136 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; 137 short int kdiv; 138 u64 fvco = parent_rate; 139 140 pll_div_ctl0 = readl_relaxed(pll->base + 4); 141 pll_div_ctl1 = readl_relaxed(pll->base + 8); 142 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; 143 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; 144 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; 145 kdiv = pll_div_ctl1 & KDIV_MASK; 146 147 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ 148 fvco *= (mdiv * 65536 + kdiv); 149 pdiv *= 65536; 150 151 do_div(fvco, pdiv << sdiv); 152 153 return fvco; 154 } 155 156 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, 157 u32 pll_div) 158 { 159 u32 old_mdiv, old_pdiv; 160 161 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; 162 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; 163 164 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; 165 } 166 167 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) 168 { 169 u32 val; 170 171 return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, 172 LOCK_TIMEOUT_US); 173 } 174 175 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, 176 unsigned long prate) 177 { 178 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 179 const struct imx_pll14xx_rate_table *rate; 180 u32 tmp, div_val; 181 int ret; 182 183 rate = imx_get_pll_settings(pll, drate); 184 if (!rate) { 185 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 186 drate, clk_hw_get_name(hw)); 187 return -EINVAL; 188 } 189 190 tmp = readl_relaxed(pll->base + 4); 191 192 if (!clk_pll14xx_mp_change(rate, tmp)) { 193 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; 194 tmp |= rate->sdiv << SDIV_SHIFT; 195 writel_relaxed(tmp, pll->base + 4); 196 197 return 0; 198 } 199 200 /* Bypass clock and set lock to pll output lock */ 201 tmp = readl_relaxed(pll->base); 202 tmp |= LOCK_SEL_MASK; 203 writel_relaxed(tmp, pll->base); 204 205 /* Enable RST */ 206 tmp &= ~RST_MASK; 207 writel_relaxed(tmp, pll->base); 208 209 /* Enable BYPASS */ 210 tmp |= BYPASS_MASK; 211 writel(tmp, pll->base); 212 213 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 214 (rate->sdiv << SDIV_SHIFT); 215 writel_relaxed(div_val, pll->base + 0x4); 216 217 /* 218 * According to SPEC, t3 - t2 need to be greater than 219 * 1us and 1/FREF, respectively. 220 * FREF is FIN / Prediv, the prediv is [1, 63], so choose 221 * 3us. 222 */ 223 udelay(3); 224 225 /* Disable RST */ 226 tmp |= RST_MASK; 227 writel_relaxed(tmp, pll->base); 228 229 /* Wait Lock */ 230 ret = clk_pll14xx_wait_lock(pll); 231 if (ret) 232 return ret; 233 234 /* Bypass */ 235 tmp &= ~BYPASS_MASK; 236 writel_relaxed(tmp, pll->base); 237 238 return 0; 239 } 240 241 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, 242 unsigned long prate) 243 { 244 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 245 const struct imx_pll14xx_rate_table *rate; 246 u32 tmp, div_val; 247 int ret; 248 249 rate = imx_get_pll_settings(pll, drate); 250 if (!rate) { 251 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 252 drate, clk_hw_get_name(hw)); 253 return -EINVAL; 254 } 255 256 tmp = readl_relaxed(pll->base + 4); 257 258 if (!clk_pll14xx_mp_change(rate, tmp)) { 259 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; 260 tmp |= rate->sdiv << SDIV_SHIFT; 261 writel_relaxed(tmp, pll->base + 4); 262 263 tmp = rate->kdiv << KDIV_SHIFT; 264 writel_relaxed(tmp, pll->base + 8); 265 266 return 0; 267 } 268 269 /* Enable RST */ 270 tmp = readl_relaxed(pll->base); 271 tmp &= ~RST_MASK; 272 writel_relaxed(tmp, pll->base); 273 274 /* Enable BYPASS */ 275 tmp |= BYPASS_MASK; 276 writel_relaxed(tmp, pll->base); 277 278 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 279 (rate->sdiv << SDIV_SHIFT); 280 writel_relaxed(div_val, pll->base + 0x4); 281 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); 282 283 /* 284 * According to SPEC, t3 - t2 need to be greater than 285 * 1us and 1/FREF, respectively. 286 * FREF is FIN / Prediv, the prediv is [1, 63], so choose 287 * 3us. 288 */ 289 udelay(3); 290 291 /* Disable RST */ 292 tmp |= RST_MASK; 293 writel_relaxed(tmp, pll->base); 294 295 /* Wait Lock*/ 296 ret = clk_pll14xx_wait_lock(pll); 297 if (ret) 298 return ret; 299 300 /* Bypass */ 301 tmp &= ~BYPASS_MASK; 302 writel_relaxed(tmp, pll->base); 303 304 return 0; 305 } 306 307 static int clk_pll14xx_prepare(struct clk_hw *hw) 308 { 309 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 310 u32 val; 311 int ret; 312 313 /* 314 * RESETB = 1 from 0, PLL starts its normal 315 * operation after lock time 316 */ 317 val = readl_relaxed(pll->base + GNRL_CTL); 318 if (val & RST_MASK) 319 return 0; 320 val |= BYPASS_MASK; 321 writel_relaxed(val, pll->base + GNRL_CTL); 322 val |= RST_MASK; 323 writel_relaxed(val, pll->base + GNRL_CTL); 324 325 ret = clk_pll14xx_wait_lock(pll); 326 if (ret) 327 return ret; 328 329 val &= ~BYPASS_MASK; 330 writel_relaxed(val, pll->base + GNRL_CTL); 331 332 return 0; 333 } 334 335 static int clk_pll14xx_is_prepared(struct clk_hw *hw) 336 { 337 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 338 u32 val; 339 340 val = readl_relaxed(pll->base + GNRL_CTL); 341 342 return (val & RST_MASK) ? 1 : 0; 343 } 344 345 static void clk_pll14xx_unprepare(struct clk_hw *hw) 346 { 347 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 348 u32 val; 349 350 /* 351 * Set RST to 0, power down mode is enabled and 352 * every digital block is reset 353 */ 354 val = readl_relaxed(pll->base + GNRL_CTL); 355 val &= ~RST_MASK; 356 writel_relaxed(val, pll->base + GNRL_CTL); 357 } 358 359 static const struct clk_ops clk_pll1416x_ops = { 360 .prepare = clk_pll14xx_prepare, 361 .unprepare = clk_pll14xx_unprepare, 362 .is_prepared = clk_pll14xx_is_prepared, 363 .recalc_rate = clk_pll1416x_recalc_rate, 364 .round_rate = clk_pll14xx_round_rate, 365 .set_rate = clk_pll1416x_set_rate, 366 }; 367 368 static const struct clk_ops clk_pll1416x_min_ops = { 369 .recalc_rate = clk_pll1416x_recalc_rate, 370 }; 371 372 static const struct clk_ops clk_pll1443x_ops = { 373 .prepare = clk_pll14xx_prepare, 374 .unprepare = clk_pll14xx_unprepare, 375 .is_prepared = clk_pll14xx_is_prepared, 376 .recalc_rate = clk_pll1443x_recalc_rate, 377 .round_rate = clk_pll14xx_round_rate, 378 .set_rate = clk_pll1443x_set_rate, 379 }; 380 381 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, 382 const char *parent_name, void __iomem *base, 383 const struct imx_pll14xx_clk *pll_clk) 384 { 385 struct clk_pll14xx *pll; 386 struct clk_hw *hw; 387 struct clk_init_data init; 388 int ret; 389 u32 val; 390 391 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 392 if (!pll) 393 return ERR_PTR(-ENOMEM); 394 395 init.name = name; 396 init.flags = pll_clk->flags; 397 init.parent_names = &parent_name; 398 init.num_parents = 1; 399 400 switch (pll_clk->type) { 401 case PLL_1416X: 402 if (!pll_clk->rate_table) 403 init.ops = &clk_pll1416x_min_ops; 404 else 405 init.ops = &clk_pll1416x_ops; 406 break; 407 case PLL_1443X: 408 init.ops = &clk_pll1443x_ops; 409 break; 410 default: 411 pr_err("%s: Unknown pll type for pll clk %s\n", 412 __func__, name); 413 kfree(pll); 414 return ERR_PTR(-EINVAL); 415 }; 416 417 pll->base = base; 418 pll->hw.init = &init; 419 pll->type = pll_clk->type; 420 pll->rate_table = pll_clk->rate_table; 421 pll->rate_count = pll_clk->rate_count; 422 423 val = readl_relaxed(pll->base + GNRL_CTL); 424 val &= ~BYPASS_MASK; 425 writel_relaxed(val, pll->base + GNRL_CTL); 426 427 hw = &pll->hw; 428 429 ret = clk_hw_register(dev, hw); 430 if (ret) { 431 pr_err("%s: failed to register pll %s %d\n", 432 __func__, name, ret); 433 kfree(pll); 434 return ERR_PTR(ret); 435 } 436 437 return hw; 438 } 439