1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2017-2018 NXP. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/slab.h> 12 #include <linux/jiffies.h> 13 14 #include "clk.h" 15 16 #define GNRL_CTL 0x0 17 #define DIV_CTL 0x4 18 #define LOCK_STATUS BIT(31) 19 #define LOCK_SEL_MASK BIT(29) 20 #define CLKE_MASK BIT(11) 21 #define RST_MASK BIT(9) 22 #define BYPASS_MASK BIT(4) 23 #define MDIV_SHIFT 12 24 #define MDIV_MASK GENMASK(21, 12) 25 #define PDIV_SHIFT 4 26 #define PDIV_MASK GENMASK(9, 4) 27 #define SDIV_SHIFT 0 28 #define SDIV_MASK GENMASK(2, 0) 29 #define KDIV_SHIFT 0 30 #define KDIV_MASK GENMASK(15, 0) 31 32 #define LOCK_TIMEOUT_US 10000 33 34 struct clk_pll14xx { 35 struct clk_hw hw; 36 void __iomem *base; 37 enum imx_pll14xx_type type; 38 const struct imx_pll14xx_rate_table *rate_table; 39 int rate_count; 40 }; 41 42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) 43 44 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { 45 PLL_1416X_RATE(1800000000U, 225, 3, 0), 46 PLL_1416X_RATE(1600000000U, 200, 3, 0), 47 PLL_1416X_RATE(1500000000U, 375, 3, 1), 48 PLL_1416X_RATE(1400000000U, 350, 3, 1), 49 PLL_1416X_RATE(1200000000U, 300, 3, 1), 50 PLL_1416X_RATE(1000000000U, 250, 3, 1), 51 PLL_1416X_RATE(800000000U, 200, 3, 1), 52 PLL_1416X_RATE(750000000U, 250, 2, 2), 53 PLL_1416X_RATE(700000000U, 350, 3, 2), 54 PLL_1416X_RATE(600000000U, 300, 3, 2), 55 }; 56 57 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = { 58 PLL_1443X_RATE(650000000U, 325, 3, 2, 0), 59 PLL_1443X_RATE(594000000U, 198, 2, 2, 0), 60 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), 61 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), 62 }; 63 64 struct imx_pll14xx_clk imx_1443x_pll = { 65 .type = PLL_1443X, 66 .rate_table = imx_pll1443x_tbl, 67 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), 68 }; 69 70 struct imx_pll14xx_clk imx_1443x_dram_pll = { 71 .type = PLL_1443X, 72 .rate_table = imx_pll1443x_tbl, 73 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), 74 .flags = CLK_GET_RATE_NOCACHE, 75 }; 76 77 struct imx_pll14xx_clk imx_1416x_pll = { 78 .type = PLL_1416X, 79 .rate_table = imx_pll1416x_tbl, 80 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), 81 }; 82 83 static const struct imx_pll14xx_rate_table *imx_get_pll_settings( 84 struct clk_pll14xx *pll, unsigned long rate) 85 { 86 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; 87 int i; 88 89 for (i = 0; i < pll->rate_count; i++) 90 if (rate == rate_table[i].rate) 91 return &rate_table[i]; 92 93 return NULL; 94 } 95 96 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, 97 unsigned long *prate) 98 { 99 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 100 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; 101 int i; 102 103 /* Assumming rate_table is in descending order */ 104 for (i = 0; i < pll->rate_count; i++) 105 if (rate >= rate_table[i].rate) 106 return rate_table[i].rate; 107 108 /* return minimum supported value */ 109 return rate_table[i - 1].rate; 110 } 111 112 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, 113 unsigned long parent_rate) 114 { 115 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 116 u32 mdiv, pdiv, sdiv, pll_div; 117 u64 fvco = parent_rate; 118 119 pll_div = readl_relaxed(pll->base + 4); 120 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; 121 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; 122 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; 123 124 fvco *= mdiv; 125 do_div(fvco, pdiv << sdiv); 126 127 return fvco; 128 } 129 130 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, 131 unsigned long parent_rate) 132 { 133 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 134 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; 135 short int kdiv; 136 u64 fvco = parent_rate; 137 138 pll_div_ctl0 = readl_relaxed(pll->base + 4); 139 pll_div_ctl1 = readl_relaxed(pll->base + 8); 140 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; 141 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; 142 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; 143 kdiv = pll_div_ctl1 & KDIV_MASK; 144 145 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ 146 fvco *= (mdiv * 65536 + kdiv); 147 pdiv *= 65536; 148 149 do_div(fvco, pdiv << sdiv); 150 151 return fvco; 152 } 153 154 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, 155 u32 pll_div) 156 { 157 u32 old_mdiv, old_pdiv; 158 159 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; 160 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; 161 162 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; 163 } 164 165 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) 166 { 167 u32 val; 168 169 return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, 170 LOCK_TIMEOUT_US); 171 } 172 173 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, 174 unsigned long prate) 175 { 176 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 177 const struct imx_pll14xx_rate_table *rate; 178 u32 tmp, div_val; 179 int ret; 180 181 rate = imx_get_pll_settings(pll, drate); 182 if (!rate) { 183 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 184 drate, clk_hw_get_name(hw)); 185 return -EINVAL; 186 } 187 188 tmp = readl_relaxed(pll->base + 4); 189 190 if (!clk_pll14xx_mp_change(rate, tmp)) { 191 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; 192 tmp |= rate->sdiv << SDIV_SHIFT; 193 writel_relaxed(tmp, pll->base + 4); 194 195 return 0; 196 } 197 198 /* Bypass clock and set lock to pll output lock */ 199 tmp = readl_relaxed(pll->base); 200 tmp |= LOCK_SEL_MASK; 201 writel_relaxed(tmp, pll->base); 202 203 /* Enable RST */ 204 tmp &= ~RST_MASK; 205 writel_relaxed(tmp, pll->base); 206 207 /* Enable BYPASS */ 208 tmp |= BYPASS_MASK; 209 writel(tmp, pll->base); 210 211 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 212 (rate->sdiv << SDIV_SHIFT); 213 writel_relaxed(div_val, pll->base + 0x4); 214 215 /* 216 * According to SPEC, t3 - t2 need to be greater than 217 * 1us and 1/FREF, respectively. 218 * FREF is FIN / Prediv, the prediv is [1, 63], so choose 219 * 3us. 220 */ 221 udelay(3); 222 223 /* Disable RST */ 224 tmp |= RST_MASK; 225 writel_relaxed(tmp, pll->base); 226 227 /* Wait Lock */ 228 ret = clk_pll14xx_wait_lock(pll); 229 if (ret) 230 return ret; 231 232 /* Bypass */ 233 tmp &= ~BYPASS_MASK; 234 writel_relaxed(tmp, pll->base); 235 236 return 0; 237 } 238 239 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, 240 unsigned long prate) 241 { 242 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 243 const struct imx_pll14xx_rate_table *rate; 244 u32 tmp, div_val; 245 int ret; 246 247 rate = imx_get_pll_settings(pll, drate); 248 if (!rate) { 249 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 250 drate, clk_hw_get_name(hw)); 251 return -EINVAL; 252 } 253 254 tmp = readl_relaxed(pll->base + 4); 255 256 if (!clk_pll14xx_mp_change(rate, tmp)) { 257 tmp &= ~(SDIV_MASK) << SDIV_SHIFT; 258 tmp |= rate->sdiv << SDIV_SHIFT; 259 writel_relaxed(tmp, pll->base + 4); 260 261 tmp = rate->kdiv << KDIV_SHIFT; 262 writel_relaxed(tmp, pll->base + 8); 263 264 return 0; 265 } 266 267 /* Enable RST */ 268 tmp = readl_relaxed(pll->base); 269 tmp &= ~RST_MASK; 270 writel_relaxed(tmp, pll->base); 271 272 /* Enable BYPASS */ 273 tmp |= BYPASS_MASK; 274 writel_relaxed(tmp, pll->base); 275 276 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 277 (rate->sdiv << SDIV_SHIFT); 278 writel_relaxed(div_val, pll->base + 0x4); 279 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); 280 281 /* 282 * According to SPEC, t3 - t2 need to be greater than 283 * 1us and 1/FREF, respectively. 284 * FREF is FIN / Prediv, the prediv is [1, 63], so choose 285 * 3us. 286 */ 287 udelay(3); 288 289 /* Disable RST */ 290 tmp |= RST_MASK; 291 writel_relaxed(tmp, pll->base); 292 293 /* Wait Lock*/ 294 ret = clk_pll14xx_wait_lock(pll); 295 if (ret) 296 return ret; 297 298 /* Bypass */ 299 tmp &= ~BYPASS_MASK; 300 writel_relaxed(tmp, pll->base); 301 302 return 0; 303 } 304 305 static int clk_pll14xx_prepare(struct clk_hw *hw) 306 { 307 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 308 u32 val; 309 int ret; 310 311 /* 312 * RESETB = 1 from 0, PLL starts its normal 313 * operation after lock time 314 */ 315 val = readl_relaxed(pll->base + GNRL_CTL); 316 if (val & RST_MASK) 317 return 0; 318 val |= BYPASS_MASK; 319 writel_relaxed(val, pll->base + GNRL_CTL); 320 val |= RST_MASK; 321 writel_relaxed(val, pll->base + GNRL_CTL); 322 323 ret = clk_pll14xx_wait_lock(pll); 324 if (ret) 325 return ret; 326 327 val &= ~BYPASS_MASK; 328 writel_relaxed(val, pll->base + GNRL_CTL); 329 330 return 0; 331 } 332 333 static int clk_pll14xx_is_prepared(struct clk_hw *hw) 334 { 335 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 336 u32 val; 337 338 val = readl_relaxed(pll->base + GNRL_CTL); 339 340 return (val & RST_MASK) ? 1 : 0; 341 } 342 343 static void clk_pll14xx_unprepare(struct clk_hw *hw) 344 { 345 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 346 u32 val; 347 348 /* 349 * Set RST to 0, power down mode is enabled and 350 * every digital block is reset 351 */ 352 val = readl_relaxed(pll->base + GNRL_CTL); 353 val &= ~RST_MASK; 354 writel_relaxed(val, pll->base + GNRL_CTL); 355 } 356 357 static const struct clk_ops clk_pll1416x_ops = { 358 .prepare = clk_pll14xx_prepare, 359 .unprepare = clk_pll14xx_unprepare, 360 .is_prepared = clk_pll14xx_is_prepared, 361 .recalc_rate = clk_pll1416x_recalc_rate, 362 .round_rate = clk_pll14xx_round_rate, 363 .set_rate = clk_pll1416x_set_rate, 364 }; 365 366 static const struct clk_ops clk_pll1416x_min_ops = { 367 .recalc_rate = clk_pll1416x_recalc_rate, 368 }; 369 370 static const struct clk_ops clk_pll1443x_ops = { 371 .prepare = clk_pll14xx_prepare, 372 .unprepare = clk_pll14xx_unprepare, 373 .is_prepared = clk_pll14xx_is_prepared, 374 .recalc_rate = clk_pll1443x_recalc_rate, 375 .round_rate = clk_pll14xx_round_rate, 376 .set_rate = clk_pll1443x_set_rate, 377 }; 378 379 struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name, 380 void __iomem *base, 381 const struct imx_pll14xx_clk *pll_clk) 382 { 383 struct clk_pll14xx *pll; 384 struct clk_hw *hw; 385 struct clk_init_data init; 386 int ret; 387 u32 val; 388 389 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 390 if (!pll) 391 return ERR_PTR(-ENOMEM); 392 393 init.name = name; 394 init.flags = pll_clk->flags; 395 init.parent_names = &parent_name; 396 init.num_parents = 1; 397 398 switch (pll_clk->type) { 399 case PLL_1416X: 400 if (!pll_clk->rate_table) 401 init.ops = &clk_pll1416x_min_ops; 402 else 403 init.ops = &clk_pll1416x_ops; 404 break; 405 case PLL_1443X: 406 init.ops = &clk_pll1443x_ops; 407 break; 408 default: 409 pr_err("%s: Unknown pll type for pll clk %s\n", 410 __func__, name); 411 }; 412 413 pll->base = base; 414 pll->hw.init = &init; 415 pll->type = pll_clk->type; 416 pll->rate_table = pll_clk->rate_table; 417 pll->rate_count = pll_clk->rate_count; 418 419 val = readl_relaxed(pll->base + GNRL_CTL); 420 val &= ~BYPASS_MASK; 421 writel_relaxed(val, pll->base + GNRL_CTL); 422 423 hw = &pll->hw; 424 425 ret = clk_hw_register(NULL, hw); 426 if (ret) { 427 pr_err("%s: failed to register pll %s %d\n", 428 __func__, name, ret); 429 kfree(pll); 430 return ERR_PTR(ret); 431 } 432 433 return hw; 434 } 435