1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2021 NXP. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/io.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 #include <linux/types.h> 14 #include <dt-bindings/clock/imx93-clock.h> 15 16 #include "clk.h" 17 18 enum clk_sel { 19 LOW_SPEED_IO_SEL, 20 NON_IO_SEL, 21 FAST_SEL, 22 AUDIO_SEL, 23 VIDEO_SEL, 24 TPM_SEL, 25 CKO1_SEL, 26 CKO2_SEL, 27 MISC_SEL, 28 MAX_SEL 29 }; 30 31 static u32 share_count_sai1; 32 static u32 share_count_sai2; 33 static u32 share_count_sai3; 34 static u32 share_count_mub; 35 36 static const char *parent_names[MAX_SEL][4] = { 37 {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, 38 {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, 39 {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2"}, 40 {"osc_24m", "audio_pll", "video_pll", "clk_ext1"}, 41 {"osc_24m", "audio_pll", "video_pll", "sys_pll_pfd0"}, 42 {"osc_24m", "sys_pll_pfd0", "audio_pll", "clk_ext1"}, 43 {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll"}, 44 {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll"}, 45 {"osc_24m", "audio_pll", "video_pll", "sys_pll_pfd2"}, 46 }; 47 48 static const struct imx93_clk_root { 49 u32 clk; 50 char *name; 51 u32 off; 52 enum clk_sel sel; 53 unsigned long flags; 54 } root_array[] = { 55 /* a55/m33/bus critical clk for system run */ 56 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, 57 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 58 { IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, 59 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 60 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 61 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, 62 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, 63 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, 64 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, 65 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, 66 { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, 67 { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, 68 { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, 69 { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, 70 { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, 71 { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, 72 { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, 73 { IMX93_CLK_FLEXSPI1, "flexspi1_root", 0x0b00, FAST_SEL, }, 74 { IMX93_CLK_CAN1, "can1_root", 0x0b80, LOW_SPEED_IO_SEL, }, 75 { IMX93_CLK_CAN2, "can2_root", 0x0c00, LOW_SPEED_IO_SEL, }, 76 { IMX93_CLK_LPUART1, "lpuart1_root", 0x0c80, LOW_SPEED_IO_SEL, }, 77 { IMX93_CLK_LPUART2, "lpuart2_root", 0x0d00, LOW_SPEED_IO_SEL, }, 78 { IMX93_CLK_LPUART3, "lpuart3_root", 0x0d80, LOW_SPEED_IO_SEL, }, 79 { IMX93_CLK_LPUART4, "lpuart4_root", 0x0e00, LOW_SPEED_IO_SEL, }, 80 { IMX93_CLK_LPUART5, "lpuart5_root", 0x0e80, LOW_SPEED_IO_SEL, }, 81 { IMX93_CLK_LPUART6, "lpuart6_root", 0x0f00, LOW_SPEED_IO_SEL, }, 82 { IMX93_CLK_LPUART7, "lpuart7_root", 0x0f80, LOW_SPEED_IO_SEL, }, 83 { IMX93_CLK_LPUART8, "lpuart8_root", 0x1000, LOW_SPEED_IO_SEL, }, 84 { IMX93_CLK_LPI2C1, "lpi2c1_root", 0x1080, LOW_SPEED_IO_SEL, }, 85 { IMX93_CLK_LPI2C2, "lpi2c2_root", 0x1100, LOW_SPEED_IO_SEL, }, 86 { IMX93_CLK_LPI2C3, "lpi2c3_root", 0x1180, LOW_SPEED_IO_SEL, }, 87 { IMX93_CLK_LPI2C4, "lpi2c4_root", 0x1200, LOW_SPEED_IO_SEL, }, 88 { IMX93_CLK_LPI2C5, "lpi2c5_root", 0x1280, LOW_SPEED_IO_SEL, }, 89 { IMX93_CLK_LPI2C6, "lpi2c6_root", 0x1300, LOW_SPEED_IO_SEL, }, 90 { IMX93_CLK_LPI2C7, "lpi2c7_root", 0x1380, LOW_SPEED_IO_SEL, }, 91 { IMX93_CLK_LPI2C8, "lpi2c8_root", 0x1400, LOW_SPEED_IO_SEL, }, 92 { IMX93_CLK_LPSPI1, "lpspi1_root", 0x1480, LOW_SPEED_IO_SEL, }, 93 { IMX93_CLK_LPSPI2, "lpspi2_root", 0x1500, LOW_SPEED_IO_SEL, }, 94 { IMX93_CLK_LPSPI3, "lpspi3_root", 0x1580, LOW_SPEED_IO_SEL, }, 95 { IMX93_CLK_LPSPI4, "lpspi4_root", 0x1600, LOW_SPEED_IO_SEL, }, 96 { IMX93_CLK_LPSPI5, "lpspi5_root", 0x1680, LOW_SPEED_IO_SEL, }, 97 { IMX93_CLK_LPSPI6, "lpspi6_root", 0x1700, LOW_SPEED_IO_SEL, }, 98 { IMX93_CLK_LPSPI7, "lpspi7_root", 0x1780, LOW_SPEED_IO_SEL, }, 99 { IMX93_CLK_LPSPI8, "lpspi8_root", 0x1800, LOW_SPEED_IO_SEL, }, 100 { IMX93_CLK_I3C1, "i3c1_root", 0x1880, LOW_SPEED_IO_SEL, }, 101 { IMX93_CLK_I3C2, "i3c2_root", 0x1900, LOW_SPEED_IO_SEL, }, 102 { IMX93_CLK_USDHC1, "usdhc1_root", 0x1980, FAST_SEL, }, 103 { IMX93_CLK_USDHC2, "usdhc2_root", 0x1a00, FAST_SEL, }, 104 { IMX93_CLK_USDHC3, "usdhc3_root", 0x1a80, FAST_SEL, }, 105 { IMX93_CLK_SAI1, "sai1_root", 0x1b00, AUDIO_SEL, }, 106 { IMX93_CLK_SAI2, "sai2_root", 0x1b80, AUDIO_SEL, }, 107 { IMX93_CLK_SAI3, "sai3_root", 0x1c00, AUDIO_SEL, }, 108 { IMX93_CLK_CCM_CKO1, "ccm_cko1_root", 0x1c80, CKO1_SEL, }, 109 { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, 110 { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, 111 { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, 112 /* 113 * Critical because clk is used for handshake between HSIOMIX and NICMIX when 114 * NICMIX power down/on during system suspend/resume 115 */ 116 { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL}, 117 { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, 118 { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, 119 { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, 120 { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, 121 { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, 122 { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, 123 { IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, }, 124 { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, }, 125 { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, }, 126 { IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, }, 127 { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, }, 128 { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, }, 129 { IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, }, 130 { IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, }, 131 { IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, }, 132 { IMX93_CLK_TSTMR2, "tstmr2_root", 0x2880, LOW_SPEED_IO_SEL, }, 133 { IMX93_CLK_MQS1, "mqs1_root", 0x2900, AUDIO_SEL, }, 134 { IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, }, 135 { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, }, 136 { IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, }, 137 { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, }, 138 { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, }, 139 { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, }, 140 { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, }, 141 { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, }, 142 { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, }, 143 { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, }, 144 { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, }, 145 { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, } 146 }; 147 148 static const struct imx93_clk_ccgr { 149 u32 clk; 150 char *name; 151 char *parent_name; 152 u32 off; 153 unsigned long flags; 154 u32 *shared_count; 155 } ccgr_array[] = { 156 { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, }, 157 /* M33 critical clk for system run */ 158 { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, 159 { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, }, 160 { IMX93_CLK_WDOG1_GATE, "wdog1", "osc_24m", 0x8300, }, 161 { IMX93_CLK_WDOG2_GATE, "wdog2", "osc_24m", 0x8340, }, 162 { IMX93_CLK_WDOG3_GATE, "wdog3", "osc_24m", 0x8380, }, 163 { IMX93_CLK_WDOG4_GATE, "wdog4", "osc_24m", 0x83c0, }, 164 { IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, }, 165 { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, 166 { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, 167 { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED }, 168 { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED }, 169 { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub }, 170 { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, 171 { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, 172 { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, 173 { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, 174 { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, 175 { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, 176 { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, 177 { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, 178 { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, 179 { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, 180 { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, 181 { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, 182 { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, 183 { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, 184 { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, }, 185 { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, 186 { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, }, 187 { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, 188 { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, 189 { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, 190 { IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, }, 191 { IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, }, 192 { IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, }, 193 { IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, }, 194 { IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, }, 195 { IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, }, 196 { IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, }, 197 { IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, }, 198 { IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, }, 199 { IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, }, 200 { IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, }, 201 { IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, }, 202 { IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, }, 203 { IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, }, 204 { IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, }, 205 { IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, }, 206 { IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, }, 207 { IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, }, 208 { IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, }, 209 { IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, }, 210 { IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, }, 211 { IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, }, 212 { IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, }, 213 { IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, }, 214 { IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, }, 215 { IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, }, 216 { IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, }, 217 { IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, }, 218 { IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, }, 219 { IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, }, 220 { IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, }, 221 { IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, 0, &share_count_sai1}, 222 { IMX93_CLK_SAI1_IPG, "sai1_ipg_clk", "bus_aon_root", 0x9440, 0, &share_count_sai1}, 223 { IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, 0, &share_count_sai2}, 224 { IMX93_CLK_SAI2_IPG, "sai2_ipg_clk", "bus_wakeup_root", 0x9480, 0, &share_count_sai2}, 225 { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, 0, &share_count_sai3}, 226 { IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3}, 227 { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, 228 { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, 229 { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, 230 { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, 231 { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, 232 { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, 233 { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, }, 234 { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, 235 { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, 236 { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, }, 237 { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, 238 { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, 239 { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, 240 { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, 241 { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, 242 { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, 243 { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, 244 { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, 245 /* Critical because clk accessed during CPU idle */ 246 { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL}, 247 { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, 248 { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, 249 { IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, }, 250 { IMX93_CLK_PMRO_GATE, "pmro", "osc_24m", 0x9f80, } 251 }; 252 253 static struct clk_hw_onecell_data *clk_hw_data; 254 static struct clk_hw **clks; 255 256 static int imx93_clocks_probe(struct platform_device *pdev) 257 { 258 struct device *dev = &pdev->dev; 259 struct device_node *np = dev->of_node; 260 const struct imx93_clk_root *root; 261 const struct imx93_clk_ccgr *ccgr; 262 void __iomem *base, *anatop_base; 263 int i, ret; 264 265 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, 266 IMX93_CLK_END), GFP_KERNEL); 267 if (!clk_hw_data) 268 return -ENOMEM; 269 270 clk_hw_data->num = IMX93_CLK_END; 271 clks = clk_hw_data->hws; 272 273 clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); 274 clks[IMX93_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); 275 clks[IMX93_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); 276 clks[IMX93_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); 277 278 clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000); 279 clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", 280 "sys_pll_pfd0", 1, 2); 281 clks[IMX93_CLK_SYS_PLL_PFD1] = imx_clk_hw_fixed("sys_pll_pfd1", 800000000); 282 clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", 283 "sys_pll_pfd1", 1, 2); 284 clks[IMX93_CLK_SYS_PLL_PFD2] = imx_clk_hw_fixed("sys_pll_pfd2", 625000000); 285 clks[IMX93_CLK_SYS_PLL_PFD2_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd2_div2", 286 "sys_pll_pfd2", 1, 2); 287 288 np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop"); 289 anatop_base = of_iomap(np, 0); 290 of_node_put(np); 291 if (WARN_ON(!anatop_base)) 292 return -ENOMEM; 293 294 clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, 295 &imx_fracn_gppll); 296 clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, 297 &imx_fracn_gppll); 298 299 np = dev->of_node; 300 base = devm_platform_ioremap_resource(pdev, 0); 301 if (WARN_ON(IS_ERR(base))) { 302 iounmap(anatop_base); 303 return PTR_ERR(base); 304 } 305 306 for (i = 0; i < ARRAY_SIZE(root_array); i++) { 307 root = &root_array[i]; 308 clks[root->clk] = imx93_clk_composite_flags(root->name, 309 parent_names[root->sel], 310 4, base + root->off, 3, 311 root->flags); 312 } 313 314 for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) { 315 ccgr = &ccgr_array[i]; 316 clks[ccgr->clk] = imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name, 317 ccgr->flags, base + ccgr->off, 0, 1, 1, 3, 318 ccgr->shared_count); 319 } 320 321 imx_check_clk_hws(clks, IMX93_CLK_END); 322 323 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 324 if (ret < 0) { 325 dev_err(dev, "failed to register clks for i.MX93\n"); 326 goto unregister_hws; 327 } 328 329 imx_register_uart_clocks(); 330 331 return 0; 332 333 unregister_hws: 334 imx_unregister_hw_clocks(clks, IMX93_CLK_END); 335 iounmap(anatop_base); 336 337 return ret; 338 } 339 340 static const struct of_device_id imx93_clk_of_match[] = { 341 { .compatible = "fsl,imx93-ccm" }, 342 { /* Sentinel */ }, 343 }; 344 MODULE_DEVICE_TABLE(of, imx93_clk_of_match); 345 346 static struct platform_driver imx93_clk_driver = { 347 .probe = imx93_clocks_probe, 348 .driver = { 349 .name = "imx93-ccm", 350 .suppress_bind_attrs = true, 351 .of_match_table = imx93_clk_of_match, 352 }, 353 }; 354 module_platform_driver(imx93_clk_driver); 355 356 MODULE_DESCRIPTION("NXP i.MX93 clock driver"); 357 MODULE_LICENSE("GPL v2"); 358