18f6d8094SFrank Li /* 28f6d8094SFrank Li * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 38f6d8094SFrank Li * 48f6d8094SFrank Li * The code contained herein is licensed under the GNU General Public 58f6d8094SFrank Li * License. You may obtain a copy of the GNU General Public License 68f6d8094SFrank Li * Version 2 or later at the following locations: 78f6d8094SFrank Li * 88f6d8094SFrank Li * http://www.opensource.org/licenses/gpl-license.html 98f6d8094SFrank Li * http://www.gnu.org/copyleft/gpl.html 108f6d8094SFrank Li */ 118f6d8094SFrank Li 128f6d8094SFrank Li #include <dt-bindings/clock/imx7d-clock.h> 138f6d8094SFrank Li #include <linux/clk.h> 148f6d8094SFrank Li #include <linux/clkdev.h> 158f6d8094SFrank Li #include <linux/err.h> 168f6d8094SFrank Li #include <linux/init.h> 178f6d8094SFrank Li #include <linux/io.h> 188f6d8094SFrank Li #include <linux/of.h> 198f6d8094SFrank Li #include <linux/of_address.h> 208f6d8094SFrank Li #include <linux/of_irq.h> 218f6d8094SFrank Li #include <linux/types.h> 228f6d8094SFrank Li 238f6d8094SFrank Li #include "clk.h" 248f6d8094SFrank Li 2506981025SFabio Estevam static u32 share_count_sai1; 2606981025SFabio Estevam static u32 share_count_sai2; 2706981025SFabio Estevam static u32 share_count_sai3; 2822039d15SStefan Agner static u32 share_count_nand; 299c7150daSAnson Huang static u32 share_count_enet1; 309c7150daSAnson Huang static u32 share_count_enet2; 3106981025SFabio Estevam 32fdda6ee9SArvind Yadav static const struct clk_div_table test_div_table[] = { 3354fe0791SFabio Estevam { .val = 3, .div = 1, }, 3454fe0791SFabio Estevam { .val = 2, .div = 1, }, 3554fe0791SFabio Estevam { .val = 1, .div = 2, }, 3654fe0791SFabio Estevam { .val = 0, .div = 4, }, 3754fe0791SFabio Estevam { } 3854fe0791SFabio Estevam }; 3954fe0791SFabio Estevam 40fdda6ee9SArvind Yadav static const struct clk_div_table post_div_table[] = { 4154fe0791SFabio Estevam { .val = 3, .div = 4, }, 4254fe0791SFabio Estevam { .val = 2, .div = 1, }, 4354fe0791SFabio Estevam { .val = 1, .div = 2, }, 4454fe0791SFabio Estevam { .val = 0, .div = 1, }, 4554fe0791SFabio Estevam { } 4654fe0791SFabio Estevam }; 4754fe0791SFabio Estevam 488f6d8094SFrank Li static struct clk *clks[IMX7D_CLK_END]; 498f6d8094SFrank Li static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", 508f6d8094SFrank Li "pll_enet_500m_clk", "pll_dram_main_clk", 5154fe0791SFabio Estevam "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div", 528f6d8094SFrank Li "pll_usb_main_clk", }; 538f6d8094SFrank Li 548f6d8094SFrank Li static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", 558f6d8094SFrank Li "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", 56b716aad9SAnson Huang "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div", 578f6d8094SFrank Li "pll_usb_main_clk", }; 588f6d8094SFrank Li 598f6d8094SFrank Li static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 608f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", 61b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", }; 628f6d8094SFrank Li 638f6d8094SFrank Li static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 648f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", 65b716aad9SAnson Huang "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", }; 668f6d8094SFrank Li 678f6d8094SFrank Li static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 688f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", 69b716aad9SAnson Huang "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div", 708f6d8094SFrank Li "pll_sys_pfd4_clk", }; 718f6d8094SFrank Li 728f6d8094SFrank Li static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 738f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_240m_clk", 748f6d8094SFrank Li "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", 7554fe0791SFabio Estevam "pll_audio_post_div", }; 768f6d8094SFrank Li 7792a847e3SStefan Agner static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 788f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", 79a12ec8b6SAnson Huang "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div", 80b716aad9SAnson Huang "pll_video_post_div", }; 818f6d8094SFrank Li 828f6d8094SFrank Li static const char *dram_phym_sel[] = { "pll_dram_main_clk", 838f6d8094SFrank Li "dram_phym_alt_clk", }; 848f6d8094SFrank Li 858f6d8094SFrank Li static const char *dram_sel[] = { "pll_dram_main_clk", 867e797d9fSAnson Huang "dram_alt_root_clk", }; 878f6d8094SFrank Li 888f6d8094SFrank Li static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", 898f6d8094SFrank Li "pll_sys_main_clk", "pll_enet_500m_clk", 9054fe0791SFabio Estevam "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div", 91b716aad9SAnson Huang "pll_video_post_div", }; 928f6d8094SFrank Li 938f6d8094SFrank Li static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", 948f6d8094SFrank Li "pll_sys_main_clk", "pll_enet_500m_clk", 958f6d8094SFrank Li "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk", 9654fe0791SFabio Estevam "pll_audio_post_div", "pll_sys_pfd2_270m_clk", }; 978f6d8094SFrank Li 988f6d8094SFrank Li static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk", 998f6d8094SFrank Li "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", 1008f6d8094SFrank Li "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1018f6d8094SFrank Li 1028f6d8094SFrank Li static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk", 1038f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", 1048f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", 1058f6d8094SFrank Li "pll_sys_pfd1_332m_clk", "pll_sys_pfd6_clk", }; 1068f6d8094SFrank Li 1078f6d8094SFrank Li static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk", 1088f6d8094SFrank Li "pll_enet_500m_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", 1098f6d8094SFrank Li "ext_clk_4", "pll_sys_pfd0_392m_clk", }; 1108f6d8094SFrank Li 1118f6d8094SFrank Li static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 1128f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk", 113b716aad9SAnson Huang "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", }; 1148f6d8094SFrank Li 1158f6d8094SFrank Li static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", 1168f6d8094SFrank Li "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk", 117b716aad9SAnson Huang "pll_sys_pfd2_270m_clk", "pll_video_post_div", 1188f6d8094SFrank Li "pll_usb_main_clk", }; 1198f6d8094SFrank Li 1208f6d8094SFrank Li static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", 1218f6d8094SFrank Li "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 122b716aad9SAnson Huang "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", }; 1238f6d8094SFrank Li 1248f6d8094SFrank Li static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", 1258f6d8094SFrank Li "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 126b716aad9SAnson Huang "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", }; 1278f6d8094SFrank Li 1288f6d8094SFrank Li static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", 1298f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", 130b716aad9SAnson Huang "pll_video_post_div", "ext_clk_3", }; 1318f6d8094SFrank Li 1328f6d8094SFrank Li static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 133b716aad9SAnson Huang "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", 1348f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 1358f6d8094SFrank Li 1368f6d8094SFrank Li static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 137b716aad9SAnson Huang "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", 1388f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 1398f6d8094SFrank Li 1408f6d8094SFrank Li static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 141b716aad9SAnson Huang "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", 1428f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; 1438f6d8094SFrank Li 1448f6d8094SFrank Li static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 145b716aad9SAnson Huang "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div", 1468f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; 1478f6d8094SFrank Li 1488f6d8094SFrank Li static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", 1498f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_25m_clk", 150b716aad9SAnson Huang "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div", 1518f6d8094SFrank Li "ext_clk_4", }; 1528f6d8094SFrank Li 1538f6d8094SFrank Li static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", 15454fe0791SFabio Estevam "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", 155b716aad9SAnson Huang "ext_clk_4", "pll_video_post_div", }; 1568f6d8094SFrank Li 1578f6d8094SFrank Li static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", 1588f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_25m_clk", 159b716aad9SAnson Huang "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div", 1608f6d8094SFrank Li "ext_clk_4", }; 1618f6d8094SFrank Li 1628f6d8094SFrank Li static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", 16354fe0791SFabio Estevam "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", 164b716aad9SAnson Huang "ext_clk_4", "pll_video_post_div", }; 1658f6d8094SFrank Li 1668f6d8094SFrank Li static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", 1678f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_125m_clk", 168b716aad9SAnson Huang "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div", 1698f6d8094SFrank Li "pll_sys_pfd3_clk", }; 1708f6d8094SFrank Li 1718f6d8094SFrank Li static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1728f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 1738f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk", 1748f6d8094SFrank Li "pll_usb_main_clk", }; 1758f6d8094SFrank Li 1768f6d8094SFrank Li static const char *nand_sel[] = { "osc", "pll_sys_main_clk", 1778f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk", 1788f6d8094SFrank Li "pll_enet_500m_clk", "pll_enet_250m_clk", 179b716aad9SAnson Huang "pll_video_post_div", }; 1808f6d8094SFrank Li 1818f6d8094SFrank Li static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk", 1828f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk", 1838f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1848f6d8094SFrank Li 1858f6d8094SFrank Li static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1868f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1878f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1888f6d8094SFrank Li 1898f6d8094SFrank Li static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1908f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1918f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1928f6d8094SFrank Li 1938f6d8094SFrank Li static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1948f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1958f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1968f6d8094SFrank Li 1978f6d8094SFrank Li static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk", 1988f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", 1998f6d8094SFrank Li "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", 2008f6d8094SFrank Li "ext_clk_4", }; 2018f6d8094SFrank Li 2028f6d8094SFrank Li static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", 2038f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", 2048f6d8094SFrank Li "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", 2058f6d8094SFrank Li "ext_clk_3", }; 2068f6d8094SFrank Li 2078f6d8094SFrank Li static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", 2088f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 209b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", 2108f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2118f6d8094SFrank Li 2128f6d8094SFrank Li static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", 2138f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 214b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", 2158f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2168f6d8094SFrank Li 2178f6d8094SFrank Li static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", 2188f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 219b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", 2208f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2218f6d8094SFrank Li 2228f6d8094SFrank Li static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", 2238f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 224b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk", 2258f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2268f6d8094SFrank Li 2278f6d8094SFrank Li static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", 2288f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2298f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2308f6d8094SFrank Li "pll_usb_main_clk", }; 2318f6d8094SFrank Li 2328f6d8094SFrank Li static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk", 2338f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2348f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2358f6d8094SFrank Li "pll_usb_main_clk", }; 2368f6d8094SFrank Li 2378f6d8094SFrank Li static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk", 2388f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2398f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2408f6d8094SFrank Li "pll_usb_main_clk", }; 2418f6d8094SFrank Li 2428f6d8094SFrank Li static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk", 2438f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2448f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2458f6d8094SFrank Li "pll_usb_main_clk", }; 2468f6d8094SFrank Li 2478f6d8094SFrank Li static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk", 2488f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2498f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2508f6d8094SFrank Li "pll_usb_main_clk", }; 2518f6d8094SFrank Li 2528f6d8094SFrank Li static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk", 2538f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2548f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2558f6d8094SFrank Li "pll_usb_main_clk", }; 2568f6d8094SFrank Li 2578f6d8094SFrank Li static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk", 2588f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2598f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2608f6d8094SFrank Li "pll_usb_main_clk", }; 2618f6d8094SFrank Li 2628f6d8094SFrank Li static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk", 2638f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2648f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2658f6d8094SFrank Li "pll_usb_main_clk", }; 2668f6d8094SFrank Li 2678f6d8094SFrank Li static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk", 2688f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2698f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2708f6d8094SFrank Li "pll_usb_main_clk", }; 2718f6d8094SFrank Li 2728f6d8094SFrank Li static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk", 2738f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2748f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2758f6d8094SFrank Li "pll_usb_main_clk", }; 2768f6d8094SFrank Li 2778f6d8094SFrank Li static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", 2788f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2798f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2808f6d8094SFrank Li "pll_usb_main_clk", }; 2818f6d8094SFrank Li 2828f6d8094SFrank Li static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", 28354fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 284b716aad9SAnson Huang "ext_clk_1", "ref_1m_clk", "pll_video_post_div", }; 2858f6d8094SFrank Li 2868f6d8094SFrank Li static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", 28754fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 288b716aad9SAnson Huang "ext_clk_1", "ref_1m_clk", "pll_video_post_div", }; 2898f6d8094SFrank Li 2908f6d8094SFrank Li static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", 29154fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 292b716aad9SAnson Huang "ext_clk_2", "ref_1m_clk", "pll_video_post_div", }; 2938f6d8094SFrank Li 2948f6d8094SFrank Li static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", 29554fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 296b716aad9SAnson Huang "ext_clk_2", "ref_1m_clk", "pll_video_post_div", }; 2978f6d8094SFrank Li 2988f6d8094SFrank Li static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", 29954fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 300b716aad9SAnson Huang "ext_clk_3", "ref_1m_clk", "pll_video_post_div", }; 3018f6d8094SFrank Li 3028f6d8094SFrank Li static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", 30354fe0791SFabio Estevam "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", 304b716aad9SAnson Huang "ext_clk_3", "ref_1m_clk", "pll_video_post_div", }; 3058f6d8094SFrank Li 3068f6d8094SFrank Li static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3078f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 30854fe0791SFabio Estevam "pll_usb_main_clk", "pll_audio_post_div", "pll_enet_125m_clk", 3098f6d8094SFrank Li "pll_sys_pfd7_clk", }; 3108f6d8094SFrank Li 3118f6d8094SFrank Li static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3128f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 313b716aad9SAnson Huang "pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk", 3148f6d8094SFrank Li "pll_sys_pfd7_clk", }; 3158f6d8094SFrank Li 3168f6d8094SFrank Li static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", 317b716aad9SAnson Huang "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", 31854fe0791SFabio Estevam "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", }; 3198f6d8094SFrank Li 3208f6d8094SFrank Li static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", 321b716aad9SAnson Huang "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", 32254fe0791SFabio Estevam "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", }; 3238f6d8094SFrank Li 3248f6d8094SFrank Li static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", 325b716aad9SAnson Huang "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", 32654fe0791SFabio Estevam "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", }; 3278f6d8094SFrank Li 3288f6d8094SFrank Li static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", 329b716aad9SAnson Huang "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div", 33054fe0791SFabio Estevam "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", }; 3318f6d8094SFrank Li 3328f6d8094SFrank Li static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3338f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3348f6d8094SFrank Li "pll_enet_125m_clk", "pll_usb_main_clk", "ext_clk_2", 3358f6d8094SFrank Li "ext_clk_3", }; 3368f6d8094SFrank Li 3378f6d8094SFrank Li static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3388f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3398f6d8094SFrank Li "pll_enet_125m_clk", "pll_usb_main_clk", "ref_1m_clk", 3408f6d8094SFrank Li "pll_sys_pfd1_166m_clk", }; 3418f6d8094SFrank Li 3428f6d8094SFrank Li static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3438f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 344b716aad9SAnson Huang "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div", 3458f6d8094SFrank Li "pll_usb_main_clk", }; 3468f6d8094SFrank Li 3478f6d8094SFrank Li static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3488f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 349b716aad9SAnson Huang "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div", 3508f6d8094SFrank Li "pll_usb_main_clk", }; 3518f6d8094SFrank Li 3528f6d8094SFrank Li static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", 3538f6d8094SFrank Li "pll_dram_533m_clk", "pll_usb_main_clk", 3548f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", 3558f6d8094SFrank Li "pll_enet_500m_clk", "pll_sys_pfd7_clk", }; 3568f6d8094SFrank Li 3578f6d8094SFrank Li static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", 3588f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk", 3598f6d8094SFrank Li "pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", }; 3608f6d8094SFrank Li 3618f6d8094SFrank Li static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", 3628f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", 363b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "ckil", }; 3648f6d8094SFrank Li 3658f6d8094SFrank Li static const char *lvds1_sel[] = { "pll_arm_main_clk", 3668f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", 3678f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", 3688f6d8094SFrank Li "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", 369b716aad9SAnson Huang "pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk", 3708f6d8094SFrank Li "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", 3718f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", 3728f6d8094SFrank Li "pll_dram_main_clk", }; 3738f6d8094SFrank Li 3748f6d8094SFrank Li static const char *pll_bypass_src_sel[] = { "osc", "dummy", }; 3758f6d8094SFrank Li static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", }; 3768f6d8094SFrank Li static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", }; 3778f6d8094SFrank Li static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", }; 3788f6d8094SFrank Li static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", }; 3798f6d8094SFrank Li static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; 3808f6d8094SFrank Li static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; 3818f6d8094SFrank Li 3828f6d8094SFrank Li static struct clk_onecell_data clk_data; 3838f6d8094SFrank Li 3841b9af68fSLucas Stach static struct clk ** const uart_clks[] __initconst = { 3851b9af68fSLucas Stach &clks[IMX7D_UART1_ROOT_CLK], 3861b9af68fSLucas Stach &clks[IMX7D_UART2_ROOT_CLK], 3871b9af68fSLucas Stach &clks[IMX7D_UART3_ROOT_CLK], 3881b9af68fSLucas Stach &clks[IMX7D_UART4_ROOT_CLK], 3891b9af68fSLucas Stach &clks[IMX7D_UART5_ROOT_CLK], 3901b9af68fSLucas Stach &clks[IMX7D_UART6_ROOT_CLK], 3911b9af68fSLucas Stach &clks[IMX7D_UART7_ROOT_CLK], 3921b9af68fSLucas Stach NULL 3931b9af68fSLucas Stach }; 3941b9af68fSLucas Stach 3958f6d8094SFrank Li static void __init imx7d_clocks_init(struct device_node *ccm_node) 3968f6d8094SFrank Li { 3978f6d8094SFrank Li struct device_node *np; 3988f6d8094SFrank Li void __iomem *base; 3998f6d8094SFrank Li 4008f6d8094SFrank Li clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 4018f6d8094SFrank Li clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); 4024aba2755SGary Bisson clks[IMX7D_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); 4038f6d8094SFrank Li 4048f6d8094SFrank Li np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); 4058f6d8094SFrank Li base = of_iomap(np, 0); 4068f6d8094SFrank Li WARN_ON(!base); 4078f6d8094SFrank Li 4088f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4098f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4108f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4118f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4128f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4138f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 4148f6d8094SFrank Li 415f83d3163SDong Aisheng clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f); 416ad149724SFabio Estevam clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f); 417f83d3163SDong Aisheng clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1); 418f83d3163SDong Aisheng clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0); 419f83d3163SDong Aisheng clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f); 420f83d3163SDong Aisheng clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f); 4218f6d8094SFrank Li 4228f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); 4238f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); 4248f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); 4258f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); 4268f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); 4278f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); 4288f6d8094SFrank Li 4298f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); 430afe7c08aSAnson Huang clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13); 4318f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); 4328f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); 4338f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); 4348f6d8094SFrank Li 435afe7c08aSAnson Huang clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass", 436afe7c08aSAnson Huang CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock); 43754fe0791SFabio Estevam clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", 43854fe0791SFabio Estevam CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); 43954fe0791SFabio Estevam clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", 44054fe0791SFabio Estevam CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); 441b716aad9SAnson Huang clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk", 442b716aad9SAnson Huang CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock); 443b716aad9SAnson Huang clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div", 444b716aad9SAnson Huang CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); 44554fe0791SFabio Estevam 4468f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); 4478f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); 4488f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); 4498f6d8094SFrank Li 4508f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3); 4518f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0); 4528f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1); 4538f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2); 4548f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3); 4558f6d8094SFrank Li 4568f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1); 4578f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2); 4588f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4); 4598f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2); 4608f6d8094SFrank Li 461febb6548SAnson Huang clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis_flags("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4, CLK_IS_CRITICAL); 4628f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5); 4638f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6); 4648f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12); 4658f6d8094SFrank Li 4668f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_196M] = imx_clk_fixed_factor("pll_sys_pfd0_196m", "pll_sys_pfd0_392m_clk", 1, 2); 4678f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_166M] = imx_clk_fixed_factor("pll_sys_pfd1_166m", "pll_sys_pfd1_332m_clk", 1, 2); 4688f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_135M] = imx_clk_fixed_factor("pll_sys_pfd2_135m", "pll_sys_pfd2_270m_clk", 1, 2); 4698f6d8094SFrank Li 4708f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26); 4718f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27); 4728f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28); 4738f6d8094SFrank Li 4748f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1); 4758f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2); 4768f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4); 4778f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8); 4788f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_100M] = imx_clk_fixed_factor("pll_enet_100m", "pll_enet_main_clk", 1, 10); 4798f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_50M] = imx_clk_fixed_factor("pll_enet_50m", "pll_enet_main_clk", 1, 20); 4808f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_40M] = imx_clk_fixed_factor("pll_enet_40m", "pll_enet_main_clk", 1, 25); 4818f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_25M] = imx_clk_fixed_factor("pll_enet_25m", "pll_enet_main_clk", 1, 40); 4828f6d8094SFrank Li 4838f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12); 4848f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11); 4858f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10); 4868f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9); 4878f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8); 4888f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7); 4898f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6); 4908f6d8094SFrank Li 4918f6d8094SFrank Li clks[IMX7D_LVDS1_OUT_SEL] = imx_clk_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel)); 4928f6d8094SFrank Li clks[IMX7D_LVDS1_OUT_CLK] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); 4938f6d8094SFrank Li 4948f6d8094SFrank Li np = ccm_node; 4958f6d8094SFrank Li base = of_iomap(np, 0); 4968f6d8094SFrank Li WARN_ON(!base); 4978f6d8094SFrank Li 498cbeac74aSDong Aisheng clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); 499cbeac74aSDong Aisheng clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); 500cbeac74aSDong Aisheng clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); 501cbeac74aSDong Aisheng clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); 502cbeac74aSDong Aisheng clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); 503cbeac74aSDong Aisheng clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux2("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); 504cbeac74aSDong Aisheng clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); 505cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux2("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); 506cbeac74aSDong Aisheng clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); 507cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux2("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); 508cbeac74aSDong Aisheng clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); 509cbeac74aSDong Aisheng clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux2("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); 510cbeac74aSDong Aisheng clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); 511cbeac74aSDong Aisheng clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); 512cbeac74aSDong Aisheng clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); 513cbeac74aSDong Aisheng clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); 514cbeac74aSDong Aisheng clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); 515cbeac74aSDong Aisheng clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); 516cbeac74aSDong Aisheng clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); 517cbeac74aSDong Aisheng clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux2("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); 518cbeac74aSDong Aisheng clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux2("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); 519cbeac74aSDong Aisheng clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux2("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); 520cbeac74aSDong Aisheng clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux2("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); 521cbeac74aSDong Aisheng clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux2("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); 522cbeac74aSDong Aisheng clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux2("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); 523cbeac74aSDong Aisheng clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux2("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); 524cbeac74aSDong Aisheng clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux2("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); 525cbeac74aSDong Aisheng clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux2("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); 526cbeac74aSDong Aisheng clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux2("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); 527cbeac74aSDong Aisheng clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux2("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); 528cbeac74aSDong Aisheng clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux2("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); 529cbeac74aSDong Aisheng clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux2("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); 530cbeac74aSDong Aisheng clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux2("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); 531cbeac74aSDong Aisheng clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux2("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); 532cbeac74aSDong Aisheng clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); 533cbeac74aSDong Aisheng clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); 534cbeac74aSDong Aisheng clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux2("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); 535cbeac74aSDong Aisheng clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux2("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); 536cbeac74aSDong Aisheng clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux2("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); 537cbeac74aSDong Aisheng clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux2("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); 538cbeac74aSDong Aisheng clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux2("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); 539cbeac74aSDong Aisheng clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux2("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); 540cbeac74aSDong Aisheng clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux2("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); 541cbeac74aSDong Aisheng clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux2("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); 542cbeac74aSDong Aisheng clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux2("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); 543cbeac74aSDong Aisheng clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux2("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); 544cbeac74aSDong Aisheng clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux2("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); 545cbeac74aSDong Aisheng clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); 546cbeac74aSDong Aisheng clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); 547cbeac74aSDong Aisheng clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux2("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); 548cbeac74aSDong Aisheng clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux2("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); 549cbeac74aSDong Aisheng clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux2("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); 550cbeac74aSDong Aisheng clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux2("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); 551cbeac74aSDong Aisheng clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux2("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); 552cbeac74aSDong Aisheng clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux2("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); 553cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux2("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); 554cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux2("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); 555cbeac74aSDong Aisheng clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux2("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); 556cbeac74aSDong Aisheng clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux2("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); 557cbeac74aSDong Aisheng clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux2("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); 558cbeac74aSDong Aisheng clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux2("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); 559cbeac74aSDong Aisheng clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux2("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); 560cbeac74aSDong Aisheng clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux2("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); 561cbeac74aSDong Aisheng clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux2("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); 562cbeac74aSDong Aisheng clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux2("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); 563cbeac74aSDong Aisheng clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux2("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); 564cbeac74aSDong Aisheng clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux2("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); 565cbeac74aSDong Aisheng clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux2("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); 566cbeac74aSDong Aisheng clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux2("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); 567cbeac74aSDong Aisheng clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux2("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); 5688f6d8094SFrank Li 569cbeac74aSDong Aisheng clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); 570cbeac74aSDong Aisheng clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); 571cbeac74aSDong Aisheng clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate3("axi_cg", "axi_src", base + 0x8800, 28); 572cbeac74aSDong Aisheng clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); 573cbeac74aSDong Aisheng clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); 574cbeac74aSDong Aisheng clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate3("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); 575cbeac74aSDong Aisheng clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28); 576cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate3("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); 577cbeac74aSDong Aisheng clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate3("dram_cg", "dram_src", base + 0x9880, 28); 578cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate3("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); 579cbeac74aSDong Aisheng clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); 580cbeac74aSDong Aisheng clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate3("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); 581cbeac74aSDong Aisheng clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate3("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); 582cbeac74aSDong Aisheng clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate3("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); 583cbeac74aSDong Aisheng clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate3("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); 584cbeac74aSDong Aisheng clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate3("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); 585cbeac74aSDong Aisheng clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate3("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); 586cbeac74aSDong Aisheng clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate3("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); 587cbeac74aSDong Aisheng clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate3("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); 588cbeac74aSDong Aisheng clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate3("sai1_cg", "sai1_src", base + 0xa500, 28); 589cbeac74aSDong Aisheng clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate3("sai2_cg", "sai2_src", base + 0xa580, 28); 590cbeac74aSDong Aisheng clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate3("sai3_cg", "sai3_src", base + 0xa600, 28); 591cbeac74aSDong Aisheng clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate3("spdif_cg", "spdif_src", base + 0xa680, 28); 592cbeac74aSDong Aisheng clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); 593cbeac74aSDong Aisheng clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); 594cbeac74aSDong Aisheng clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); 595cbeac74aSDong Aisheng clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); 596cbeac74aSDong Aisheng clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate3("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); 597cbeac74aSDong Aisheng clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate3("eim_cg", "eim_src", base + 0xa980, 28); 598cbeac74aSDong Aisheng clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xaa00, 28); 599cbeac74aSDong Aisheng clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xaa80, 28); 600cbeac74aSDong Aisheng clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); 601cbeac74aSDong Aisheng clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); 602cbeac74aSDong Aisheng clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate3("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); 603cbeac74aSDong Aisheng clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate3("can1_cg", "can1_src", base + 0xac80, 28); 604cbeac74aSDong Aisheng clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate3("can2_cg", "can2_src", base + 0xad00, 28); 605cbeac74aSDong Aisheng clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad80, 28); 606cbeac74aSDong Aisheng clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xae00, 28); 607cbeac74aSDong Aisheng clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae80, 28); 608cbeac74aSDong Aisheng clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xaf00, 28); 609cbeac74aSDong Aisheng clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf80, 28); 610cbeac74aSDong Aisheng clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xb000, 28); 611cbeac74aSDong Aisheng clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb080, 28); 612cbeac74aSDong Aisheng clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb100, 28); 613cbeac74aSDong Aisheng clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate3("uart5_cg", "uart5_src", base + 0xb180, 28); 614cbeac74aSDong Aisheng clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate3("uart6_cg", "uart6_src", base + 0xb200, 28); 615cbeac74aSDong Aisheng clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate3("uart7_cg", "uart7_src", base + 0xb280, 28); 616cbeac74aSDong Aisheng clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); 617cbeac74aSDong Aisheng clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); 618cbeac74aSDong Aisheng clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); 619cbeac74aSDong Aisheng clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate3("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); 620cbeac74aSDong Aisheng clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb500, 28); 621cbeac74aSDong Aisheng clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb580, 28); 622cbeac74aSDong Aisheng clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb600, 28); 623cbeac74aSDong Aisheng clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb680, 28); 624cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate3("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); 625cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate3("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); 626cbeac74aSDong Aisheng clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate3("sim1_cg", "sim1_src", base + 0xb800, 28); 627cbeac74aSDong Aisheng clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate3("sim2_cg", "sim2_src", base + 0xb880, 28); 628cbeac74aSDong Aisheng clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb900, 28); 629cbeac74aSDong Aisheng clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate3("gpt2_cg", "gpt2_src", base + 0xb980, 28); 630cbeac74aSDong Aisheng clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate3("gpt3_cg", "gpt3_src", base + 0xbA00, 28); 631cbeac74aSDong Aisheng clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate3("gpt4_cg", "gpt4_src", base + 0xbA80, 28); 632cbeac74aSDong Aisheng clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate3("trace_cg", "trace_src", base + 0xbb00, 28); 633cbeac74aSDong Aisheng clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xbb80, 28); 634cbeac74aSDong Aisheng clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate3("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); 635cbeac74aSDong Aisheng clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate3("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); 636cbeac74aSDong Aisheng clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xbd00, 28); 637cbeac74aSDong Aisheng clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate3("clko1_cg", "clko1_src", base + 0xbd80, 28); 638cbeac74aSDong Aisheng clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xbe00, 28); 6398f6d8094SFrank Li 640cbeac74aSDong Aisheng clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider2("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); 641cbeac74aSDong Aisheng clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); 642cbeac74aSDong Aisheng clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); 643cbeac74aSDong Aisheng clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider2("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); 644cbeac74aSDong Aisheng clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); 645cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); 646cbeac74aSDong Aisheng clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); 647cbeac74aSDong Aisheng clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider2("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); 648cbeac74aSDong Aisheng clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider2("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); 649cbeac74aSDong Aisheng clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider2("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); 650cbeac74aSDong Aisheng clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); 651cbeac74aSDong Aisheng clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); 652cbeac74aSDong Aisheng clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); 653cbeac74aSDong Aisheng clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); 654cbeac74aSDong Aisheng clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); 655cbeac74aSDong Aisheng clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider2("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); 656cbeac74aSDong Aisheng clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider2("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); 657cbeac74aSDong Aisheng clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider2("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); 658cbeac74aSDong Aisheng clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider2("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); 659cbeac74aSDong Aisheng clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); 660cbeac74aSDong Aisheng clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); 661cbeac74aSDong Aisheng clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); 662cbeac74aSDong Aisheng clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); 663cbeac74aSDong Aisheng clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); 664cbeac74aSDong Aisheng clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider2("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); 665cbeac74aSDong Aisheng clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); 666cbeac74aSDong Aisheng clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); 667cbeac74aSDong Aisheng clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); 668cbeac74aSDong Aisheng clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); 669cbeac74aSDong Aisheng clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider2("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); 670cbeac74aSDong Aisheng clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); 671cbeac74aSDong Aisheng clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); 672cbeac74aSDong Aisheng clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); 673cbeac74aSDong Aisheng clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); 674cbeac74aSDong Aisheng clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); 675cbeac74aSDong Aisheng clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); 676cbeac74aSDong Aisheng clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); 677cbeac74aSDong Aisheng clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); 678cbeac74aSDong Aisheng clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); 679cbeac74aSDong Aisheng clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); 680cbeac74aSDong Aisheng clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider2("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); 681cbeac74aSDong Aisheng clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider2("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); 682cbeac74aSDong Aisheng clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider2("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); 683cbeac74aSDong Aisheng clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); 684cbeac74aSDong Aisheng clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); 685cbeac74aSDong Aisheng clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); 686cbeac74aSDong Aisheng clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider2("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); 687cbeac74aSDong Aisheng clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); 688cbeac74aSDong Aisheng clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); 689cbeac74aSDong Aisheng clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); 690cbeac74aSDong Aisheng clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); 691cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider2("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); 692cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider2("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); 693cbeac74aSDong Aisheng clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider2("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); 694cbeac74aSDong Aisheng clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider2("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); 695cbeac74aSDong Aisheng clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); 696cbeac74aSDong Aisheng clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider2("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); 697cbeac74aSDong Aisheng clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider2("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); 698cbeac74aSDong Aisheng clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider2("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); 699cbeac74aSDong Aisheng clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider2("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); 700cbeac74aSDong Aisheng clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); 701cbeac74aSDong Aisheng clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); 702cbeac74aSDong Aisheng clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); 703cbeac74aSDong Aisheng clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); 704cbeac74aSDong Aisheng clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); 705cbeac74aSDong Aisheng clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); 7068f6d8094SFrank Li 707cbeac74aSDong Aisheng clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); 708cbeac74aSDong Aisheng clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); 709cbeac74aSDong Aisheng clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); 710cbeac74aSDong Aisheng clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); 711cbeac74aSDong Aisheng clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); 712e24f5287SStefan Agner clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_divider2("nand_usdhc_root_clk", "nand_usdhc_pre_div", base + 0x8980, 0, 6); 7139a6e9042SDong Aisheng clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6); 714febb6548SAnson Huang clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT); 715cbeac74aSDong Aisheng clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3); 716cbeac74aSDong Aisheng clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); 717cbeac74aSDong Aisheng clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); 718cbeac74aSDong Aisheng clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider2("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); 719cbeac74aSDong Aisheng clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider2("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); 720cbeac74aSDong Aisheng clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider2("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); 721cbeac74aSDong Aisheng clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider2("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); 722cbeac74aSDong Aisheng clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); 723cbeac74aSDong Aisheng clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); 724cbeac74aSDong Aisheng clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); 7254dd5d5b5SRui Miguel Silva clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6); 726cbeac74aSDong Aisheng clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); 727cbeac74aSDong Aisheng clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); 728cbeac74aSDong Aisheng clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); 729cbeac74aSDong Aisheng clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider2("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); 730cbeac74aSDong Aisheng clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider2("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); 731cbeac74aSDong Aisheng clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); 732cbeac74aSDong Aisheng clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); 733cbeac74aSDong Aisheng clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); 734f93f2ed9SAnson Huang clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); 735cbeac74aSDong Aisheng clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); 73622039d15SStefan Agner clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); 737cbeac74aSDong Aisheng clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); 738cbeac74aSDong Aisheng clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); 739cbeac74aSDong Aisheng clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); 740cbeac74aSDong Aisheng clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider2("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); 741cbeac74aSDong Aisheng clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); 742cbeac74aSDong Aisheng clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); 743cbeac74aSDong Aisheng clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider2("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); 744cbeac74aSDong Aisheng clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider2("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); 745cbeac74aSDong Aisheng clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider2("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); 746cbeac74aSDong Aisheng clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider2("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); 747cbeac74aSDong Aisheng clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider2("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); 748cbeac74aSDong Aisheng clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider2("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); 749cbeac74aSDong Aisheng clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider2("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); 750cbeac74aSDong Aisheng clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider2("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); 751cbeac74aSDong Aisheng clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider2("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); 752cbeac74aSDong Aisheng clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider2("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); 753cbeac74aSDong Aisheng clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider2("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); 754cbeac74aSDong Aisheng clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider2("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); 755cbeac74aSDong Aisheng clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider2("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); 756cbeac74aSDong Aisheng clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider2("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); 757cbeac74aSDong Aisheng clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider2("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); 758cbeac74aSDong Aisheng clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider2("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); 759cbeac74aSDong Aisheng clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider2("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); 760cbeac74aSDong Aisheng clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider2("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); 761cbeac74aSDong Aisheng clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider2("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); 762cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider2("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); 763cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider2("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); 764cbeac74aSDong Aisheng clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider2("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); 765cbeac74aSDong Aisheng clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider2("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); 766cbeac74aSDong Aisheng clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider2("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); 767cbeac74aSDong Aisheng clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider2("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); 768cbeac74aSDong Aisheng clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider2("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); 769cbeac74aSDong Aisheng clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider2("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); 770cbeac74aSDong Aisheng clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider2("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); 771cbeac74aSDong Aisheng clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider2("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); 772cbeac74aSDong Aisheng clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider2("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); 773cbeac74aSDong Aisheng clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider2("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); 774cbeac74aSDong Aisheng clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); 775cbeac74aSDong Aisheng clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); 776cbeac74aSDong Aisheng clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); 7778f6d8094SFrank Li 778febb6548SAnson Huang clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 779cbeac74aSDong Aisheng clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); 780febb6548SAnson Huang clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 781cbeac74aSDong Aisheng clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); 782cbeac74aSDong Aisheng clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); 783edc5a8e7SAdriana Reus clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "main_axi_root_clk", base + 0x4110, 0); 7849a6e9042SDong Aisheng clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0); 785febb6548SAnson Huang clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 786febb6548SAnson Huang clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 787febb6548SAnson Huang clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 788febb6548SAnson Huang clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); 7896847c4c2SFabio Estevam clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0); 790d931ba53SAnson Huang clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0); 79130343897SOleksij Rempel clks[IMX7D_MU_ROOT_CLK] = imx_clk_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0); 792baf15cbfSRui Miguel Silva clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0); 7935fcb4c76SPeter Chen clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0); 79496e9dff6SFabio Estevam clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); 795cbeac74aSDong Aisheng clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); 796cbeac74aSDong Aisheng clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); 797cbeac74aSDong Aisheng clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); 798cbeac74aSDong Aisheng clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); 799cbeac74aSDong Aisheng clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); 800cbeac74aSDong Aisheng clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); 801cbeac74aSDong Aisheng clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); 8029c7150daSAnson Huang clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1); 8039c7150daSAnson Huang clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1); 8049c7150daSAnson Huang clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2); 8059c7150daSAnson Huang clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2); 80606981025SFabio Estevam clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1); 80706981025SFabio Estevam clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1); 80806981025SFabio Estevam clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2); 80906981025SFabio Estevam clks[IMX7D_SAI2_IPG_CLK] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root_clk", base + 0x48d0, 0, &share_count_sai2); 81006981025SFabio Estevam clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3); 81106981025SFabio Estevam clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3); 812cbeac74aSDong Aisheng clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); 813cbeac74aSDong Aisheng clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); 81422039d15SStefan Agner clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); 81522039d15SStefan Agner clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); 816cbeac74aSDong Aisheng clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); 817cbeac74aSDong Aisheng clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); 818cbeac74aSDong Aisheng clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); 819cbeac74aSDong Aisheng clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate4("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); 820cbeac74aSDong Aisheng clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0); 821cbeac74aSDong Aisheng clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0); 822cbeac74aSDong Aisheng clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate4("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); 823cbeac74aSDong Aisheng clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate4("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); 824cbeac74aSDong Aisheng clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate4("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); 825cbeac74aSDong Aisheng clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate4("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); 826cbeac74aSDong Aisheng clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate4("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); 827cbeac74aSDong Aisheng clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate4("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); 828cbeac74aSDong Aisheng clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate4("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); 829cbeac74aSDong Aisheng clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate4("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); 830cbeac74aSDong Aisheng clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate4("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); 831cbeac74aSDong Aisheng clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate4("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); 832cbeac74aSDong Aisheng clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate4("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); 833cbeac74aSDong Aisheng clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); 834cbeac74aSDong Aisheng clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); 835cbeac74aSDong Aisheng clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); 836cbeac74aSDong Aisheng clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate4("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); 837cbeac74aSDong Aisheng clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate4("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); 838cbeac74aSDong Aisheng clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate4("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); 839cbeac74aSDong Aisheng clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate4("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); 840cbeac74aSDong Aisheng clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate4("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); 841cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate4("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); 842cbeac74aSDong Aisheng clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate4("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); 843cbeac74aSDong Aisheng clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate4("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); 844cbeac74aSDong Aisheng clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate4("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); 845cbeac74aSDong Aisheng clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate4("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); 846cbeac74aSDong Aisheng clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate4("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); 847cbeac74aSDong Aisheng clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate4("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); 848cbeac74aSDong Aisheng clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate4("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); 849cbeac74aSDong Aisheng clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate4("trace_root_clk", "trace_post_div", base + 0x4300, 0); 850cbeac74aSDong Aisheng clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate4("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); 851cbeac74aSDong Aisheng clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); 852cbeac74aSDong Aisheng clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); 853cbeac74aSDong Aisheng clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); 8541691cc37SStefan Agner clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0); 855cbeac74aSDong Aisheng clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); 856cbeac74aSDong Aisheng clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); 857cbeac74aSDong Aisheng clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); 8585fcb4c76SPeter Chen clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0); 8595fcb4c76SPeter Chen clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); 8605fcb4c76SPeter Chen clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); 861cbeac74aSDong Aisheng clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); 8628f6d8094SFrank Li 8638f6d8094SFrank Li clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 8648f6d8094SFrank Li 865fdb868cdSBai Ping clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk", 866fdb868cdSBai Ping clks[IMX7D_ARM_A7_ROOT_CLK], 867fdb868cdSBai Ping clks[IMX7D_ARM_A7_ROOT_SRC], 868fdb868cdSBai Ping clks[IMX7D_PLL_ARM_MAIN_CLK], 869fdb868cdSBai Ping clks[IMX7D_PLL_SYS_MAIN_CLK]); 870fdb868cdSBai Ping 87131cbb57dSBai Ping imx_check_clocks(clks, ARRAY_SIZE(clks)); 8728f6d8094SFrank Li 8738f6d8094SFrank Li clk_data.clks = clks; 8748f6d8094SFrank Li clk_data.clk_num = ARRAY_SIZE(clks); 8758f6d8094SFrank Li of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 8768f6d8094SFrank Li 8778d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); 8788d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); 8798d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); 8808d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); 8818d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); 8828d41e653SDong Aisheng clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); 8838d41e653SDong Aisheng 884b4f5e1ffSRui Miguel Silva clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]); 885b4f5e1ffSRui Miguel Silva 8868f6d8094SFrank Li /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ 8878f6d8094SFrank Li clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 8888f6d8094SFrank Li 8898f6d8094SFrank Li /* set uart module clock's parent clock source that must be great then 80MHz */ 8908f6d8094SFrank Li clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 8918f6d8094SFrank Li 8925fcb4c76SPeter Chen /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */ 8935fcb4c76SPeter Chen clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); 8945fcb4c76SPeter Chen clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1); 8955fcb4c76SPeter Chen 8961b9af68fSLucas Stach imx_register_uart_clocks(uart_clks); 8971b9af68fSLucas Stach 8988f6d8094SFrank Li } 8998f6d8094SFrank Li CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); 900