18f6d8094SFrank Li /* 28f6d8094SFrank Li * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 38f6d8094SFrank Li * 48f6d8094SFrank Li * The code contained herein is licensed under the GNU General Public 58f6d8094SFrank Li * License. You may obtain a copy of the GNU General Public License 68f6d8094SFrank Li * Version 2 or later at the following locations: 78f6d8094SFrank Li * 88f6d8094SFrank Li * http://www.opensource.org/licenses/gpl-license.html 98f6d8094SFrank Li * http://www.gnu.org/copyleft/gpl.html 108f6d8094SFrank Li */ 118f6d8094SFrank Li 128f6d8094SFrank Li #include <dt-bindings/clock/imx7d-clock.h> 138f6d8094SFrank Li #include <linux/clk.h> 148f6d8094SFrank Li #include <linux/clkdev.h> 158f6d8094SFrank Li #include <linux/err.h> 168f6d8094SFrank Li #include <linux/init.h> 178f6d8094SFrank Li #include <linux/io.h> 188f6d8094SFrank Li #include <linux/of.h> 198f6d8094SFrank Li #include <linux/of_address.h> 208f6d8094SFrank Li #include <linux/of_irq.h> 218f6d8094SFrank Li #include <linux/types.h> 228f6d8094SFrank Li 238f6d8094SFrank Li #include "clk.h" 248f6d8094SFrank Li 258f6d8094SFrank Li static struct clk *clks[IMX7D_CLK_END]; 268f6d8094SFrank Li static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", 278f6d8094SFrank Li "pll_enet_500m_clk", "pll_dram_main_clk", 288f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_main_clk", 298f6d8094SFrank Li "pll_usb_main_clk", }; 308f6d8094SFrank Li 318f6d8094SFrank Li static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", 328f6d8094SFrank Li "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", 338f6d8094SFrank Li "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", 348f6d8094SFrank Li "pll_usb_main_clk", }; 358f6d8094SFrank Li 368f6d8094SFrank Li static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk", 378f6d8094SFrank Li "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk", 388f6d8094SFrank Li "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", 398f6d8094SFrank Li "pll_usb_main_clk", }; 408f6d8094SFrank Li 418f6d8094SFrank Li static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 428f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", 438f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_sys_pfd7_clk", }; 448f6d8094SFrank Li 458f6d8094SFrank Li static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 468f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", 478f6d8094SFrank Li "pll_sys_pfd7_clk", "pll_audio_main_clk", "pll_video_main_clk", }; 488f6d8094SFrank Li 498f6d8094SFrank Li static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 508f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_250m_clk", 518f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_audio_main_clk", "pll_video_main_clk", 528f6d8094SFrank Li "pll_sys_pfd4_clk", }; 538f6d8094SFrank Li 548f6d8094SFrank Li static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", 558f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_240m_clk", 568f6d8094SFrank Li "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", 578f6d8094SFrank Li "pll_audio_main_clk", }; 588f6d8094SFrank Li 598f6d8094SFrank Li static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 608f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", 618f6d8094SFrank Li "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk", 628f6d8094SFrank Li "pll_video_main_clk", }; 638f6d8094SFrank Li 648f6d8094SFrank Li static const char *dram_phym_sel[] = { "pll_dram_main_clk", 658f6d8094SFrank Li "dram_phym_alt_clk", }; 668f6d8094SFrank Li 678f6d8094SFrank Li static const char *dram_sel[] = { "pll_dram_main_clk", 688f6d8094SFrank Li "dram_alt_clk", }; 698f6d8094SFrank Li 708f6d8094SFrank Li static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", 718f6d8094SFrank Li "pll_sys_main_clk", "pll_enet_500m_clk", 728f6d8094SFrank Li "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_main_clk", 738f6d8094SFrank Li "pll_video_main_clk", }; 748f6d8094SFrank Li 758f6d8094SFrank Li static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", 768f6d8094SFrank Li "pll_sys_main_clk", "pll_enet_500m_clk", 778f6d8094SFrank Li "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk", 788f6d8094SFrank Li "pll_audio_main_clk", "pll_sys_pfd2_270m_clk", }; 798f6d8094SFrank Li 808f6d8094SFrank Li static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk", 818f6d8094SFrank Li "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", 828f6d8094SFrank Li "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 838f6d8094SFrank Li 848f6d8094SFrank Li static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk", 858f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", 868f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", 878f6d8094SFrank Li "pll_sys_pfd1_332m_clk", "pll_sys_pfd6_clk", }; 888f6d8094SFrank Li 898f6d8094SFrank Li static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk", 908f6d8094SFrank Li "pll_enet_500m_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", 918f6d8094SFrank Li "ext_clk_4", "pll_sys_pfd0_392m_clk", }; 928f6d8094SFrank Li 938f6d8094SFrank Li static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 948f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk", 958f6d8094SFrank Li "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", }; 968f6d8094SFrank Li 978f6d8094SFrank Li static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", 988f6d8094SFrank Li "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk", 998f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_video_main_clk", 1008f6d8094SFrank Li "pll_usb_main_clk", }; 1018f6d8094SFrank Li 1028f6d8094SFrank Li static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", 1038f6d8094SFrank Li "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 1048f6d8094SFrank Li "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; 1058f6d8094SFrank Li 1068f6d8094SFrank Li static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", 1078f6d8094SFrank Li "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", 1088f6d8094SFrank Li "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; 1098f6d8094SFrank Li 1108f6d8094SFrank Li static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", 1118f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", 1128f6d8094SFrank Li "pll_video_main_clk", "ext_clk_3", }; 1138f6d8094SFrank Li 1148f6d8094SFrank Li static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1158f6d8094SFrank Li "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", 1168f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 1178f6d8094SFrank Li 1188f6d8094SFrank Li static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1198f6d8094SFrank Li "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", 1208f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; 1218f6d8094SFrank Li 1228f6d8094SFrank Li static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1238f6d8094SFrank Li "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", 1248f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; 1258f6d8094SFrank Li 1268f6d8094SFrank Li static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1278f6d8094SFrank Li "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", 1288f6d8094SFrank Li "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; 1298f6d8094SFrank Li 1308f6d8094SFrank Li static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", 1318f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_25m_clk", 1328f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", 1338f6d8094SFrank Li "ext_clk_4", }; 1348f6d8094SFrank Li 1358f6d8094SFrank Li static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", 1368f6d8094SFrank Li "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", 1378f6d8094SFrank Li "ext_clk_4", "pll_video_main_clk", }; 1388f6d8094SFrank Li 1398f6d8094SFrank Li static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", 1408f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_25m_clk", 1418f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", 1428f6d8094SFrank Li "ext_clk_4", }; 1438f6d8094SFrank Li 1448f6d8094SFrank Li static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", 1458f6d8094SFrank Li "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", 1468f6d8094SFrank Li "ext_clk_4", "pll_video_main_clk", }; 1478f6d8094SFrank Li 1488f6d8094SFrank Li static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", 1498f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_125m_clk", 1508f6d8094SFrank Li "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", 1518f6d8094SFrank Li "pll_sys_pfd3_clk", }; 1528f6d8094SFrank Li 1538f6d8094SFrank Li static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 1548f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 1558f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk", 1568f6d8094SFrank Li "pll_usb_main_clk", }; 1578f6d8094SFrank Li 1588f6d8094SFrank Li static const char *nand_sel[] = { "osc", "pll_sys_main_clk", 1598f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk", 1608f6d8094SFrank Li "pll_enet_500m_clk", "pll_enet_250m_clk", 1618f6d8094SFrank Li "pll_video_main_clk", }; 1628f6d8094SFrank Li 1638f6d8094SFrank Li static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk", 1648f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk", 1658f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1668f6d8094SFrank Li 1678f6d8094SFrank Li static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1688f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1698f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1708f6d8094SFrank Li 1718f6d8094SFrank Li static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1728f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1738f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1748f6d8094SFrank Li 1758f6d8094SFrank Li static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk", 1768f6d8094SFrank Li "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", 1778f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; 1788f6d8094SFrank Li 1798f6d8094SFrank Li static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk", 1808f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", 1818f6d8094SFrank Li "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", 1828f6d8094SFrank Li "ext_clk_4", }; 1838f6d8094SFrank Li 1848f6d8094SFrank Li static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", 1858f6d8094SFrank Li "pll_dram_533m_clk", "pll_sys_main_clk", 1868f6d8094SFrank Li "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", 1878f6d8094SFrank Li "ext_clk_3", }; 1888f6d8094SFrank Li 1898f6d8094SFrank Li static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", 1908f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 1918f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", 1928f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 1938f6d8094SFrank Li 1948f6d8094SFrank Li static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", 1958f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 1968f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", 1978f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 1988f6d8094SFrank Li 1998f6d8094SFrank Li static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", 2008f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 2018f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", 2028f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2038f6d8094SFrank Li 2048f6d8094SFrank Li static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", 2058f6d8094SFrank Li "pll_enet_50m_clk", "pll_dram_533m_clk", 2068f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", 2078f6d8094SFrank Li "pll_sys_pfd2_135m_clk", }; 2088f6d8094SFrank Li 2098f6d8094SFrank Li static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", 2108f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2118f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2128f6d8094SFrank Li "pll_usb_main_clk", }; 2138f6d8094SFrank Li 2148f6d8094SFrank Li static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk", 2158f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2168f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2178f6d8094SFrank Li "pll_usb_main_clk", }; 2188f6d8094SFrank Li 2198f6d8094SFrank Li static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk", 2208f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2218f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2228f6d8094SFrank Li "pll_usb_main_clk", }; 2238f6d8094SFrank Li 2248f6d8094SFrank Li static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk", 2258f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2268f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2278f6d8094SFrank Li "pll_usb_main_clk", }; 2288f6d8094SFrank Li 2298f6d8094SFrank Li static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk", 2308f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2318f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2328f6d8094SFrank Li "pll_usb_main_clk", }; 2338f6d8094SFrank Li 2348f6d8094SFrank Li static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk", 2358f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2368f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", 2378f6d8094SFrank Li "pll_usb_main_clk", }; 2388f6d8094SFrank Li 2398f6d8094SFrank Li static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk", 2408f6d8094SFrank Li "pll_enet_40m_clk", "pll_enet_100m_clk", 2418f6d8094SFrank Li "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", 2428f6d8094SFrank Li "pll_usb_main_clk", }; 2438f6d8094SFrank Li 2448f6d8094SFrank Li static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk", 2458f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2468f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2478f6d8094SFrank Li "pll_usb_main_clk", }; 2488f6d8094SFrank Li 2498f6d8094SFrank Li static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk", 2508f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2518f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2528f6d8094SFrank Li "pll_usb_main_clk", }; 2538f6d8094SFrank Li 2548f6d8094SFrank Li static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk", 2558f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2568f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2578f6d8094SFrank Li "pll_usb_main_clk", }; 2588f6d8094SFrank Li 2598f6d8094SFrank Li static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", 2608f6d8094SFrank Li "pll_enet_40m_clk", "pll_sys_main_120m_clk", 2618f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", 2628f6d8094SFrank Li "pll_usb_main_clk", }; 2638f6d8094SFrank Li 2648f6d8094SFrank Li static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", 2658f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2668f6d8094SFrank Li "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; 2678f6d8094SFrank Li 2688f6d8094SFrank Li static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", 2698f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2708f6d8094SFrank Li "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; 2718f6d8094SFrank Li 2728f6d8094SFrank Li static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", 2738f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2748f6d8094SFrank Li "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; 2758f6d8094SFrank Li 2768f6d8094SFrank Li static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", 2778f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2788f6d8094SFrank Li "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; 2798f6d8094SFrank Li 2808f6d8094SFrank Li static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", 2818f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2828f6d8094SFrank Li "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; 2838f6d8094SFrank Li 2848f6d8094SFrank Li static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", 2858f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", 2868f6d8094SFrank Li "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; 2878f6d8094SFrank Li 2888f6d8094SFrank Li static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 2898f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 2908f6d8094SFrank Li "pll_usb_main_clk", "pll_audio_main_clk", "pll_enet_125m_clk", 2918f6d8094SFrank Li "pll_sys_pfd7_clk", }; 2928f6d8094SFrank Li 2938f6d8094SFrank Li static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 2948f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 2958f6d8094SFrank Li "pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk", 2968f6d8094SFrank Li "pll_sys_pfd7_clk", }; 2978f6d8094SFrank Li 2988f6d8094SFrank Li static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", 2998f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 3008f6d8094SFrank Li "ref_1m_clk", "pll_audio_main_clk", "ext_clk_1", }; 3018f6d8094SFrank Li 3028f6d8094SFrank Li static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", 3038f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 3048f6d8094SFrank Li "ref_1m_clk", "pll_audio_main_clk", "ext_clk_2", }; 3058f6d8094SFrank Li 3068f6d8094SFrank Li static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", 3078f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 3088f6d8094SFrank Li "ref_1m_clk", "pll_audio_main_clk", "ext_clk_3", }; 3098f6d8094SFrank Li 3108f6d8094SFrank Li static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", 3118f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", 3128f6d8094SFrank Li "ref_1m_clk", "pll_audio_main_clk", "ext_clk_4", }; 3138f6d8094SFrank Li 3148f6d8094SFrank Li static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3158f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3168f6d8094SFrank Li "pll_enet_125m_clk", "pll_usb_main_clk", "ext_clk_2", 3178f6d8094SFrank Li "ext_clk_3", }; 3188f6d8094SFrank Li 3198f6d8094SFrank Li static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3208f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3218f6d8094SFrank Li "pll_enet_125m_clk", "pll_usb_main_clk", "ref_1m_clk", 3228f6d8094SFrank Li "pll_sys_pfd1_166m_clk", }; 3238f6d8094SFrank Li 3248f6d8094SFrank Li static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3258f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3268f6d8094SFrank Li "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", 3278f6d8094SFrank Li "pll_usb_main_clk", }; 3288f6d8094SFrank Li 3298f6d8094SFrank Li static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", 3308f6d8094SFrank Li "pll_sys_main_120m_clk", "pll_dram_533m_clk", 3318f6d8094SFrank Li "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", 3328f6d8094SFrank Li "pll_usb_main_clk", }; 3338f6d8094SFrank Li 3348f6d8094SFrank Li static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", 3358f6d8094SFrank Li "pll_dram_533m_clk", "pll_usb_main_clk", 3368f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", 3378f6d8094SFrank Li "pll_enet_500m_clk", "pll_sys_pfd7_clk", }; 3388f6d8094SFrank Li 3398f6d8094SFrank Li static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", 3408f6d8094SFrank Li "pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk", 3418f6d8094SFrank Li "pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", }; 3428f6d8094SFrank Li 3438f6d8094SFrank Li static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", 3448f6d8094SFrank Li "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", 3454aba2755SGary Bisson "pll_audio_main_clk", "pll_video_main_clk", "ckil", }; 3468f6d8094SFrank Li 3478f6d8094SFrank Li static const char *lvds1_sel[] = { "pll_arm_main_clk", 3488f6d8094SFrank Li "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", 3498f6d8094SFrank Li "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", 3508f6d8094SFrank Li "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", 3518f6d8094SFrank Li "pll_audio_main_clk", "pll_video_main_clk", "pll_enet_500m_clk", 3528f6d8094SFrank Li "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", 3538f6d8094SFrank Li "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", 3548f6d8094SFrank Li "pll_dram_main_clk", }; 3558f6d8094SFrank Li 3568f6d8094SFrank Li static const char *pll_bypass_src_sel[] = { "osc", "dummy", }; 3578f6d8094SFrank Li static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", }; 3588f6d8094SFrank Li static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", }; 3598f6d8094SFrank Li static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", }; 3608f6d8094SFrank Li static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", }; 3618f6d8094SFrank Li static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; 3628f6d8094SFrank Li static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; 3638f6d8094SFrank Li 3648f6d8094SFrank Li static struct clk_onecell_data clk_data; 3658f6d8094SFrank Li 3661b9af68fSLucas Stach static struct clk ** const uart_clks[] __initconst = { 3671b9af68fSLucas Stach &clks[IMX7D_UART1_ROOT_CLK], 3681b9af68fSLucas Stach &clks[IMX7D_UART2_ROOT_CLK], 3691b9af68fSLucas Stach &clks[IMX7D_UART3_ROOT_CLK], 3701b9af68fSLucas Stach &clks[IMX7D_UART4_ROOT_CLK], 3711b9af68fSLucas Stach &clks[IMX7D_UART5_ROOT_CLK], 3721b9af68fSLucas Stach &clks[IMX7D_UART6_ROOT_CLK], 3731b9af68fSLucas Stach &clks[IMX7D_UART7_ROOT_CLK], 3741b9af68fSLucas Stach NULL 3751b9af68fSLucas Stach }; 3761b9af68fSLucas Stach 3778f6d8094SFrank Li static void __init imx7d_clocks_init(struct device_node *ccm_node) 3788f6d8094SFrank Li { 3798f6d8094SFrank Li struct device_node *np; 3808f6d8094SFrank Li void __iomem *base; 3818f6d8094SFrank Li int i; 3828f6d8094SFrank Li 3838f6d8094SFrank Li clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 3848f6d8094SFrank Li clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); 3854aba2755SGary Bisson clks[IMX7D_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); 3868f6d8094SFrank Li 3878f6d8094SFrank Li np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); 3888f6d8094SFrank Li base = of_iomap(np, 0); 3898f6d8094SFrank Li WARN_ON(!base); 3908f6d8094SFrank Li 3918f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3928f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3938f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3948f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3958f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3968f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); 3978f6d8094SFrank Li 3988f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "pll_arm_main_src", base + 0x60, 0x7f); 3998f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_dram_main", "pll_dram_main_src", base + 0x70, 0x7f); 4008f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "pll_sys_main_src", base + 0xb0, 0x1); 4018f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "pll_enet_main_src", base + 0xe0, 0x0); 4028f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "pll_audio_main_src", base + 0xf0, 0x7f); 4038f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "pll_video_main_src", base + 0x130, 0x7f); 4048f6d8094SFrank Li 4058f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); 4068f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); 4078f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); 4088f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); 4098f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); 4108f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); 4118f6d8094SFrank Li 4128f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); 4138f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); 4148f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); 4158f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); 4168f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); 4178f6d8094SFrank Li clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); 4188f6d8094SFrank Li 4198f6d8094SFrank Li clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); 4208f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); 4218f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); 4228f6d8094SFrank Li clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); 4238f6d8094SFrank Li clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); 4248f6d8094SFrank Li 4258f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); 4268f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); 4278f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); 4288f6d8094SFrank Li 4298f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3); 4308f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0); 4318f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1); 4328f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2); 4338f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3); 4348f6d8094SFrank Li 4358f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1); 4368f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2); 4378f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4); 4388f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2); 4398f6d8094SFrank Li 4408f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4); 4418f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5); 4428f6d8094SFrank Li clks[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6); 4438f6d8094SFrank Li clks[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12); 4448f6d8094SFrank Li 4458f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_196M] = imx_clk_fixed_factor("pll_sys_pfd0_196m", "pll_sys_pfd0_392m_clk", 1, 2); 4468f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_166M] = imx_clk_fixed_factor("pll_sys_pfd1_166m", "pll_sys_pfd1_332m_clk", 1, 2); 4478f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_135M] = imx_clk_fixed_factor("pll_sys_pfd2_135m", "pll_sys_pfd2_270m_clk", 1, 2); 4488f6d8094SFrank Li 4498f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26); 4508f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27); 4518f6d8094SFrank Li clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28); 4528f6d8094SFrank Li 4538f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1); 4548f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2); 4558f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4); 4568f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8); 4578f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_100M] = imx_clk_fixed_factor("pll_enet_100m", "pll_enet_main_clk", 1, 10); 4588f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_50M] = imx_clk_fixed_factor("pll_enet_50m", "pll_enet_main_clk", 1, 20); 4598f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_40M] = imx_clk_fixed_factor("pll_enet_40m", "pll_enet_main_clk", 1, 25); 4608f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_25M] = imx_clk_fixed_factor("pll_enet_25m", "pll_enet_main_clk", 1, 40); 4618f6d8094SFrank Li 4628f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12); 4638f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11); 4648f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10); 4658f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9); 4668f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8); 4678f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7); 4688f6d8094SFrank Li clks[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6); 4698f6d8094SFrank Li 4708f6d8094SFrank Li clks[IMX7D_LVDS1_OUT_SEL] = imx_clk_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel)); 4718f6d8094SFrank Li clks[IMX7D_LVDS1_OUT_CLK] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); 4728f6d8094SFrank Li 4738f6d8094SFrank Li np = ccm_node; 4748f6d8094SFrank Li base = of_iomap(np, 0); 4758f6d8094SFrank Li WARN_ON(!base); 4768f6d8094SFrank Li 4778f6d8094SFrank Li clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); 4788f6d8094SFrank Li clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); 4798f6d8094SFrank Li clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel)); 4808f6d8094SFrank Li clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); 4818f6d8094SFrank Li clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); 4828f6d8094SFrank Li clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); 4838f6d8094SFrank Li clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); 4848f6d8094SFrank Li clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); 4858f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); 4868f6d8094SFrank Li clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); 4878f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); 4888f6d8094SFrank Li clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); 4898f6d8094SFrank Li clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); 4908f6d8094SFrank Li clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); 4918f6d8094SFrank Li clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); 4928f6d8094SFrank Li clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); 4938f6d8094SFrank Li clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); 4948f6d8094SFrank Li clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); 4958f6d8094SFrank Li clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); 4968f6d8094SFrank Li clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); 4978f6d8094SFrank Li clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); 4988f6d8094SFrank Li clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); 4998f6d8094SFrank Li clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); 5008f6d8094SFrank Li clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); 5018f6d8094SFrank Li clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); 5028f6d8094SFrank Li clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); 5038f6d8094SFrank Li clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); 5048f6d8094SFrank Li clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); 5058f6d8094SFrank Li clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); 5068f6d8094SFrank Li clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); 5078f6d8094SFrank Li clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); 5088f6d8094SFrank Li clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); 5098f6d8094SFrank Li clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); 5108f6d8094SFrank Li clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); 5118f6d8094SFrank Li clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); 5128f6d8094SFrank Li clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); 5138f6d8094SFrank Li clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); 5148f6d8094SFrank Li clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); 5158f6d8094SFrank Li clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); 5168f6d8094SFrank Li clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); 5178f6d8094SFrank Li clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); 5188f6d8094SFrank Li clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); 5198f6d8094SFrank Li clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); 5208f6d8094SFrank Li clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); 5218f6d8094SFrank Li clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); 5228f6d8094SFrank Li clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); 5238f6d8094SFrank Li clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); 5248f6d8094SFrank Li clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); 5258f6d8094SFrank Li clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); 5268f6d8094SFrank Li clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); 5278f6d8094SFrank Li clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); 5288f6d8094SFrank Li clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); 5298f6d8094SFrank Li clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); 5308f6d8094SFrank Li clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); 5318f6d8094SFrank Li clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); 5328f6d8094SFrank Li clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); 5338f6d8094SFrank Li clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); 5348f6d8094SFrank Li clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); 5358f6d8094SFrank Li clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); 5368f6d8094SFrank Li clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); 5378f6d8094SFrank Li clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); 5388f6d8094SFrank Li clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); 5398f6d8094SFrank Li clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); 5408f6d8094SFrank Li clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); 5418f6d8094SFrank Li clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); 5428f6d8094SFrank Li clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); 5438f6d8094SFrank Li clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); 5448f6d8094SFrank Li clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); 5458f6d8094SFrank Li clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); 5468f6d8094SFrank Li clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); 5478f6d8094SFrank Li clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); 5488f6d8094SFrank Li 5498f6d8094SFrank Li clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); 5508f6d8094SFrank Li clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); 5518f6d8094SFrank Li clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate("arm_m0_cg", "arm_m0_src", base + 0x8100, 28); 5528f6d8094SFrank Li clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate("axi_cg", "axi_src", base + 0x8800, 28); 5538f6d8094SFrank Li clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); 5548f6d8094SFrank Li clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); 5558f6d8094SFrank Li clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); 5568f6d8094SFrank Li clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate("ahb_cg", "ahb_src", base + 0x9000, 28); 5578f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); 5588f6d8094SFrank Li clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate("dram_cg", "dram_src", base + 0x9880, 28); 5598f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); 5608f6d8094SFrank Li clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); 5618f6d8094SFrank Li clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); 5628f6d8094SFrank Li clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); 5638f6d8094SFrank Li clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); 5648f6d8094SFrank Li clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); 5658f6d8094SFrank Li clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); 5668f6d8094SFrank Li clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); 5678f6d8094SFrank Li clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); 5688f6d8094SFrank Li clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); 5698f6d8094SFrank Li clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate("sai1_cg", "sai1_src", base + 0xa500, 28); 5708f6d8094SFrank Li clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate("sai2_cg", "sai2_src", base + 0xa580, 28); 5718f6d8094SFrank Li clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate("sai3_cg", "sai3_src", base + 0xa600, 28); 5728f6d8094SFrank Li clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate("spdif_cg", "spdif_src", base + 0xa680, 28); 5738f6d8094SFrank Li clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); 5748f6d8094SFrank Li clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); 5758f6d8094SFrank Li clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); 5768f6d8094SFrank Li clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); 5778f6d8094SFrank Li clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); 5788f6d8094SFrank Li clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate("eim_cg", "eim_src", base + 0xa980, 28); 5798f6d8094SFrank Li clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate("nand_cg", "nand_src", base + 0xaa00, 28); 5808f6d8094SFrank Li clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate("qspi_cg", "qspi_src", base + 0xaa80, 28); 5818f6d8094SFrank Li clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); 5828f6d8094SFrank Li clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); 5838f6d8094SFrank Li clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); 5848f6d8094SFrank Li clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate("can1_cg", "can1_src", base + 0xac80, 28); 5858f6d8094SFrank Li clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate("can2_cg", "can2_src", base + 0xad00, 28); 5868f6d8094SFrank Li clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate("i2c1_cg", "i2c1_src", base + 0xad80, 28); 5878f6d8094SFrank Li clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate("i2c2_cg", "i2c2_src", base + 0xae00, 28); 5888f6d8094SFrank Li clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate("i2c3_cg", "i2c3_src", base + 0xae80, 28); 5898f6d8094SFrank Li clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate("i2c4_cg", "i2c4_src", base + 0xaf00, 28); 5908f6d8094SFrank Li clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate("uart1_cg", "uart1_src", base + 0xaf80, 28); 5918f6d8094SFrank Li clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate("uart2_cg", "uart2_src", base + 0xb000, 28); 5928f6d8094SFrank Li clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate("uart3_cg", "uart3_src", base + 0xb080, 28); 5938f6d8094SFrank Li clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate("uart4_cg", "uart4_src", base + 0xb100, 28); 5948f6d8094SFrank Li clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate("uart5_cg", "uart5_src", base + 0xb180, 28); 5958f6d8094SFrank Li clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate("uart6_cg", "uart6_src", base + 0xb200, 28); 5968f6d8094SFrank Li clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate("uart7_cg", "uart7_src", base + 0xb280, 28); 5978f6d8094SFrank Li clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); 5988f6d8094SFrank Li clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); 5998f6d8094SFrank Li clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); 6008f6d8094SFrank Li clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); 6018f6d8094SFrank Li clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate("pwm1_cg", "pwm1_src", base + 0xb500, 28); 6028f6d8094SFrank Li clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate("pwm2_cg", "pwm2_src", base + 0xb580, 28); 6038f6d8094SFrank Li clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate("pwm3_cg", "pwm3_src", base + 0xb600, 28); 6048f6d8094SFrank Li clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate("pwm4_cg", "pwm4_src", base + 0xb680, 28); 6058f6d8094SFrank Li clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); 6068f6d8094SFrank Li clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); 6078f6d8094SFrank Li clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate("sim1_cg", "sim1_src", base + 0xb800, 28); 6088f6d8094SFrank Li clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate("sim2_cg", "sim2_src", base + 0xb880, 28); 6098f6d8094SFrank Li clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate("gpt1_cg", "gpt1_src", base + 0xb900, 28); 6108f6d8094SFrank Li clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate("gpt2_cg", "gpt2_src", base + 0xb980, 28); 6118f6d8094SFrank Li clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate("gpt3_cg", "gpt3_src", base + 0xbA00, 28); 6128f6d8094SFrank Li clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate("gpt4_cg", "gpt4_src", base + 0xbA80, 28); 6138f6d8094SFrank Li clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate("trace_cg", "trace_src", base + 0xbb00, 28); 6148f6d8094SFrank Li clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate("wdog_cg", "wdog_src", base + 0xbb80, 28); 6158f6d8094SFrank Li clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); 6168f6d8094SFrank Li clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); 6178f6d8094SFrank Li clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate("wrclk_cg", "wrclk_src", base + 0xbd00, 28); 6188f6d8094SFrank Li clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate("clko1_cg", "clko1_src", base + 0xbd80, 28); 6198f6d8094SFrank Li clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate("clko2_cg", "clko2_src", base + 0xbe00, 28); 6208f6d8094SFrank Li 6218f6d8094SFrank Li clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); 6228f6d8094SFrank Li clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); 6238f6d8094SFrank Li clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); 6248f6d8094SFrank Li clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); 6258f6d8094SFrank Li clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); 6268f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); 6278f6d8094SFrank Li clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); 6288f6d8094SFrank Li clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); 6298f6d8094SFrank Li clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); 6308f6d8094SFrank Li clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); 6318f6d8094SFrank Li clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); 6328f6d8094SFrank Li clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); 6338f6d8094SFrank Li clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); 6348f6d8094SFrank Li clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); 6358f6d8094SFrank Li clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); 6368f6d8094SFrank Li clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); 6378f6d8094SFrank Li clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); 6388f6d8094SFrank Li clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); 6398f6d8094SFrank Li clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); 6408f6d8094SFrank Li clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); 6418f6d8094SFrank Li clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); 6428f6d8094SFrank Li clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); 6438f6d8094SFrank Li clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); 6448f6d8094SFrank Li clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); 6458f6d8094SFrank Li clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); 6468f6d8094SFrank Li clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); 6478f6d8094SFrank Li clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); 6488f6d8094SFrank Li clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); 6498f6d8094SFrank Li clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); 6508f6d8094SFrank Li clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); 6518f6d8094SFrank Li clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); 6528f6d8094SFrank Li clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); 6538f6d8094SFrank Li clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); 6548f6d8094SFrank Li clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); 6558f6d8094SFrank Li clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); 6568f6d8094SFrank Li clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); 6578f6d8094SFrank Li clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); 6588f6d8094SFrank Li clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); 6598f6d8094SFrank Li clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); 6608f6d8094SFrank Li clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); 6618f6d8094SFrank Li clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); 6628f6d8094SFrank Li clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); 6638f6d8094SFrank Li clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); 6648f6d8094SFrank Li clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); 6658f6d8094SFrank Li clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); 6668f6d8094SFrank Li clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); 6678f6d8094SFrank Li clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); 6688f6d8094SFrank Li clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); 6698f6d8094SFrank Li clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); 6708f6d8094SFrank Li clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); 6718f6d8094SFrank Li clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); 6728f6d8094SFrank Li clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); 6738f6d8094SFrank Li clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); 6748f6d8094SFrank Li clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); 6758f6d8094SFrank Li clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); 6768f6d8094SFrank Li clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); 6778f6d8094SFrank Li clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); 6788f6d8094SFrank Li clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); 6798f6d8094SFrank Li clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); 6808f6d8094SFrank Li clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); 6818f6d8094SFrank Li clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); 6828f6d8094SFrank Li clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); 6838f6d8094SFrank Li clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); 6848f6d8094SFrank Li clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); 6858f6d8094SFrank Li clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); 6868f6d8094SFrank Li clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); 6878f6d8094SFrank Li 6888f6d8094SFrank Li clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); 6898f6d8094SFrank Li clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); 6908f6d8094SFrank Li clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3); 6918f6d8094SFrank Li clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); 6928f6d8094SFrank Li clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); 6938f6d8094SFrank Li clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); 6948f6d8094SFrank Li clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); 6958f6d8094SFrank Li clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); 6968f6d8094SFrank Li clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider("dram_post_div", "dram_cg", base + 0x9880, 0, 3); 6978f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); 6988f6d8094SFrank Li clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); 6998f6d8094SFrank Li clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); 7008f6d8094SFrank Li clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); 7018f6d8094SFrank Li clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); 7028f6d8094SFrank Li clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); 7038f6d8094SFrank Li clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); 7048f6d8094SFrank Li clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); 7058f6d8094SFrank Li clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); 7068f6d8094SFrank Li clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); 7078f6d8094SFrank Li clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); 7088f6d8094SFrank Li clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); 7098f6d8094SFrank Li clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); 7108f6d8094SFrank Li clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); 7118f6d8094SFrank Li clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); 7128f6d8094SFrank Li clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); 7138f6d8094SFrank Li clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); 7148f6d8094SFrank Li clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); 7158f6d8094SFrank Li clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); 7168f6d8094SFrank Li clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); 7178f6d8094SFrank Li clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); 7188f6d8094SFrank Li clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); 7198f6d8094SFrank Li clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); 7208f6d8094SFrank Li clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); 7218f6d8094SFrank Li clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); 7228f6d8094SFrank Li clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); 7238f6d8094SFrank Li clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); 7248f6d8094SFrank Li clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); 7258f6d8094SFrank Li clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); 7268f6d8094SFrank Li clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); 7278f6d8094SFrank Li clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); 7288f6d8094SFrank Li clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); 7298f6d8094SFrank Li clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); 7308f6d8094SFrank Li clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); 7318f6d8094SFrank Li clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); 7328f6d8094SFrank Li clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); 7338f6d8094SFrank Li clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); 7348f6d8094SFrank Li clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); 7358f6d8094SFrank Li clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); 7368f6d8094SFrank Li clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); 7378f6d8094SFrank Li clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); 7388f6d8094SFrank Li clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); 7398f6d8094SFrank Li clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); 7408f6d8094SFrank Li clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); 7418f6d8094SFrank Li clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); 7428f6d8094SFrank Li clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); 7438f6d8094SFrank Li clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); 7448f6d8094SFrank Li clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); 7458f6d8094SFrank Li clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); 7468f6d8094SFrank Li clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); 7478f6d8094SFrank Li clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); 7488f6d8094SFrank Li clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); 7498f6d8094SFrank Li clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); 7508f6d8094SFrank Li clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); 7518f6d8094SFrank Li clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); 7528f6d8094SFrank Li clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); 7538f6d8094SFrank Li clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); 7548f6d8094SFrank Li clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); 7558f6d8094SFrank Li clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); 7568f6d8094SFrank Li clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); 7578f6d8094SFrank Li clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); 7588f6d8094SFrank Li 7598f6d8094SFrank Li clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); 7608f6d8094SFrank Li clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate2("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); 7618f6d8094SFrank Li clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate2("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0); 7628f6d8094SFrank Li clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); 7638f6d8094SFrank Li clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate2("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); 7648f6d8094SFrank Li clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate2("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); 7658f6d8094SFrank Li clks[IMX7D_OCRAM_CLK] = imx_clk_gate2("ocram_clk", "axi_post_div", base + 0x4110, 0); 7668f6d8094SFrank Li clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate2("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); 7678f6d8094SFrank Li clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate2("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); 7688f6d8094SFrank Li clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate2("ahb_root_clk", "ahb_post_div", base + 0x4200, 0); 7698f6d8094SFrank Li clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2("dram_root_clk", "dram_post_div", base + 0x4130, 0); 7708f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); 7718f6d8094SFrank Li clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); 7728f6d8094SFrank Li clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); 7738f6d8094SFrank Li clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate2("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); 7748f6d8094SFrank Li clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate2("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); 7758f6d8094SFrank Li clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate2("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); 7768f6d8094SFrank Li clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate2("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); 7778f6d8094SFrank Li clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate2("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); 7788f6d8094SFrank Li clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate2("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); 7798f6d8094SFrank Li clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate2("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); 7808f6d8094SFrank Li clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate2("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); 7818f6d8094SFrank Li clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0); 7828f6d8094SFrank Li clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0); 7838f6d8094SFrank Li clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0); 7848f6d8094SFrank Li clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate2("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); 7858f6d8094SFrank Li clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate2("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0); 7868f6d8094SFrank Li clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0); 7878f6d8094SFrank Li clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate2("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0); 7888f6d8094SFrank Li clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); 7898f6d8094SFrank Li clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate2("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); 7908f6d8094SFrank Li clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate2("eim_root_clk", "eim_post_div", base + 0x4160, 0); 7918f6d8094SFrank Li clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2("nand_root_clk", "nand_post_div", base + 0x4140, 0); 7928f6d8094SFrank Li clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate2("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); 7938f6d8094SFrank Li clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate2("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); 7948f6d8094SFrank Li clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate2("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); 7958f6d8094SFrank Li clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate2("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); 7968f6d8094SFrank Li clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate2("can1_root_clk", "can1_post_div", base + 0x4740, 0); 7978f6d8094SFrank Li clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate2("can2_root_clk", "can2_post_div", base + 0x4750, 0); 7988f6d8094SFrank Li clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate2("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); 7998f6d8094SFrank Li clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate2("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); 8008f6d8094SFrank Li clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate2("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); 8018f6d8094SFrank Li clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate2("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); 8028f6d8094SFrank Li clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate2("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); 8038f6d8094SFrank Li clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate2("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); 8048f6d8094SFrank Li clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate2("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); 8058f6d8094SFrank Li clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate2("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); 8068f6d8094SFrank Li clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate2("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); 8078f6d8094SFrank Li clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate2("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); 8088f6d8094SFrank Li clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate2("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); 8098f6d8094SFrank Li clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate2("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); 8108f6d8094SFrank Li clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate2("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); 8118f6d8094SFrank Li clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate2("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); 8128f6d8094SFrank Li clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate2("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); 8138f6d8094SFrank Li clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate2("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); 8148f6d8094SFrank Li clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate2("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); 8158f6d8094SFrank Li clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate2("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); 8168f6d8094SFrank Li clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate2("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); 8178f6d8094SFrank Li clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate2("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); 8188f6d8094SFrank Li clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate2("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); 8198f6d8094SFrank Li clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate2("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); 8208f6d8094SFrank Li clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate2("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); 8218f6d8094SFrank Li clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate2("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); 8228f6d8094SFrank Li clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate2("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); 8238f6d8094SFrank Li clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate2("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); 8248f6d8094SFrank Li clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate2("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); 8258f6d8094SFrank Li clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate2("trace_root_clk", "trace_post_div", base + 0x4300, 0); 8268f6d8094SFrank Li clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate2("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); 8278f6d8094SFrank Li clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate2("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); 8288f6d8094SFrank Li clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate2("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); 8298f6d8094SFrank Li clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate2("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); 8308f6d8094SFrank Li clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); 8318f6d8094SFrank Li clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); 8328f6d8094SFrank Li clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); 833ab4c6a24SHaibo Chen clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); 8348f6d8094SFrank Li 8358f6d8094SFrank Li clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 8368f6d8094SFrank Li 837fdb868cdSBai Ping clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk", 838fdb868cdSBai Ping clks[IMX7D_ARM_A7_ROOT_CLK], 839fdb868cdSBai Ping clks[IMX7D_ARM_A7_ROOT_SRC], 840fdb868cdSBai Ping clks[IMX7D_PLL_ARM_MAIN_CLK], 841fdb868cdSBai Ping clks[IMX7D_PLL_SYS_MAIN_CLK]); 842fdb868cdSBai Ping 84331cbb57dSBai Ping imx_check_clocks(clks, ARRAY_SIZE(clks)); 8448f6d8094SFrank Li 8458f6d8094SFrank Li clk_data.clks = clks; 8468f6d8094SFrank Li clk_data.clk_num = ARRAY_SIZE(clks); 8478f6d8094SFrank Li of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 8488f6d8094SFrank Li 8498f6d8094SFrank Li /* TO BE FIXED LATER 8508f6d8094SFrank Li * Enable all clock to bring up imx7, otherwise system will be halt and block 8518f6d8094SFrank Li * the other part upstream Because imx7d clock design changed, clock framework 8528f6d8094SFrank Li * need do a little modify. 8538f6d8094SFrank Li * Dong Aisheng is working on this. After that, this part need be changed. 8548f6d8094SFrank Li */ 8558f6d8094SFrank Li for (i = 0; i < IMX7D_CLK_END; i++) 8568f6d8094SFrank Li clk_prepare_enable(clks[i]); 8578f6d8094SFrank Li 8588f6d8094SFrank Li /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ 8598f6d8094SFrank Li clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 8608f6d8094SFrank Li 8618f6d8094SFrank Li /* 8628f6d8094SFrank Li * init enet clock source: 8638f6d8094SFrank Li * AXI clock source is 250MHz 8648f6d8094SFrank Li * Phy refrence clock is 25MHz 8658f6d8094SFrank Li * 1588 time clock source is 100MHz 8668f6d8094SFrank Li */ 8678f6d8094SFrank Li clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); 8688f6d8094SFrank Li clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]); 8698f6d8094SFrank Li clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); 8708f6d8094SFrank Li clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); 8718f6d8094SFrank Li 8728f6d8094SFrank Li /* set uart module clock's parent clock source that must be great then 80MHz */ 8738f6d8094SFrank Li clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); 8748f6d8094SFrank Li 8751b9af68fSLucas Stach imx_register_uart_clocks(uart_clks); 8761b9af68fSLucas Stach 8778f6d8094SFrank Li } 8788f6d8094SFrank Li CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); 879