1 /* 2 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 #include <linux/mm.h> 10 #include <linux/delay.h> 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/clkdev.h> 14 #include <linux/of.h> 15 #include <linux/err.h> 16 #include <soc/imx/revision.h> 17 #include <soc/imx/timer.h> 18 #include <asm/irq.h> 19 20 #include "clk.h" 21 22 #define MX35_CCM_BASE_ADDR 0x53f80000 23 #define MX35_GPT1_BASE_ADDR 0x53f90000 24 #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) 25 26 #define MXC_CCM_PDR0 0x04 27 #define MX35_CCM_PDR2 0x0c 28 #define MX35_CCM_PDR3 0x10 29 #define MX35_CCM_PDR4 0x14 30 #define MX35_CCM_MPCTL 0x1c 31 #define MX35_CCM_PPCTL 0x20 32 #define MX35_CCM_CGR0 0x2c 33 #define MX35_CCM_CGR1 0x30 34 #define MX35_CCM_CGR2 0x34 35 #define MX35_CCM_CGR3 0x38 36 37 struct arm_ahb_div { 38 unsigned char arm, ahb, sel; 39 }; 40 41 static struct arm_ahb_div clk_consumer[] = { 42 { .arm = 1, .ahb = 4, .sel = 0}, 43 { .arm = 1, .ahb = 3, .sel = 1}, 44 { .arm = 2, .ahb = 2, .sel = 0}, 45 { .arm = 0, .ahb = 0, .sel = 0}, 46 { .arm = 0, .ahb = 0, .sel = 0}, 47 { .arm = 0, .ahb = 0, .sel = 0}, 48 { .arm = 4, .ahb = 1, .sel = 0}, 49 { .arm = 1, .ahb = 5, .sel = 0}, 50 { .arm = 1, .ahb = 8, .sel = 0}, 51 { .arm = 1, .ahb = 6, .sel = 1}, 52 { .arm = 2, .ahb = 4, .sel = 0}, 53 { .arm = 0, .ahb = 0, .sel = 0}, 54 { .arm = 0, .ahb = 0, .sel = 0}, 55 { .arm = 0, .ahb = 0, .sel = 0}, 56 { .arm = 4, .ahb = 2, .sel = 0}, 57 { .arm = 0, .ahb = 0, .sel = 0}, 58 }; 59 60 static char hsp_div_532[] = { 4, 8, 3, 0 }; 61 static char hsp_div_400[] = { 3, 6, 3, 0 }; 62 63 static struct clk_onecell_data clk_data; 64 65 static const char *std_sel[] = {"ppll", "arm"}; 66 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 67 68 enum mx35_clks { 69 ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, 70 arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, 71 esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, 72 spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, 73 ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, 74 audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, 75 edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, 76 esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, 77 gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, 78 kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, 79 rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, 80 ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, 81 wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, 82 gpu2d_gate, clk_max 83 }; 84 85 static struct clk *clk[clk_max]; 86 87 static struct clk ** const uart_clks[] __initconst = { 88 &clk[ipg], 89 &clk[uart1_gate], 90 &clk[uart2_gate], 91 &clk[uart3_gate], 92 NULL 93 }; 94 95 static void __init _mx35_clocks_init(void) 96 { 97 void __iomem *base; 98 u32 pdr0, consumer_sel, hsp_sel; 99 struct arm_ahb_div *aad; 100 unsigned char *hsp_div; 101 102 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); 103 BUG_ON(!base); 104 105 pdr0 = __raw_readl(base + MXC_CCM_PDR0); 106 consumer_sel = (pdr0 >> 16) & 0xf; 107 aad = &clk_consumer[consumer_sel]; 108 if (!aad->arm) { 109 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); 110 /* 111 * We are basically stuck. Continue with a default entry and hope we 112 * get far enough to actually show the above message 113 */ 114 aad = &clk_consumer[0]; 115 } 116 117 clk[ckih] = imx_clk_fixed("ckih", 24000000); 118 clk[ckil] = imx_clk_fixed("ckih", 32768); 119 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); 120 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); 121 122 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); 123 124 if (aad->sel) 125 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); 126 else 127 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); 128 129 if (clk_get_rate(clk[arm]) > 400000000) 130 hsp_div = hsp_div_532; 131 else 132 hsp_div = hsp_div_400; 133 134 hsp_sel = (pdr0 >> 20) & 0x3; 135 if (!hsp_div[hsp_sel]) { 136 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); 137 hsp_sel = 0; 138 } 139 140 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); 141 142 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); 143 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); 144 145 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); 146 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); 147 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); 148 149 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); 150 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); 151 152 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); 153 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); 154 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); 155 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); 156 157 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); 158 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 159 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); 160 161 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); 162 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); 163 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); 164 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); 165 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); 166 167 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); 168 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); 169 170 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); 171 172 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); 173 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); 174 175 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); 176 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); 177 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); 178 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); 179 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); 180 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); 181 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); 182 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); 183 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); 184 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); 185 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); 186 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); 187 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); 188 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); 189 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); 190 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); 191 192 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); 193 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); 194 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); 195 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); 196 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); 197 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); 198 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); 199 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); 200 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); 201 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); 202 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); 203 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); 204 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); 205 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); 206 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); 207 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); 208 209 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); 210 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); 211 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); 212 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); 213 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); 214 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); 215 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); 216 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); 217 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); 218 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); 219 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); 220 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); 221 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); 222 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); 223 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); 224 225 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); 226 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); 227 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); 228 229 imx_check_clocks(clk, ARRAY_SIZE(clk)); 230 231 clk_prepare_enable(clk[spba_gate]); 232 clk_prepare_enable(clk[gpio1_gate]); 233 clk_prepare_enable(clk[gpio2_gate]); 234 clk_prepare_enable(clk[gpio3_gate]); 235 clk_prepare_enable(clk[iim_gate]); 236 clk_prepare_enable(clk[emi_gate]); 237 clk_prepare_enable(clk[max_gate]); 238 clk_prepare_enable(clk[iomuxc_gate]); 239 240 /* 241 * SCC is needed to boot via mmc after a watchdog reset. The clock code 242 * before conversion to common clk also enabled UART1 (which isn't 243 * handled here and not needed for mmc) and IIM (which is enabled 244 * unconditionally above). 245 */ 246 clk_prepare_enable(clk[scc_gate]); 247 248 imx_register_uart_clocks(uart_clks); 249 250 imx_print_silicon_rev("i.MX35", mx35_revision()); 251 } 252 253 int __init mx35_clocks_init(void) 254 { 255 _mx35_clocks_init(); 256 257 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); 258 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); 259 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); 260 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); 261 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); 262 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); 263 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); 264 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); 265 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); 266 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); 267 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); 268 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); 269 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); 270 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); 271 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); 272 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); 273 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); 274 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); 275 /* i.mx35 has the i.mx27 type fec */ 276 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); 277 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); 278 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 279 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); 280 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); 281 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 282 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); 283 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); 284 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); 285 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); 286 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 287 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); 288 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); 289 /* i.mx35 has the i.mx21 type uart */ 290 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); 291 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); 292 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); 293 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); 294 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); 295 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); 296 /* i.mx35 has the i.mx21 type rtc */ 297 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); 298 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); 299 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); 300 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); 301 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); 302 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); 303 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); 304 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); 305 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); 306 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); 307 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); 308 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); 309 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); 310 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); 311 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 312 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); 313 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 314 clk_register_clkdev(clk[admux_gate], "audmux", NULL); 315 316 mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31); 317 318 return 0; 319 } 320 321 static void __init mx35_clocks_init_dt(struct device_node *ccm_node) 322 { 323 _mx35_clocks_init(); 324 325 clk_data.clks = clk; 326 clk_data.clk_num = ARRAY_SIZE(clk); 327 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data); 328 } 329 CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt); 330