1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 4 */ 5 #include <linux/mm.h> 6 #include <linux/delay.h> 7 #include <linux/clk.h> 8 #include <linux/io.h> 9 #include <linux/clkdev.h> 10 #include <linux/of.h> 11 #include <linux/err.h> 12 #include <soc/imx/revision.h> 13 #include <soc/imx/timer.h> 14 #include <asm/irq.h> 15 16 #include "clk.h" 17 18 #define MX35_CCM_BASE_ADDR 0x53f80000 19 #define MX35_GPT1_BASE_ADDR 0x53f90000 20 #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) 21 22 #define MXC_CCM_PDR0 0x04 23 #define MX35_CCM_PDR2 0x0c 24 #define MX35_CCM_PDR3 0x10 25 #define MX35_CCM_PDR4 0x14 26 #define MX35_CCM_MPCTL 0x1c 27 #define MX35_CCM_PPCTL 0x20 28 #define MX35_CCM_CGR0 0x2c 29 #define MX35_CCM_CGR1 0x30 30 #define MX35_CCM_CGR2 0x34 31 #define MX35_CCM_CGR3 0x38 32 33 struct arm_ahb_div { 34 unsigned char arm, ahb, sel; 35 }; 36 37 static struct arm_ahb_div clk_consumer[] = { 38 { .arm = 1, .ahb = 4, .sel = 0}, 39 { .arm = 1, .ahb = 3, .sel = 1}, 40 { .arm = 2, .ahb = 2, .sel = 0}, 41 { .arm = 0, .ahb = 0, .sel = 0}, 42 { .arm = 0, .ahb = 0, .sel = 0}, 43 { .arm = 0, .ahb = 0, .sel = 0}, 44 { .arm = 4, .ahb = 1, .sel = 0}, 45 { .arm = 1, .ahb = 5, .sel = 0}, 46 { .arm = 1, .ahb = 8, .sel = 0}, 47 { .arm = 1, .ahb = 6, .sel = 1}, 48 { .arm = 2, .ahb = 4, .sel = 0}, 49 { .arm = 0, .ahb = 0, .sel = 0}, 50 { .arm = 0, .ahb = 0, .sel = 0}, 51 { .arm = 0, .ahb = 0, .sel = 0}, 52 { .arm = 4, .ahb = 2, .sel = 0}, 53 { .arm = 0, .ahb = 0, .sel = 0}, 54 }; 55 56 static char hsp_div_532[] = { 4, 8, 3, 0 }; 57 static char hsp_div_400[] = { 3, 6, 3, 0 }; 58 59 static struct clk_onecell_data clk_data; 60 61 static const char *std_sel[] = {"ppll", "arm"}; 62 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 63 64 enum mx35_clks { 65 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, 66 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, 67 /* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, 68 /* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre, 69 /* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div, 70 /* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate, 71 /* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate, 72 /* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, 73 /* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, 74 /* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, 75 /* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate, 76 /* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate, 77 /* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate, 78 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate, 79 /* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, 80 /* 81 */ gpu2d_gate, ckil, clk_max 81 }; 82 83 static struct clk *clk[clk_max]; 84 85 static void __init _mx35_clocks_init(void) 86 { 87 void __iomem *base; 88 u32 pdr0, consumer_sel, hsp_sel; 89 struct arm_ahb_div *aad; 90 unsigned char *hsp_div; 91 92 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); 93 BUG_ON(!base); 94 95 pdr0 = __raw_readl(base + MXC_CCM_PDR0); 96 consumer_sel = (pdr0 >> 16) & 0xf; 97 aad = &clk_consumer[consumer_sel]; 98 if (!aad->arm) { 99 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); 100 /* 101 * We are basically stuck. Continue with a default entry and hope we 102 * get far enough to actually show the above message 103 */ 104 aad = &clk_consumer[0]; 105 } 106 107 clk[ckih] = imx_clk_fixed("ckih", 24000000); 108 clk[ckil] = imx_clk_fixed("ckil", 32768); 109 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); 110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); 111 112 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); 113 114 if (aad->sel) 115 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); 116 else 117 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); 118 119 if (clk_get_rate(clk[arm]) > 400000000) 120 hsp_div = hsp_div_532; 121 else 122 hsp_div = hsp_div_400; 123 124 hsp_sel = (pdr0 >> 20) & 0x3; 125 if (!hsp_div[hsp_sel]) { 126 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); 127 hsp_sel = 0; 128 } 129 130 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); 131 132 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); 133 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); 134 135 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); 136 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); 137 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); 138 139 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); 140 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); 141 142 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); 143 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); 144 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); 145 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); 146 147 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); 148 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 149 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); 150 151 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); 152 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); 153 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); 154 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); 155 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); 156 157 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); 158 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); 159 160 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); 161 162 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); 163 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); 164 165 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); 166 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); 167 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); 168 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); 169 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); 170 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); 171 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); 172 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); 173 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); 174 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); 175 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); 176 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); 177 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); 178 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); 179 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); 180 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); 181 182 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); 183 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); 184 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); 185 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); 186 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); 187 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); 188 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); 189 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); 190 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); 191 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); 192 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); 193 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); 194 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); 195 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); 196 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); 197 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); 198 199 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); 200 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); 201 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); 202 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); 203 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); 204 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); 205 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); 206 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); 207 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); 208 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); 209 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); 210 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); 211 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); 212 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); 213 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); 214 215 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); 216 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); 217 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); 218 219 imx_check_clocks(clk, ARRAY_SIZE(clk)); 220 221 clk_prepare_enable(clk[spba_gate]); 222 clk_prepare_enable(clk[gpio1_gate]); 223 clk_prepare_enable(clk[gpio2_gate]); 224 clk_prepare_enable(clk[gpio3_gate]); 225 clk_prepare_enable(clk[iim_gate]); 226 clk_prepare_enable(clk[emi_gate]); 227 clk_prepare_enable(clk[max_gate]); 228 clk_prepare_enable(clk[iomuxc_gate]); 229 230 /* 231 * SCC is needed to boot via mmc after a watchdog reset. The clock code 232 * before conversion to common clk also enabled UART1 (which isn't 233 * handled here and not needed for mmc) and IIM (which is enabled 234 * unconditionally above). 235 */ 236 clk_prepare_enable(clk[scc_gate]); 237 238 imx_register_uart_clocks(4); 239 240 imx_print_silicon_rev("i.MX35", mx35_revision()); 241 } 242 243 static void __init mx35_clocks_init_dt(struct device_node *ccm_node) 244 { 245 _mx35_clocks_init(); 246 247 clk_data.clks = clk; 248 clk_data.clk_num = ARRAY_SIZE(clk); 249 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data); 250 } 251 CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt); 252