1 /* 2 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/clk.h> 20 #include <linux/clkdev.h> 21 #include <linux/io.h> 22 #include <linux/err.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 #include <soc/imx/revision.h> 26 #include <soc/imx/timer.h> 27 #include <asm/irq.h> 28 29 #include "clk.h" 30 31 #define MX31_CCM_BASE_ADDR 0x53f80000 32 #define MX31_GPT1_BASE_ADDR 0x53f90000 33 #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) 34 35 #define MXC_CCM_CCMR 0x00 36 #define MXC_CCM_PDR0 0x04 37 #define MXC_CCM_PDR1 0x08 38 #define MXC_CCM_MPCTL 0x10 39 #define MXC_CCM_UPCTL 0x14 40 #define MXC_CCM_SRPCTL 0x18 41 #define MXC_CCM_CGR0 0x20 42 #define MXC_CCM_CGR1 0x24 43 #define MXC_CCM_CGR2 0x28 44 #define MXC_CCM_PMCR0 0x5c 45 46 static const char *mcu_main_sel[] = { "spll", "mpll", }; 47 static const char *per_sel[] = { "per_div", "ipg", }; 48 static const char *csi_sel[] = { "upll", "spll", }; 49 static const char *fir_sel[] = { "mcu_main", "upll", "spll" }; 50 51 enum mx31_clks { 52 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, 53 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, 54 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, 55 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, 56 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, 57 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate, 58 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, 59 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate, 60 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max 61 }; 62 63 static struct clk *clk[clk_max]; 64 static struct clk_onecell_data clk_data; 65 66 static struct clk ** const uart_clks[] __initconst = { 67 &clk[ipg], 68 &clk[uart1_gate], 69 &clk[uart2_gate], 70 &clk[uart3_gate], 71 &clk[uart4_gate], 72 &clk[uart5_gate], 73 NULL 74 }; 75 76 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) 77 { 78 clk[dummy] = imx_clk_fixed("dummy", 0); 79 clk[ckih] = imx_clk_fixed("ckih", fref); 80 clk[ckil] = imx_clk_fixed("ckil", 32768); 81 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); 82 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); 83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); 84 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); 85 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); 86 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); 87 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); 88 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); 89 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); 90 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); 91 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); 92 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); 93 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); 94 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); 95 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); 96 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); 97 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); 98 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); 99 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); 100 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); 101 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); 102 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); 103 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); 104 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); 105 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); 106 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); 107 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); 108 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); 109 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); 110 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); 111 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); 112 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); 113 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); 114 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); 115 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); 116 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); 117 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); 118 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); 119 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); 120 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); 121 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); 122 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); 123 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); 124 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); 125 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); 126 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); 127 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); 128 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); 129 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); 130 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); 131 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); 132 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); 133 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); 134 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); 135 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); 136 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); 137 138 imx_check_clocks(clk, ARRAY_SIZE(clk)); 139 140 clk_set_parent(clk[csi], clk[upll]); 141 clk_prepare_enable(clk[emi_gate]); 142 clk_prepare_enable(clk[iim_gate]); 143 mx31_revision(); 144 clk_disable_unprepare(clk[iim_gate]); 145 } 146 147 int __init mx31_clocks_init(unsigned long fref) 148 { 149 void __iomem *base; 150 151 base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); 152 if (!base) 153 panic("%s: failed to map registers\n", __func__); 154 155 _mx31_clocks_init(base, fref); 156 157 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); 158 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 159 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); 160 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); 161 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); 162 clk_register_clkdev(clk[pwm_gate], "pwm", NULL); 163 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 164 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); 165 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); 166 clk_register_clkdev(clk[epit1_gate], "epit", NULL); 167 clk_register_clkdev(clk[epit2_gate], "epit", NULL); 168 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); 169 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); 170 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); 171 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); 172 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); 173 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); 174 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); 175 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); 176 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); 177 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); 178 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); 179 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); 180 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); 181 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); 182 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); 183 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); 184 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 185 /* i.mx31 has the i.mx21 type uart */ 186 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); 187 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); 188 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); 189 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); 190 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); 191 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); 192 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); 193 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); 194 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); 195 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); 196 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); 197 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); 198 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 199 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); 200 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); 201 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); 202 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); 203 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); 204 clk_register_clkdev(clk[firi_gate], "firi", NULL); 205 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); 206 clk_register_clkdev(clk[rtic_gate], "rtic", NULL); 207 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); 208 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); 209 clk_register_clkdev(clk[iim_gate], "iim", NULL); 210 211 212 imx_register_uart_clocks(uart_clks); 213 mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); 214 215 return 0; 216 } 217 218 static void __init mx31_clocks_init_dt(struct device_node *np) 219 { 220 struct device_node *osc_np; 221 u32 fref = 26000000; /* default */ 222 void __iomem *ccm; 223 224 for_each_compatible_node(osc_np, NULL, "fixed-clock") { 225 if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m")) 226 continue; 227 228 if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) { 229 of_node_put(osc_np); 230 break; 231 } 232 } 233 234 ccm = of_iomap(np, 0); 235 if (!ccm) 236 panic("%s: failed to map registers\n", __func__); 237 238 _mx31_clocks_init(ccm, fref); 239 240 clk_data.clks = clk; 241 clk_data.clk_num = ARRAY_SIZE(clk); 242 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 243 } 244 245 CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt); 246