1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 5 * 6 * Gated clock implementation 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/module.h> 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/string.h> 15 #include "clk.h" 16 17 /** 18 * DOC: basic gatable clock which can gate and ungate it's ouput 19 * 20 * Traits of this clock: 21 * prepare - clk_(un)prepare only ensures parent is (un)prepared 22 * enable - clk_enable and clk_disable are functional & control gating 23 * rate - inherits rate from parent. No clk_set_rate support 24 * parent - fixed parent. No clk_set_parent support 25 */ 26 27 struct clk_gate2 { 28 struct clk_hw hw; 29 void __iomem *reg; 30 u8 bit_idx; 31 u8 cgr_val; 32 u8 flags; 33 spinlock_t *lock; 34 unsigned int *share_count; 35 }; 36 37 #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) 38 39 static int clk_gate2_enable(struct clk_hw *hw) 40 { 41 struct clk_gate2 *gate = to_clk_gate2(hw); 42 u32 reg; 43 unsigned long flags; 44 45 spin_lock_irqsave(gate->lock, flags); 46 47 if (gate->share_count && (*gate->share_count)++ > 0) 48 goto out; 49 50 reg = readl(gate->reg); 51 reg &= ~(3 << gate->bit_idx); 52 reg |= gate->cgr_val << gate->bit_idx; 53 writel(reg, gate->reg); 54 55 out: 56 spin_unlock_irqrestore(gate->lock, flags); 57 58 return 0; 59 } 60 61 static void clk_gate2_disable(struct clk_hw *hw) 62 { 63 struct clk_gate2 *gate = to_clk_gate2(hw); 64 u32 reg; 65 unsigned long flags; 66 67 spin_lock_irqsave(gate->lock, flags); 68 69 if (gate->share_count) { 70 if (WARN_ON(*gate->share_count == 0)) 71 goto out; 72 else if (--(*gate->share_count) > 0) 73 goto out; 74 } 75 76 reg = readl(gate->reg); 77 reg &= ~(3 << gate->bit_idx); 78 writel(reg, gate->reg); 79 80 out: 81 spin_unlock_irqrestore(gate->lock, flags); 82 } 83 84 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) 85 { 86 u32 val = readl(reg); 87 88 if (((val >> bit_idx) & 1) == 1) 89 return 1; 90 91 return 0; 92 } 93 94 static int clk_gate2_is_enabled(struct clk_hw *hw) 95 { 96 struct clk_gate2 *gate = to_clk_gate2(hw); 97 98 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); 99 } 100 101 static void clk_gate2_disable_unused(struct clk_hw *hw) 102 { 103 struct clk_gate2 *gate = to_clk_gate2(hw); 104 unsigned long flags; 105 u32 reg; 106 107 spin_lock_irqsave(gate->lock, flags); 108 109 if (!gate->share_count || *gate->share_count == 0) { 110 reg = readl(gate->reg); 111 reg &= ~(3 << gate->bit_idx); 112 writel(reg, gate->reg); 113 } 114 115 spin_unlock_irqrestore(gate->lock, flags); 116 } 117 118 static const struct clk_ops clk_gate2_ops = { 119 .enable = clk_gate2_enable, 120 .disable = clk_gate2_disable, 121 .disable_unused = clk_gate2_disable_unused, 122 .is_enabled = clk_gate2_is_enabled, 123 }; 124 125 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, 126 const char *parent_name, unsigned long flags, 127 void __iomem *reg, u8 bit_idx, u8 cgr_val, 128 u8 clk_gate2_flags, spinlock_t *lock, 129 unsigned int *share_count) 130 { 131 struct clk_gate2 *gate; 132 struct clk_hw *hw; 133 struct clk_init_data init; 134 int ret; 135 136 gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); 137 if (!gate) 138 return ERR_PTR(-ENOMEM); 139 140 /* struct clk_gate2 assignments */ 141 gate->reg = reg; 142 gate->bit_idx = bit_idx; 143 gate->cgr_val = cgr_val; 144 gate->flags = clk_gate2_flags; 145 gate->lock = lock; 146 gate->share_count = share_count; 147 148 init.name = name; 149 init.ops = &clk_gate2_ops; 150 init.flags = flags; 151 init.parent_names = parent_name ? &parent_name : NULL; 152 init.num_parents = parent_name ? 1 : 0; 153 154 gate->hw.init = &init; 155 hw = &gate->hw; 156 157 ret = clk_hw_register(dev, hw); 158 if (ret) { 159 kfree(gate); 160 return ERR_PTR(ret); 161 } 162 163 return hw; 164 } 165