1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright 2021 NXP
4  */
5 
6 #include <linux/bitfield.h>
7 #include <linux/clk-provider.h>
8 #include <linux/err.h>
9 #include <linux/export.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/slab.h>
13 #include <asm/div64.h>
14 
15 #include "clk.h"
16 
17 #define PLL_CTRL		0x0
18 #define HW_CTRL_SEL		BIT(16)
19 #define CLKMUX_BYPASS		BIT(2)
20 #define CLKMUX_EN		BIT(1)
21 #define POWERUP_MASK		BIT(0)
22 
23 #define PLL_ANA_PRG		0x10
24 #define PLL_SPREAD_SPECTRUM	0x30
25 
26 #define PLL_NUMERATOR		0x40
27 #define PLL_MFN_MASK		GENMASK(31, 2)
28 
29 #define PLL_DENOMINATOR		0x50
30 #define PLL_MFD_MASK		GENMASK(29, 0)
31 
32 #define PLL_DIV			0x60
33 #define PLL_MFI_MASK		GENMASK(24, 16)
34 #define PLL_RDIV_MASK		GENMASK(15, 13)
35 #define PLL_ODIV_MASK		GENMASK(7, 0)
36 
37 #define PLL_DFS_CTRL(x)		(0x70 + (x) * 0x10)
38 
39 #define PLL_STATUS		0xF0
40 #define LOCK_STATUS		BIT(0)
41 
42 #define DFS_STATUS		0xF4
43 
44 #define LOCK_TIMEOUT_US		200
45 
46 #define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv)	\
47 	{							\
48 		.rate	=	(_rate),			\
49 		.mfi	=	(_mfi),				\
50 		.mfn	=	(_mfn),				\
51 		.mfd	=	(_mfd),				\
52 		.rdiv	=	(_rdiv),			\
53 		.odiv	=	(_odiv),			\
54 	}
55 
56 #define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv)		\
57 	{							\
58 		.rate	=	(_rate),			\
59 		.mfi	=	(_mfi),				\
60 		.mfn	=	0,				\
61 		.mfd	=	0,				\
62 		.rdiv	=	(_rdiv),			\
63 		.odiv	=	(_odiv),			\
64 	}
65 
66 struct clk_fracn_gppll {
67 	struct clk_hw			hw;
68 	void __iomem			*base;
69 	const struct imx_fracn_gppll_rate_table *rate_table;
70 	int rate_count;
71 	u32 flags;
72 };
73 
74 /*
75  * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
76  * Fout = Fvco / odiv
77  * The (Fref / rdiv) should be in range 20MHz to 40MHz
78  * The Fvco should be in range 2.5Ghz to 5Ghz
79  */
80 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
81 	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
82 	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
83 	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
84 	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
85 	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
86 	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
87 	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
88 	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
89 	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
90 };
91 
92 struct imx_fracn_gppll_clk imx_fracn_gppll = {
93 	.rate_table = fracn_tbl,
94 	.rate_count = ARRAY_SIZE(fracn_tbl),
95 };
96 EXPORT_SYMBOL_GPL(imx_fracn_gppll);
97 
98 /*
99  * Fvco = (Fref / rdiv) * MFI
100  * Fout = Fvco / odiv
101  * The (Fref / rdiv) should be in range 20MHz to 40MHz
102  * The Fvco should be in range 2.5Ghz to 5Ghz
103  */
104 static const struct imx_fracn_gppll_rate_table int_tbl[] = {
105 	PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
106 	PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
107 	PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
108 };
109 
110 struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
111 	.rate_table = int_tbl,
112 	.rate_count = ARRAY_SIZE(int_tbl),
113 };
114 EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer);
115 
116 static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw)
117 {
118 	return container_of(hw, struct clk_fracn_gppll, hw);
119 }
120 
121 static const struct imx_fracn_gppll_rate_table *
122 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
123 {
124 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
125 	int i;
126 
127 	for (i = 0; i < pll->rate_count; i++)
128 		if (rate == rate_table[i].rate)
129 			return &rate_table[i];
130 
131 	return NULL;
132 }
133 
134 static long clk_fracn_gppll_round_rate(struct clk_hw *hw, unsigned long rate,
135 				       unsigned long *prate)
136 {
137 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
138 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
139 	int i;
140 
141 	/* Assuming rate_table is in descending order */
142 	for (i = 0; i < pll->rate_count; i++)
143 		if (rate >= rate_table[i].rate)
144 			return rate_table[i].rate;
145 
146 	/* return minimum supported value */
147 	return rate_table[pll->rate_count - 1].rate;
148 }
149 
150 static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
151 {
152 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
153 	const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
154 	u32 pll_numerator, pll_denominator, pll_div;
155 	u32 mfi, mfn, mfd, rdiv, odiv;
156 	u64 fvco = parent_rate;
157 	long rate = 0;
158 	int i;
159 
160 	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
161 	mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
162 
163 	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
164 	mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
165 
166 	pll_div = readl_relaxed(pll->base + PLL_DIV);
167 	mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
168 
169 	rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
170 	odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
171 
172 	/*
173 	 * Sometimes, the recalculated rate has deviation due to
174 	 * the frac part. So find the accurate pll rate from the table
175 	 * first, if no match rate in the table, use the rate calculated
176 	 * from the equation below.
177 	 */
178 	for (i = 0; i < pll->rate_count; i++) {
179 		if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
180 		    rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
181 		    rate_table[i].odiv == odiv)
182 			rate = rate_table[i].rate;
183 	}
184 
185 	if (rate)
186 		return (unsigned long)rate;
187 
188 	if (!rdiv)
189 		rdiv = rdiv + 1;
190 
191 	switch (odiv) {
192 	case 0:
193 		odiv = 2;
194 		break;
195 	case 1:
196 		odiv = 3;
197 		break;
198 	default:
199 		break;
200 	}
201 
202 	if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
203 		/* Fvco = (Fref / rdiv) * MFI */
204 		fvco = fvco * mfi;
205 		do_div(fvco, rdiv * odiv);
206 	} else {
207 		/* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
208 		fvco = fvco * mfi * mfd + fvco * mfn;
209 		do_div(fvco, mfd * rdiv * odiv);
210 	}
211 
212 	return (unsigned long)fvco;
213 }
214 
215 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
216 {
217 	u32 val;
218 
219 	return readl_poll_timeout(pll->base + PLL_STATUS, val,
220 				  val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);
221 }
222 
223 static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
224 				    unsigned long prate)
225 {
226 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
227 	const struct imx_fracn_gppll_rate_table *rate;
228 	u32 tmp, pll_div, ana_mfn;
229 	int ret;
230 
231 	rate = imx_get_pll_settings(pll, drate);
232 
233 	/* Hardware control select disable. PLL is control by register */
234 	tmp = readl_relaxed(pll->base + PLL_CTRL);
235 	tmp &= ~HW_CTRL_SEL;
236 	writel_relaxed(tmp, pll->base + PLL_CTRL);
237 
238 	/* Disable output */
239 	tmp = readl_relaxed(pll->base + PLL_CTRL);
240 	tmp &= ~CLKMUX_EN;
241 	writel_relaxed(tmp, pll->base + PLL_CTRL);
242 
243 	/* Power Down */
244 	tmp &= ~POWERUP_MASK;
245 	writel_relaxed(tmp, pll->base + PLL_CTRL);
246 
247 	/* Disable BYPASS */
248 	tmp &= ~CLKMUX_BYPASS;
249 	writel_relaxed(tmp, pll->base + PLL_CTRL);
250 
251 	pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
252 		FIELD_PREP(PLL_MFI_MASK, rate->mfi);
253 	writel_relaxed(pll_div, pll->base + PLL_DIV);
254 	if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
255 		writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
256 		writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
257 	}
258 
259 	/* Wait for 5us according to fracn mode pll doc */
260 	udelay(5);
261 
262 	/* Enable Powerup */
263 	tmp |= POWERUP_MASK;
264 	writel_relaxed(tmp, pll->base + PLL_CTRL);
265 
266 	/* Wait Lock */
267 	ret = clk_fracn_gppll_wait_lock(pll);
268 	if (ret)
269 		return ret;
270 
271 	/* Enable output */
272 	tmp |= CLKMUX_EN;
273 	writel_relaxed(tmp, pll->base + PLL_CTRL);
274 
275 	ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
276 	ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
277 
278 	WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
279 
280 	return 0;
281 }
282 
283 static int clk_fracn_gppll_prepare(struct clk_hw *hw)
284 {
285 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
286 	u32 val;
287 	int ret;
288 
289 	val = readl_relaxed(pll->base + PLL_CTRL);
290 	if (val & POWERUP_MASK)
291 		return 0;
292 
293 	val |= CLKMUX_BYPASS;
294 	writel_relaxed(val, pll->base + PLL_CTRL);
295 
296 	val |= POWERUP_MASK;
297 	writel_relaxed(val, pll->base + PLL_CTRL);
298 
299 	val |= CLKMUX_EN;
300 	writel_relaxed(val, pll->base + PLL_CTRL);
301 
302 	ret = clk_fracn_gppll_wait_lock(pll);
303 	if (ret)
304 		return ret;
305 
306 	val &= ~CLKMUX_BYPASS;
307 	writel_relaxed(val, pll->base + PLL_CTRL);
308 
309 	return 0;
310 }
311 
312 static int clk_fracn_gppll_is_prepared(struct clk_hw *hw)
313 {
314 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
315 	u32 val;
316 
317 	val = readl_relaxed(pll->base + PLL_CTRL);
318 
319 	return (val & POWERUP_MASK) ? 1 : 0;
320 }
321 
322 static void clk_fracn_gppll_unprepare(struct clk_hw *hw)
323 {
324 	struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
325 	u32 val;
326 
327 	val = readl_relaxed(pll->base + PLL_CTRL);
328 	val &= ~POWERUP_MASK;
329 	writel_relaxed(val, pll->base + PLL_CTRL);
330 }
331 
332 static const struct clk_ops clk_fracn_gppll_ops = {
333 	.prepare	= clk_fracn_gppll_prepare,
334 	.unprepare	= clk_fracn_gppll_unprepare,
335 	.is_prepared	= clk_fracn_gppll_is_prepared,
336 	.recalc_rate	= clk_fracn_gppll_recalc_rate,
337 	.round_rate	= clk_fracn_gppll_round_rate,
338 	.set_rate	= clk_fracn_gppll_set_rate,
339 };
340 
341 static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
342 					   void __iomem *base,
343 					   const struct imx_fracn_gppll_clk *pll_clk,
344 					   u32 pll_flags)
345 {
346 	struct clk_fracn_gppll *pll;
347 	struct clk_hw *hw;
348 	struct clk_init_data init;
349 	int ret;
350 
351 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
352 	if (!pll)
353 		return ERR_PTR(-ENOMEM);
354 
355 	init.name = name;
356 	init.flags = pll_clk->flags;
357 	init.parent_names = &parent_name;
358 	init.num_parents = 1;
359 	init.ops = &clk_fracn_gppll_ops;
360 
361 	pll->base = base;
362 	pll->hw.init = &init;
363 	pll->rate_table = pll_clk->rate_table;
364 	pll->rate_count = pll_clk->rate_count;
365 	pll->flags = pll_flags;
366 
367 	hw = &pll->hw;
368 
369 	ret = clk_hw_register(NULL, hw);
370 	if (ret) {
371 		pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
372 		kfree(pll);
373 		return ERR_PTR(ret);
374 	}
375 
376 	return hw;
377 }
378 
379 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
380 				   const struct imx_fracn_gppll_clk *pll_clk)
381 {
382 	return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
383 }
384 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll);
385 
386 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
387 					   void __iomem *base,
388 					   const struct imx_fracn_gppll_clk *pll_clk)
389 {
390 	return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
391 }
392 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer);
393