1d3ff9728SAbel Vesa // SPDX-License-Identifier: GPL-2.0 2d3ff9728SAbel Vesa /* 3d3ff9728SAbel Vesa * Copyright 2018 NXP 4d3ff9728SAbel Vesa */ 5d3ff9728SAbel Vesa 6d3ff9728SAbel Vesa #include <linux/clk-provider.h> 762e59c4eSStephen Boyd #include <linux/errno.h> 8870ed5e2SAnson Huang #include <linux/export.h> 962e59c4eSStephen Boyd #include <linux/io.h> 1062e59c4eSStephen Boyd #include <linux/slab.h> 11d3ff9728SAbel Vesa 12d3ff9728SAbel Vesa #include "clk.h" 13d3ff9728SAbel Vesa 14d3ff9728SAbel Vesa #define PCG_PREDIV_SHIFT 16 15d3ff9728SAbel Vesa #define PCG_PREDIV_WIDTH 3 16d3ff9728SAbel Vesa #define PCG_PREDIV_MAX 8 17d3ff9728SAbel Vesa 18d3ff9728SAbel Vesa #define PCG_DIV_SHIFT 0 1962668b68SPeng Fan #define PCG_CORE_DIV_WIDTH 3 20d3ff9728SAbel Vesa #define PCG_DIV_WIDTH 6 21d3ff9728SAbel Vesa #define PCG_DIV_MAX 64 22d3ff9728SAbel Vesa 23d3ff9728SAbel Vesa #define PCG_PCS_SHIFT 24 24d3ff9728SAbel Vesa #define PCG_PCS_MASK 0x7 25d3ff9728SAbel Vesa 26d3ff9728SAbel Vesa #define PCG_CGC_SHIFT 28 27d3ff9728SAbel Vesa 28d3ff9728SAbel Vesa static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, 29d3ff9728SAbel Vesa unsigned long parent_rate) 30d3ff9728SAbel Vesa { 31d3ff9728SAbel Vesa struct clk_divider *divider = to_clk_divider(hw); 32d3ff9728SAbel Vesa unsigned long prediv_rate; 33d3ff9728SAbel Vesa unsigned int prediv_value; 34d3ff9728SAbel Vesa unsigned int div_value; 35d3ff9728SAbel Vesa 36d3ff9728SAbel Vesa prediv_value = readl(divider->reg) >> divider->shift; 37d3ff9728SAbel Vesa prediv_value &= clk_div_mask(divider->width); 38d3ff9728SAbel Vesa 39d3ff9728SAbel Vesa prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value, 40d3ff9728SAbel Vesa NULL, divider->flags, 41d3ff9728SAbel Vesa divider->width); 42d3ff9728SAbel Vesa 43d3ff9728SAbel Vesa div_value = readl(divider->reg) >> PCG_DIV_SHIFT; 44d3ff9728SAbel Vesa div_value &= clk_div_mask(PCG_DIV_WIDTH); 45d3ff9728SAbel Vesa 46d3ff9728SAbel Vesa return divider_recalc_rate(hw, prediv_rate, div_value, NULL, 47d3ff9728SAbel Vesa divider->flags, PCG_DIV_WIDTH); 48d3ff9728SAbel Vesa } 49d3ff9728SAbel Vesa 50d3ff9728SAbel Vesa static int imx8m_clk_composite_compute_dividers(unsigned long rate, 51d3ff9728SAbel Vesa unsigned long parent_rate, 52d3ff9728SAbel Vesa int *prediv, int *postdiv) 53d3ff9728SAbel Vesa { 54d3ff9728SAbel Vesa int div1, div2; 55d3ff9728SAbel Vesa int error = INT_MAX; 56d3ff9728SAbel Vesa int ret = -EINVAL; 57d3ff9728SAbel Vesa 58d3ff9728SAbel Vesa *prediv = 1; 59d3ff9728SAbel Vesa *postdiv = 1; 60d3ff9728SAbel Vesa 61d3ff9728SAbel Vesa for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { 62d3ff9728SAbel Vesa for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { 63d3ff9728SAbel Vesa int new_error = ((parent_rate / div1) / div2) - rate; 64d3ff9728SAbel Vesa 65d3ff9728SAbel Vesa if (abs(new_error) < abs(error)) { 66d3ff9728SAbel Vesa *prediv = div1; 67d3ff9728SAbel Vesa *postdiv = div2; 68d3ff9728SAbel Vesa error = new_error; 69d3ff9728SAbel Vesa ret = 0; 70d3ff9728SAbel Vesa } 71d3ff9728SAbel Vesa } 72d3ff9728SAbel Vesa } 73d3ff9728SAbel Vesa return ret; 74d3ff9728SAbel Vesa } 75d3ff9728SAbel Vesa 76d3ff9728SAbel Vesa static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw, 77d3ff9728SAbel Vesa unsigned long rate, 78d3ff9728SAbel Vesa unsigned long *prate) 79d3ff9728SAbel Vesa { 80d3ff9728SAbel Vesa int prediv_value; 81d3ff9728SAbel Vesa int div_value; 82d3ff9728SAbel Vesa 83d3ff9728SAbel Vesa imx8m_clk_composite_compute_dividers(rate, *prate, 84d3ff9728SAbel Vesa &prediv_value, &div_value); 85d3ff9728SAbel Vesa rate = DIV_ROUND_UP(*prate, prediv_value); 86d3ff9728SAbel Vesa 87d3ff9728SAbel Vesa return DIV_ROUND_UP(rate, div_value); 88d3ff9728SAbel Vesa 89d3ff9728SAbel Vesa } 90d3ff9728SAbel Vesa 91d3ff9728SAbel Vesa static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, 92d3ff9728SAbel Vesa unsigned long rate, 93d3ff9728SAbel Vesa unsigned long parent_rate) 94d3ff9728SAbel Vesa { 95d3ff9728SAbel Vesa struct clk_divider *divider = to_clk_divider(hw); 9679ccef69SAnson Huang unsigned long flags; 97d3ff9728SAbel Vesa int prediv_value; 98d3ff9728SAbel Vesa int div_value; 9933e7a842SColin Ian King int ret; 100d3ff9728SAbel Vesa u32 val; 101d3ff9728SAbel Vesa 102d3ff9728SAbel Vesa ret = imx8m_clk_composite_compute_dividers(rate, parent_rate, 103d3ff9728SAbel Vesa &prediv_value, &div_value); 104d3ff9728SAbel Vesa if (ret) 105d3ff9728SAbel Vesa return -EINVAL; 106d3ff9728SAbel Vesa 107d3ff9728SAbel Vesa spin_lock_irqsave(divider->lock, flags); 108d3ff9728SAbel Vesa 109d3ff9728SAbel Vesa val = readl(divider->reg); 110d3ff9728SAbel Vesa val &= ~((clk_div_mask(divider->width) << divider->shift) | 111d3ff9728SAbel Vesa (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); 112d3ff9728SAbel Vesa 113d3ff9728SAbel Vesa val |= (u32)(prediv_value - 1) << divider->shift; 114d3ff9728SAbel Vesa val |= (u32)(div_value - 1) << PCG_DIV_SHIFT; 115d3ff9728SAbel Vesa writel(val, divider->reg); 116d3ff9728SAbel Vesa 117d3ff9728SAbel Vesa spin_unlock_irqrestore(divider->lock, flags); 118d3ff9728SAbel Vesa 119d3ff9728SAbel Vesa return ret; 120d3ff9728SAbel Vesa } 121d3ff9728SAbel Vesa 122d3ff9728SAbel Vesa static const struct clk_ops imx8m_clk_composite_divider_ops = { 123d3ff9728SAbel Vesa .recalc_rate = imx8m_clk_composite_divider_recalc_rate, 124d3ff9728SAbel Vesa .round_rate = imx8m_clk_composite_divider_round_rate, 125d3ff9728SAbel Vesa .set_rate = imx8m_clk_composite_divider_set_rate, 126d3ff9728SAbel Vesa }; 127d3ff9728SAbel Vesa 128f90b68d6SPeng Fan static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) 129f90b68d6SPeng Fan { 130f90b68d6SPeng Fan return clk_mux_ops.get_parent(hw); 131f90b68d6SPeng Fan } 132f90b68d6SPeng Fan 133f90b68d6SPeng Fan static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index) 134f90b68d6SPeng Fan { 135f90b68d6SPeng Fan struct clk_mux *mux = to_clk_mux(hw); 136f90b68d6SPeng Fan u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); 137f90b68d6SPeng Fan unsigned long flags = 0; 138f90b68d6SPeng Fan u32 reg; 139f90b68d6SPeng Fan 140f90b68d6SPeng Fan if (mux->lock) 141f90b68d6SPeng Fan spin_lock_irqsave(mux->lock, flags); 142f90b68d6SPeng Fan 143f90b68d6SPeng Fan reg = readl(mux->reg); 144f90b68d6SPeng Fan reg &= ~(mux->mask << mux->shift); 145f90b68d6SPeng Fan val = val << mux->shift; 146f90b68d6SPeng Fan reg |= val; 147f90b68d6SPeng Fan /* 148f90b68d6SPeng Fan * write twice to make sure non-target interface 149f90b68d6SPeng Fan * SEL_A/B point the same clk input. 150f90b68d6SPeng Fan */ 151f90b68d6SPeng Fan writel(reg, mux->reg); 152f90b68d6SPeng Fan writel(reg, mux->reg); 153f90b68d6SPeng Fan 154f90b68d6SPeng Fan if (mux->lock) 155f90b68d6SPeng Fan spin_unlock_irqrestore(mux->lock, flags); 156f90b68d6SPeng Fan 157f90b68d6SPeng Fan return 0; 158f90b68d6SPeng Fan } 159f90b68d6SPeng Fan 160f90b68d6SPeng Fan static int 161f90b68d6SPeng Fan imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw, 162f90b68d6SPeng Fan struct clk_rate_request *req) 163f90b68d6SPeng Fan { 164f90b68d6SPeng Fan return clk_mux_ops.determine_rate(hw, req); 165f90b68d6SPeng Fan } 166f90b68d6SPeng Fan 167f90b68d6SPeng Fan 168f90b68d6SPeng Fan static const struct clk_ops imx8m_clk_composite_mux_ops = { 169f90b68d6SPeng Fan .get_parent = imx8m_clk_composite_mux_get_parent, 170f90b68d6SPeng Fan .set_parent = imx8m_clk_composite_mux_set_parent, 171f90b68d6SPeng Fan .determine_rate = imx8m_clk_composite_mux_determine_rate, 172f90b68d6SPeng Fan }; 173f90b68d6SPeng Fan 174a60fe746SAbel Vesa struct clk_hw *__imx8m_clk_hw_composite(const char *name, 17565a6b7c5SAbel Vesa const char * const *parent_names, 176d3ff9728SAbel Vesa int num_parents, void __iomem *reg, 17762668b68SPeng Fan u32 composite_flags, 178d3ff9728SAbel Vesa unsigned long flags) 179d3ff9728SAbel Vesa { 180d3ff9728SAbel Vesa struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; 181*bb7e897bSPeng Fan struct clk_hw *div_hw, *gate_hw = NULL; 182d3ff9728SAbel Vesa struct clk_divider *div = NULL; 183d3ff9728SAbel Vesa struct clk_gate *gate = NULL; 184d3ff9728SAbel Vesa struct clk_mux *mux = NULL; 18562668b68SPeng Fan const struct clk_ops *divider_ops; 186f90b68d6SPeng Fan const struct clk_ops *mux_ops; 187d3ff9728SAbel Vesa 188d3ff9728SAbel Vesa mux = kzalloc(sizeof(*mux), GFP_KERNEL); 189d3ff9728SAbel Vesa if (!mux) 190d3ff9728SAbel Vesa goto fail; 191d3ff9728SAbel Vesa 192d3ff9728SAbel Vesa mux_hw = &mux->hw; 193d3ff9728SAbel Vesa mux->reg = reg; 194d3ff9728SAbel Vesa mux->shift = PCG_PCS_SHIFT; 195d3ff9728SAbel Vesa mux->mask = PCG_PCS_MASK; 196073a01e8SPeng Fan mux->lock = &imx_ccm_lock; 197d3ff9728SAbel Vesa 198d3ff9728SAbel Vesa div = kzalloc(sizeof(*div), GFP_KERNEL); 199d3ff9728SAbel Vesa if (!div) 200d3ff9728SAbel Vesa goto fail; 201d3ff9728SAbel Vesa 202d3ff9728SAbel Vesa div_hw = &div->hw; 203d3ff9728SAbel Vesa div->reg = reg; 20462668b68SPeng Fan if (composite_flags & IMX_COMPOSITE_CORE) { 20562668b68SPeng Fan div->shift = PCG_DIV_SHIFT; 20662668b68SPeng Fan div->width = PCG_CORE_DIV_WIDTH; 20762668b68SPeng Fan divider_ops = &clk_divider_ops; 208f90b68d6SPeng Fan mux_ops = &imx8m_clk_composite_mux_ops; 2090e40198dSPeng Fan } else if (composite_flags & IMX_COMPOSITE_BUS) { 2100e40198dSPeng Fan div->shift = PCG_PREDIV_SHIFT; 2110e40198dSPeng Fan div->width = PCG_PREDIV_WIDTH; 2120e40198dSPeng Fan divider_ops = &imx8m_clk_composite_divider_ops; 2130e40198dSPeng Fan mux_ops = &imx8m_clk_composite_mux_ops; 21462668b68SPeng Fan } else { 215d3ff9728SAbel Vesa div->shift = PCG_PREDIV_SHIFT; 216d3ff9728SAbel Vesa div->width = PCG_PREDIV_WIDTH; 21762668b68SPeng Fan divider_ops = &imx8m_clk_composite_divider_ops; 218f90b68d6SPeng Fan mux_ops = &clk_mux_ops; 219d36207b8SAhmad Fatoum if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED)) 220936c3836SPeng Fan flags |= CLK_SET_PARENT_GATE; 22162668b68SPeng Fan } 22262668b68SPeng Fan 223d3ff9728SAbel Vesa div->lock = &imx_ccm_lock; 224d3ff9728SAbel Vesa div->flags = CLK_DIVIDER_ROUND_CLOSEST; 225d3ff9728SAbel Vesa 226*bb7e897bSPeng Fan /* skip registering the gate ops if M4 is enabled */ 227*bb7e897bSPeng Fan if (!mcore_booted) { 228d3ff9728SAbel Vesa gate = kzalloc(sizeof(*gate), GFP_KERNEL); 229d3ff9728SAbel Vesa if (!gate) 230d3ff9728SAbel Vesa goto fail; 231d3ff9728SAbel Vesa 232d3ff9728SAbel Vesa gate_hw = &gate->hw; 233d3ff9728SAbel Vesa gate->reg = reg; 234d3ff9728SAbel Vesa gate->bit_idx = PCG_CGC_SHIFT; 235073a01e8SPeng Fan gate->lock = &imx_ccm_lock; 236*bb7e897bSPeng Fan } 237d3ff9728SAbel Vesa 238d3ff9728SAbel Vesa hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, 239f90b68d6SPeng Fan mux_hw, mux_ops, div_hw, 24062668b68SPeng Fan divider_ops, gate_hw, &clk_gate_ops, flags); 241d3ff9728SAbel Vesa if (IS_ERR(hw)) 242d3ff9728SAbel Vesa goto fail; 243d3ff9728SAbel Vesa 244a4b431f8SPeng Fan return hw; 245d3ff9728SAbel Vesa 246d3ff9728SAbel Vesa fail: 247d3ff9728SAbel Vesa kfree(gate); 248d3ff9728SAbel Vesa kfree(div); 249d3ff9728SAbel Vesa kfree(mux); 250d3ff9728SAbel Vesa return ERR_CAST(hw); 251d3ff9728SAbel Vesa } 252a60fe746SAbel Vesa EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); 253