1d3ff9728SAbel Vesa // SPDX-License-Identifier: GPL-2.0
2d3ff9728SAbel Vesa /*
3d3ff9728SAbel Vesa * Copyright 2018 NXP
4d3ff9728SAbel Vesa */
5d3ff9728SAbel Vesa
6d3ff9728SAbel Vesa #include <linux/clk-provider.h>
762e59c4eSStephen Boyd #include <linux/errno.h>
8870ed5e2SAnson Huang #include <linux/export.h>
962e59c4eSStephen Boyd #include <linux/io.h>
1062e59c4eSStephen Boyd #include <linux/slab.h>
11d3ff9728SAbel Vesa
12d3ff9728SAbel Vesa #include "clk.h"
13d3ff9728SAbel Vesa
14d3ff9728SAbel Vesa #define PCG_PREDIV_SHIFT 16
15d3ff9728SAbel Vesa #define PCG_PREDIV_WIDTH 3
16d3ff9728SAbel Vesa #define PCG_PREDIV_MAX 8
17d3ff9728SAbel Vesa
18d3ff9728SAbel Vesa #define PCG_DIV_SHIFT 0
1962668b68SPeng Fan #define PCG_CORE_DIV_WIDTH 3
20d3ff9728SAbel Vesa #define PCG_DIV_WIDTH 6
21d3ff9728SAbel Vesa #define PCG_DIV_MAX 64
22d3ff9728SAbel Vesa
23d3ff9728SAbel Vesa #define PCG_PCS_SHIFT 24
24d3ff9728SAbel Vesa #define PCG_PCS_MASK 0x7
25d3ff9728SAbel Vesa
26d3ff9728SAbel Vesa #define PCG_CGC_SHIFT 28
27d3ff9728SAbel Vesa
imx8m_clk_composite_divider_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)28d3ff9728SAbel Vesa static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
29d3ff9728SAbel Vesa unsigned long parent_rate)
30d3ff9728SAbel Vesa {
31d3ff9728SAbel Vesa struct clk_divider *divider = to_clk_divider(hw);
32d3ff9728SAbel Vesa unsigned long prediv_rate;
33d3ff9728SAbel Vesa unsigned int prediv_value;
34d3ff9728SAbel Vesa unsigned int div_value;
35d3ff9728SAbel Vesa
36d3ff9728SAbel Vesa prediv_value = readl(divider->reg) >> divider->shift;
37d3ff9728SAbel Vesa prediv_value &= clk_div_mask(divider->width);
38d3ff9728SAbel Vesa
39d3ff9728SAbel Vesa prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
40d3ff9728SAbel Vesa NULL, divider->flags,
41d3ff9728SAbel Vesa divider->width);
42d3ff9728SAbel Vesa
43d3ff9728SAbel Vesa div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
44d3ff9728SAbel Vesa div_value &= clk_div_mask(PCG_DIV_WIDTH);
45d3ff9728SAbel Vesa
46d3ff9728SAbel Vesa return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
47d3ff9728SAbel Vesa divider->flags, PCG_DIV_WIDTH);
48d3ff9728SAbel Vesa }
49d3ff9728SAbel Vesa
imx8m_clk_composite_compute_dividers(unsigned long rate,unsigned long parent_rate,int * prediv,int * postdiv)50d3ff9728SAbel Vesa static int imx8m_clk_composite_compute_dividers(unsigned long rate,
51d3ff9728SAbel Vesa unsigned long parent_rate,
52d3ff9728SAbel Vesa int *prediv, int *postdiv)
53d3ff9728SAbel Vesa {
54d3ff9728SAbel Vesa int div1, div2;
55d3ff9728SAbel Vesa int error = INT_MAX;
56d3ff9728SAbel Vesa int ret = -EINVAL;
57d3ff9728SAbel Vesa
58d3ff9728SAbel Vesa *prediv = 1;
59d3ff9728SAbel Vesa *postdiv = 1;
60d3ff9728SAbel Vesa
61d3ff9728SAbel Vesa for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
62d3ff9728SAbel Vesa for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
63d3ff9728SAbel Vesa int new_error = ((parent_rate / div1) / div2) - rate;
64d3ff9728SAbel Vesa
65d3ff9728SAbel Vesa if (abs(new_error) < abs(error)) {
66d3ff9728SAbel Vesa *prediv = div1;
67d3ff9728SAbel Vesa *postdiv = div2;
68d3ff9728SAbel Vesa error = new_error;
69d3ff9728SAbel Vesa ret = 0;
70d3ff9728SAbel Vesa }
71d3ff9728SAbel Vesa }
72d3ff9728SAbel Vesa }
73d3ff9728SAbel Vesa return ret;
74d3ff9728SAbel Vesa }
75d3ff9728SAbel Vesa
imx8m_clk_composite_divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)76d3ff9728SAbel Vesa static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
77d3ff9728SAbel Vesa unsigned long rate,
78d3ff9728SAbel Vesa unsigned long *prate)
79d3ff9728SAbel Vesa {
80d3ff9728SAbel Vesa int prediv_value;
81d3ff9728SAbel Vesa int div_value;
82d3ff9728SAbel Vesa
83d3ff9728SAbel Vesa imx8m_clk_composite_compute_dividers(rate, *prate,
84d3ff9728SAbel Vesa &prediv_value, &div_value);
85d3ff9728SAbel Vesa rate = DIV_ROUND_UP(*prate, prediv_value);
86d3ff9728SAbel Vesa
87d3ff9728SAbel Vesa return DIV_ROUND_UP(rate, div_value);
88d3ff9728SAbel Vesa
89d3ff9728SAbel Vesa }
90d3ff9728SAbel Vesa
imx8m_clk_composite_divider_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)91d3ff9728SAbel Vesa static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
92d3ff9728SAbel Vesa unsigned long rate,
93d3ff9728SAbel Vesa unsigned long parent_rate)
94d3ff9728SAbel Vesa {
95d3ff9728SAbel Vesa struct clk_divider *divider = to_clk_divider(hw);
9679ccef69SAnson Huang unsigned long flags;
97d3ff9728SAbel Vesa int prediv_value;
98d3ff9728SAbel Vesa int div_value;
9933e7a842SColin Ian King int ret;
100*4dd432d9SAhmad Fatoum u32 orig, val;
101d3ff9728SAbel Vesa
102d3ff9728SAbel Vesa ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
103d3ff9728SAbel Vesa &prediv_value, &div_value);
104d3ff9728SAbel Vesa if (ret)
105d3ff9728SAbel Vesa return -EINVAL;
106d3ff9728SAbel Vesa
107d3ff9728SAbel Vesa spin_lock_irqsave(divider->lock, flags);
108d3ff9728SAbel Vesa
109*4dd432d9SAhmad Fatoum orig = readl(divider->reg);
110*4dd432d9SAhmad Fatoum val = orig & ~((clk_div_mask(divider->width) << divider->shift) |
111d3ff9728SAbel Vesa (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
112d3ff9728SAbel Vesa
113d3ff9728SAbel Vesa val |= (u32)(prediv_value - 1) << divider->shift;
114d3ff9728SAbel Vesa val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
115*4dd432d9SAhmad Fatoum
116*4dd432d9SAhmad Fatoum if (val != orig)
117d3ff9728SAbel Vesa writel(val, divider->reg);
118d3ff9728SAbel Vesa
119d3ff9728SAbel Vesa spin_unlock_irqrestore(divider->lock, flags);
120d3ff9728SAbel Vesa
121d3ff9728SAbel Vesa return ret;
122d3ff9728SAbel Vesa }
123d3ff9728SAbel Vesa
imx8m_divider_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)1248208181fSAdam Ford static int imx8m_divider_determine_rate(struct clk_hw *hw,
1258208181fSAdam Ford struct clk_rate_request *req)
1268208181fSAdam Ford {
1278208181fSAdam Ford struct clk_divider *divider = to_clk_divider(hw);
1288208181fSAdam Ford int prediv_value;
1298208181fSAdam Ford int div_value;
1308208181fSAdam Ford
1318208181fSAdam Ford /* if read only, just return current value */
1328208181fSAdam Ford if (divider->flags & CLK_DIVIDER_READ_ONLY) {
1338208181fSAdam Ford u32 val;
1348208181fSAdam Ford
1358208181fSAdam Ford val = readl(divider->reg);
1368208181fSAdam Ford prediv_value = val >> divider->shift;
1378208181fSAdam Ford prediv_value &= clk_div_mask(divider->width);
1388208181fSAdam Ford prediv_value++;
1398208181fSAdam Ford
1408208181fSAdam Ford div_value = val >> PCG_DIV_SHIFT;
1418208181fSAdam Ford div_value &= clk_div_mask(PCG_DIV_WIDTH);
1428208181fSAdam Ford div_value++;
1438208181fSAdam Ford
1448208181fSAdam Ford return divider_ro_determine_rate(hw, req, divider->table,
1458208181fSAdam Ford PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
1468208181fSAdam Ford divider->flags, prediv_value * div_value);
1478208181fSAdam Ford }
1488208181fSAdam Ford
1498208181fSAdam Ford return divider_determine_rate(hw, req, divider->table,
1508208181fSAdam Ford PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
1518208181fSAdam Ford divider->flags);
1528208181fSAdam Ford }
1538208181fSAdam Ford
154d3ff9728SAbel Vesa static const struct clk_ops imx8m_clk_composite_divider_ops = {
155d3ff9728SAbel Vesa .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
156d3ff9728SAbel Vesa .round_rate = imx8m_clk_composite_divider_round_rate,
157d3ff9728SAbel Vesa .set_rate = imx8m_clk_composite_divider_set_rate,
1588208181fSAdam Ford .determine_rate = imx8m_divider_determine_rate,
159d3ff9728SAbel Vesa };
160d3ff9728SAbel Vesa
imx8m_clk_composite_mux_get_parent(struct clk_hw * hw)161f90b68d6SPeng Fan static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
162f90b68d6SPeng Fan {
163f90b68d6SPeng Fan return clk_mux_ops.get_parent(hw);
164f90b68d6SPeng Fan }
165f90b68d6SPeng Fan
imx8m_clk_composite_mux_set_parent(struct clk_hw * hw,u8 index)166f90b68d6SPeng Fan static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
167f90b68d6SPeng Fan {
168f90b68d6SPeng Fan struct clk_mux *mux = to_clk_mux(hw);
169f90b68d6SPeng Fan u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
170f90b68d6SPeng Fan unsigned long flags = 0;
171f90b68d6SPeng Fan u32 reg;
172f90b68d6SPeng Fan
173f90b68d6SPeng Fan if (mux->lock)
174f90b68d6SPeng Fan spin_lock_irqsave(mux->lock, flags);
175f90b68d6SPeng Fan
176f90b68d6SPeng Fan reg = readl(mux->reg);
177f90b68d6SPeng Fan reg &= ~(mux->mask << mux->shift);
178f90b68d6SPeng Fan val = val << mux->shift;
179f90b68d6SPeng Fan reg |= val;
180f90b68d6SPeng Fan /*
181f90b68d6SPeng Fan * write twice to make sure non-target interface
182f90b68d6SPeng Fan * SEL_A/B point the same clk input.
183f90b68d6SPeng Fan */
184f90b68d6SPeng Fan writel(reg, mux->reg);
185f90b68d6SPeng Fan writel(reg, mux->reg);
186f90b68d6SPeng Fan
187f90b68d6SPeng Fan if (mux->lock)
188f90b68d6SPeng Fan spin_unlock_irqrestore(mux->lock, flags);
189f90b68d6SPeng Fan
190f90b68d6SPeng Fan return 0;
191f90b68d6SPeng Fan }
192f90b68d6SPeng Fan
193f90b68d6SPeng Fan static int
imx8m_clk_composite_mux_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)194f90b68d6SPeng Fan imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
195f90b68d6SPeng Fan struct clk_rate_request *req)
196f90b68d6SPeng Fan {
197f90b68d6SPeng Fan return clk_mux_ops.determine_rate(hw, req);
198f90b68d6SPeng Fan }
199f90b68d6SPeng Fan
200f90b68d6SPeng Fan
201f90b68d6SPeng Fan static const struct clk_ops imx8m_clk_composite_mux_ops = {
202f90b68d6SPeng Fan .get_parent = imx8m_clk_composite_mux_get_parent,
203f90b68d6SPeng Fan .set_parent = imx8m_clk_composite_mux_set_parent,
204f90b68d6SPeng Fan .determine_rate = imx8m_clk_composite_mux_determine_rate,
205f90b68d6SPeng Fan };
206f90b68d6SPeng Fan
__imx8m_clk_hw_composite(const char * name,const char * const * parent_names,int num_parents,void __iomem * reg,u32 composite_flags,unsigned long flags)207a60fe746SAbel Vesa struct clk_hw *__imx8m_clk_hw_composite(const char *name,
20865a6b7c5SAbel Vesa const char * const *parent_names,
209d3ff9728SAbel Vesa int num_parents, void __iomem *reg,
21062668b68SPeng Fan u32 composite_flags,
211d3ff9728SAbel Vesa unsigned long flags)
212d3ff9728SAbel Vesa {
213d3ff9728SAbel Vesa struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
214bb7e897bSPeng Fan struct clk_hw *div_hw, *gate_hw = NULL;
215d3ff9728SAbel Vesa struct clk_divider *div = NULL;
216d3ff9728SAbel Vesa struct clk_gate *gate = NULL;
217d3ff9728SAbel Vesa struct clk_mux *mux = NULL;
21862668b68SPeng Fan const struct clk_ops *divider_ops;
219f90b68d6SPeng Fan const struct clk_ops *mux_ops;
220d3ff9728SAbel Vesa
221d3ff9728SAbel Vesa mux = kzalloc(sizeof(*mux), GFP_KERNEL);
222d3ff9728SAbel Vesa if (!mux)
223d3ff9728SAbel Vesa goto fail;
224d3ff9728SAbel Vesa
225d3ff9728SAbel Vesa mux_hw = &mux->hw;
226d3ff9728SAbel Vesa mux->reg = reg;
227d3ff9728SAbel Vesa mux->shift = PCG_PCS_SHIFT;
228d3ff9728SAbel Vesa mux->mask = PCG_PCS_MASK;
229073a01e8SPeng Fan mux->lock = &imx_ccm_lock;
230d3ff9728SAbel Vesa
231d3ff9728SAbel Vesa div = kzalloc(sizeof(*div), GFP_KERNEL);
232d3ff9728SAbel Vesa if (!div)
233d3ff9728SAbel Vesa goto fail;
234d3ff9728SAbel Vesa
235d3ff9728SAbel Vesa div_hw = &div->hw;
236d3ff9728SAbel Vesa div->reg = reg;
23762668b68SPeng Fan if (composite_flags & IMX_COMPOSITE_CORE) {
23862668b68SPeng Fan div->shift = PCG_DIV_SHIFT;
23962668b68SPeng Fan div->width = PCG_CORE_DIV_WIDTH;
24062668b68SPeng Fan divider_ops = &clk_divider_ops;
241f90b68d6SPeng Fan mux_ops = &imx8m_clk_composite_mux_ops;
2420e40198dSPeng Fan } else if (composite_flags & IMX_COMPOSITE_BUS) {
2430e40198dSPeng Fan div->shift = PCG_PREDIV_SHIFT;
2440e40198dSPeng Fan div->width = PCG_PREDIV_WIDTH;
2450e40198dSPeng Fan divider_ops = &imx8m_clk_composite_divider_ops;
2460e40198dSPeng Fan mux_ops = &imx8m_clk_composite_mux_ops;
24762668b68SPeng Fan } else {
248d3ff9728SAbel Vesa div->shift = PCG_PREDIV_SHIFT;
249d3ff9728SAbel Vesa div->width = PCG_PREDIV_WIDTH;
25062668b68SPeng Fan divider_ops = &imx8m_clk_composite_divider_ops;
251f90b68d6SPeng Fan mux_ops = &clk_mux_ops;
252d36207b8SAhmad Fatoum if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
253936c3836SPeng Fan flags |= CLK_SET_PARENT_GATE;
25462668b68SPeng Fan }
25562668b68SPeng Fan
256d3ff9728SAbel Vesa div->lock = &imx_ccm_lock;
257d3ff9728SAbel Vesa div->flags = CLK_DIVIDER_ROUND_CLOSEST;
258d3ff9728SAbel Vesa
259bb7e897bSPeng Fan /* skip registering the gate ops if M4 is enabled */
260bb7e897bSPeng Fan if (!mcore_booted) {
261d3ff9728SAbel Vesa gate = kzalloc(sizeof(*gate), GFP_KERNEL);
262d3ff9728SAbel Vesa if (!gate)
263d3ff9728SAbel Vesa goto fail;
264d3ff9728SAbel Vesa
265d3ff9728SAbel Vesa gate_hw = &gate->hw;
266d3ff9728SAbel Vesa gate->reg = reg;
267d3ff9728SAbel Vesa gate->bit_idx = PCG_CGC_SHIFT;
268073a01e8SPeng Fan gate->lock = &imx_ccm_lock;
269bb7e897bSPeng Fan }
270d3ff9728SAbel Vesa
271d3ff9728SAbel Vesa hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
272f90b68d6SPeng Fan mux_hw, mux_ops, div_hw,
27362668b68SPeng Fan divider_ops, gate_hw, &clk_gate_ops, flags);
274d3ff9728SAbel Vesa if (IS_ERR(hw))
275d3ff9728SAbel Vesa goto fail;
276d3ff9728SAbel Vesa
277a4b431f8SPeng Fan return hw;
278d3ff9728SAbel Vesa
279d3ff9728SAbel Vesa fail:
280d3ff9728SAbel Vesa kfree(gate);
281d3ff9728SAbel Vesa kfree(div);
282d3ff9728SAbel Vesa kfree(mux);
283d3ff9728SAbel Vesa return ERR_CAST(hw);
284d3ff9728SAbel Vesa }
285a60fe746SAbel Vesa EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite);
286