1 /* 2 * Hi3798CV200 Clock and Reset Generator Driver 3 * 4 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <dt-bindings/clock/histb-clock.h> 21 #include <linux/clk-provider.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include "clk.h" 26 #include "crg.h" 27 #include "reset.h" 28 29 /* hi3798CV200 core CRG */ 30 #define HI3798CV200_INNER_CLK_OFFSET 64 31 #define HI3798CV200_FIXED_24M 65 32 #define HI3798CV200_FIXED_25M 66 33 #define HI3798CV200_FIXED_50M 67 34 #define HI3798CV200_FIXED_75M 68 35 #define HI3798CV200_FIXED_100M 69 36 #define HI3798CV200_FIXED_150M 70 37 #define HI3798CV200_FIXED_200M 71 38 #define HI3798CV200_FIXED_250M 72 39 #define HI3798CV200_FIXED_300M 73 40 #define HI3798CV200_FIXED_400M 74 41 #define HI3798CV200_MMC_MUX 75 42 #define HI3798CV200_ETH_PUB_CLK 76 43 #define HI3798CV200_ETH_BUS_CLK 77 44 #define HI3798CV200_ETH_BUS0_CLK 78 45 #define HI3798CV200_ETH_BUS1_CLK 79 46 #define HI3798CV200_COMBPHY1_MUX 80 47 #define HI3798CV200_FIXED_12M 81 48 #define HI3798CV200_FIXED_48M 82 49 #define HI3798CV200_FIXED_60M 83 50 #define HI3798CV200_FIXED_166P5M 84 51 #define HI3798CV200_SDIO0_MUX 85 52 #define HI3798CV200_COMBPHY0_MUX 86 53 54 #define HI3798CV200_CRG_NR_CLKS 128 55 56 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { 57 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, 58 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, 59 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, 60 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, 61 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, 62 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, 63 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, 64 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, 65 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, 66 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, 67 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, 68 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, 69 { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, 70 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, 71 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, 72 }; 73 74 static const char *const mmc_mux_p[] = { 75 "100m", "50m", "25m", "200m", "150m" }; 76 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6}; 77 78 static const char *const comphy_mux_p[] = { 79 "100m", "25m"}; 80 static u32 comphy_mux_table[] = {2, 3}; 81 82 static const char *const sdio_mux_p[] = { 83 "100m", "50m", "150m", "166p5m" }; 84 static u32 sdio_mux_table[] = {0, 1, 2, 3}; 85 86 static struct hisi_mux_clock hi3798cv200_mux_clks[] = { 87 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 88 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, 89 { HI3798CV200_COMBPHY0_MUX, "combphy0_mux", 90 comphy_mux_p, ARRAY_SIZE(comphy_mux_p), 91 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, 92 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", 93 comphy_mux_p, ARRAY_SIZE(comphy_mux_p), 94 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, 95 { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, 96 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, 97 0x9c, 8, 2, 0, sdio_mux_table, }, 98 }; 99 100 static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7}; 101 static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315}; 102 103 static struct hisi_phase_clock hi3798cv200_phase_clks[] = { 104 { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", 105 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, 106 mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, 107 { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", 108 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, 109 mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, 110 }; 111 112 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 113 /* UART */ 114 { HISTB_UART2_CLK, "clk_uart2", "75m", 115 CLK_SET_RATE_PARENT, 0x68, 4, 0, }, 116 /* I2C */ 117 { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", 118 CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, 119 { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", 120 CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, 121 { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", 122 CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, 123 { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb", 124 CLK_SET_RATE_PARENT, 0x6C, 16, 0, }, 125 { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb", 126 CLK_SET_RATE_PARENT, 0x6C, 20, 0, }, 127 /* SPI */ 128 { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", 129 CLK_SET_RATE_PARENT, 0x70, 0, 0, }, 130 /* SDIO */ 131 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", 132 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 133 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", 134 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 135 /* EMMC */ 136 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", 137 CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, 138 { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", 139 CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, 140 /* PCIE*/ 141 { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m", 142 CLK_SET_RATE_PARENT, 0x18c, 0, 0, }, 143 { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m", 144 CLK_SET_RATE_PARENT, 0x18c, 1, 0, }, 145 { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m", 146 CLK_SET_RATE_PARENT, 0x18c, 2, 0, }, 147 { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", 148 CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, 149 /* Ethernet */ 150 { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, 151 CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, 152 { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", 153 CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, 154 { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", 155 CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, 156 { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", 157 CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, 158 { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", 159 CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, 160 { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0", 161 CLK_SET_RATE_PARENT, 0xcc, 24, 0, }, 162 { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1", 163 CLK_SET_RATE_PARENT, 0xcc, 4, 0, }, 164 { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1", 165 CLK_SET_RATE_PARENT, 0xcc, 25, 0, }, 166 /* COMBPHY0 */ 167 { HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux", 168 CLK_SET_RATE_PARENT, 0x188, 0, 0, }, 169 /* COMBPHY1 */ 170 { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux", 171 CLK_SET_RATE_PARENT, 0x188, 8, 0, }, 172 /* USB2 */ 173 { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", 174 CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, 175 { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", 176 CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, 177 { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", 178 CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, 179 { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", 180 CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, 181 { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", 182 CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, 183 { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", 184 CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, 185 { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", 186 CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, 187 { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", 188 CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, 189 }; 190 191 static struct hisi_clock_data *hi3798cv200_clk_register( 192 struct platform_device *pdev) 193 { 194 struct hisi_clock_data *clk_data; 195 int ret; 196 197 clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); 198 if (!clk_data) 199 return ERR_PTR(-ENOMEM); 200 201 /* hisi_phase_clock is resource managed */ 202 ret = hisi_clk_register_phase(&pdev->dev, 203 hi3798cv200_phase_clks, 204 ARRAY_SIZE(hi3798cv200_phase_clks), 205 clk_data); 206 if (ret) 207 return ERR_PTR(ret); 208 209 ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, 210 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 211 clk_data); 212 if (ret) 213 return ERR_PTR(ret); 214 215 ret = hisi_clk_register_mux(hi3798cv200_mux_clks, 216 ARRAY_SIZE(hi3798cv200_mux_clks), 217 clk_data); 218 if (ret) 219 goto unregister_fixed_rate; 220 221 ret = hisi_clk_register_gate(hi3798cv200_gate_clks, 222 ARRAY_SIZE(hi3798cv200_gate_clks), 223 clk_data); 224 if (ret) 225 goto unregister_mux; 226 227 ret = of_clk_add_provider(pdev->dev.of_node, 228 of_clk_src_onecell_get, &clk_data->clk_data); 229 if (ret) 230 goto unregister_gate; 231 232 return clk_data; 233 234 unregister_gate: 235 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 236 ARRAY_SIZE(hi3798cv200_gate_clks), 237 clk_data); 238 unregister_mux: 239 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 240 ARRAY_SIZE(hi3798cv200_mux_clks), 241 clk_data); 242 unregister_fixed_rate: 243 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 244 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 245 clk_data); 246 return ERR_PTR(ret); 247 } 248 249 static void hi3798cv200_clk_unregister(struct platform_device *pdev) 250 { 251 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 252 253 of_clk_del_provider(pdev->dev.of_node); 254 255 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 256 ARRAY_SIZE(hi3798cv200_gate_clks), 257 crg->clk_data); 258 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 259 ARRAY_SIZE(hi3798cv200_mux_clks), 260 crg->clk_data); 261 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 262 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 263 crg->clk_data); 264 } 265 266 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { 267 .register_clks = hi3798cv200_clk_register, 268 .unregister_clks = hi3798cv200_clk_unregister, 269 }; 270 271 /* hi3798CV200 sysctrl CRG */ 272 273 #define HI3798CV200_SYSCTRL_NR_CLKS 16 274 275 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { 276 { HISTB_IR_CLK, "clk_ir", "24m", 277 CLK_SET_RATE_PARENT, 0x48, 4, 0, }, 278 { HISTB_TIMER01_CLK, "clk_timer01", "24m", 279 CLK_SET_RATE_PARENT, 0x48, 6, 0, }, 280 { HISTB_UART0_CLK, "clk_uart0", "75m", 281 CLK_SET_RATE_PARENT, 0x48, 10, 0, }, 282 }; 283 284 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( 285 struct platform_device *pdev) 286 { 287 struct hisi_clock_data *clk_data; 288 int ret; 289 290 clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); 291 if (!clk_data) 292 return ERR_PTR(-ENOMEM); 293 294 ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, 295 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 296 clk_data); 297 if (ret) 298 return ERR_PTR(ret); 299 300 ret = of_clk_add_provider(pdev->dev.of_node, 301 of_clk_src_onecell_get, &clk_data->clk_data); 302 if (ret) 303 goto unregister_gate; 304 305 return clk_data; 306 307 unregister_gate: 308 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 309 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 310 clk_data); 311 return ERR_PTR(ret); 312 } 313 314 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) 315 { 316 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 317 318 of_clk_del_provider(pdev->dev.of_node); 319 320 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 321 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 322 crg->clk_data); 323 } 324 325 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { 326 .register_clks = hi3798cv200_sysctrl_clk_register, 327 .unregister_clks = hi3798cv200_sysctrl_clk_unregister, 328 }; 329 330 static const struct of_device_id hi3798cv200_crg_match_table[] = { 331 { .compatible = "hisilicon,hi3798cv200-crg", 332 .data = &hi3798cv200_crg_funcs }, 333 { .compatible = "hisilicon,hi3798cv200-sysctrl", 334 .data = &hi3798cv200_sysctrl_funcs }, 335 { } 336 }; 337 MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); 338 339 static int hi3798cv200_crg_probe(struct platform_device *pdev) 340 { 341 struct hisi_crg_dev *crg; 342 343 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); 344 if (!crg) 345 return -ENOMEM; 346 347 crg->funcs = of_device_get_match_data(&pdev->dev); 348 if (!crg->funcs) 349 return -ENOENT; 350 351 crg->rstc = hisi_reset_init(pdev); 352 if (!crg->rstc) 353 return -ENOMEM; 354 355 crg->clk_data = crg->funcs->register_clks(pdev); 356 if (IS_ERR(crg->clk_data)) { 357 hisi_reset_exit(crg->rstc); 358 return PTR_ERR(crg->clk_data); 359 } 360 361 platform_set_drvdata(pdev, crg); 362 return 0; 363 } 364 365 static int hi3798cv200_crg_remove(struct platform_device *pdev) 366 { 367 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 368 369 hisi_reset_exit(crg->rstc); 370 crg->funcs->unregister_clks(pdev); 371 return 0; 372 } 373 374 static struct platform_driver hi3798cv200_crg_driver = { 375 .probe = hi3798cv200_crg_probe, 376 .remove = hi3798cv200_crg_remove, 377 .driver = { 378 .name = "hi3798cv200-crg", 379 .of_match_table = hi3798cv200_crg_match_table, 380 }, 381 }; 382 383 static int __init hi3798cv200_crg_init(void) 384 { 385 return platform_driver_register(&hi3798cv200_crg_driver); 386 } 387 core_initcall(hi3798cv200_crg_init); 388 389 static void __exit hi3798cv200_crg_exit(void) 390 { 391 platform_driver_unregister(&hi3798cv200_crg_driver); 392 } 393 module_exit(hi3798cv200_crg_exit); 394 395 MODULE_LICENSE("GPL v2"); 396 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); 397