1 /* 2 * Hi3798CV200 Clock and Reset Generator Driver 3 * 4 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <dt-bindings/clock/histb-clock.h> 21 #include <linux/clk-provider.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include "clk.h" 26 #include "crg.h" 27 #include "reset.h" 28 29 /* hi3798CV200 core CRG */ 30 #define HI3798CV200_INNER_CLK_OFFSET 64 31 #define HI3798CV200_FIXED_24M 65 32 #define HI3798CV200_FIXED_25M 66 33 #define HI3798CV200_FIXED_50M 67 34 #define HI3798CV200_FIXED_75M 68 35 #define HI3798CV200_FIXED_100M 69 36 #define HI3798CV200_FIXED_150M 70 37 #define HI3798CV200_FIXED_200M 71 38 #define HI3798CV200_FIXED_250M 72 39 #define HI3798CV200_FIXED_300M 73 40 #define HI3798CV200_FIXED_400M 74 41 #define HI3798CV200_MMC_MUX 75 42 #define HI3798CV200_ETH_PUB_CLK 76 43 #define HI3798CV200_ETH_BUS_CLK 77 44 #define HI3798CV200_ETH_BUS0_CLK 78 45 #define HI3798CV200_ETH_BUS1_CLK 79 46 #define HI3798CV200_COMBPHY1_MUX 80 47 #define HI3798CV200_FIXED_12M 81 48 #define HI3798CV200_FIXED_48M 82 49 #define HI3798CV200_FIXED_60M 83 50 #define HI3798CV200_FIXED_166P5M 84 51 #define HI3798CV200_SDIO0_MUX 85 52 53 #define HI3798CV200_CRG_NR_CLKS 128 54 55 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { 56 { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, 57 { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, 58 { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, 59 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, 60 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, 61 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, 62 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, 63 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, 64 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, 65 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, 66 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, 67 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, 68 { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, 69 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, 70 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, 71 }; 72 73 static const char *const mmc_mux_p[] = { 74 "100m", "50m", "25m", "200m", "150m" }; 75 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6}; 76 77 static const char *const comphy1_mux_p[] = { 78 "100m", "25m"}; 79 static u32 comphy1_mux_table[] = {2, 3}; 80 81 static const char *const sdio_mux_p[] = { 82 "100m", "50m", "150m", "166p5m" }; 83 static u32 sdio_mux_table[] = {0, 1, 2, 3}; 84 85 static struct hisi_mux_clock hi3798cv200_mux_clks[] = { 86 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 87 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, 88 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", 89 comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p), 90 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, }, 91 { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, 92 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, 93 0x9c, 8, 2, 0, sdio_mux_table, }, 94 }; 95 96 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 97 /* UART */ 98 { HISTB_UART2_CLK, "clk_uart2", "75m", 99 CLK_SET_RATE_PARENT, 0x68, 4, 0, }, 100 /* I2C */ 101 { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", 102 CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, 103 { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", 104 CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, 105 { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", 106 CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, 107 { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb", 108 CLK_SET_RATE_PARENT, 0x6C, 16, 0, }, 109 { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb", 110 CLK_SET_RATE_PARENT, 0x6C, 20, 0, }, 111 /* SPI */ 112 { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", 113 CLK_SET_RATE_PARENT, 0x70, 0, 0, }, 114 /* SDIO */ 115 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", 116 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 117 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", 118 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 119 /* EMMC */ 120 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", 121 CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, 122 { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", 123 CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, 124 /* PCIE*/ 125 { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m", 126 CLK_SET_RATE_PARENT, 0x18c, 0, 0, }, 127 { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m", 128 CLK_SET_RATE_PARENT, 0x18c, 1, 0, }, 129 { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m", 130 CLK_SET_RATE_PARENT, 0x18c, 2, 0, }, 131 { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", 132 CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, 133 /* Ethernet */ 134 { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, 135 CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, 136 { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", 137 CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, 138 { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", 139 CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, 140 { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", 141 CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, 142 { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", 143 CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, 144 { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0", 145 CLK_SET_RATE_PARENT, 0xcc, 24, 0, }, 146 { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1", 147 CLK_SET_RATE_PARENT, 0xcc, 4, 0, }, 148 { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1", 149 CLK_SET_RATE_PARENT, 0xcc, 25, 0, }, 150 /* COMBPHY1 */ 151 { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux", 152 CLK_SET_RATE_PARENT, 0x188, 8, 0, }, 153 /* USB2 */ 154 { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", 155 CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, 156 { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", 157 CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, 158 { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", 159 CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, 160 { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", 161 CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, 162 { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", 163 CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, 164 { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", 165 CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, 166 { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", 167 CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, 168 }; 169 170 static struct hisi_clock_data *hi3798cv200_clk_register( 171 struct platform_device *pdev) 172 { 173 struct hisi_clock_data *clk_data; 174 int ret; 175 176 clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); 177 if (!clk_data) 178 return ERR_PTR(-ENOMEM); 179 180 ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, 181 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 182 clk_data); 183 if (ret) 184 return ERR_PTR(ret); 185 186 ret = hisi_clk_register_mux(hi3798cv200_mux_clks, 187 ARRAY_SIZE(hi3798cv200_mux_clks), 188 clk_data); 189 if (ret) 190 goto unregister_fixed_rate; 191 192 ret = hisi_clk_register_gate(hi3798cv200_gate_clks, 193 ARRAY_SIZE(hi3798cv200_gate_clks), 194 clk_data); 195 if (ret) 196 goto unregister_mux; 197 198 ret = of_clk_add_provider(pdev->dev.of_node, 199 of_clk_src_onecell_get, &clk_data->clk_data); 200 if (ret) 201 goto unregister_gate; 202 203 return clk_data; 204 205 unregister_fixed_rate: 206 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 207 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 208 clk_data); 209 210 unregister_mux: 211 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 212 ARRAY_SIZE(hi3798cv200_mux_clks), 213 clk_data); 214 unregister_gate: 215 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 216 ARRAY_SIZE(hi3798cv200_gate_clks), 217 clk_data); 218 return ERR_PTR(ret); 219 } 220 221 static void hi3798cv200_clk_unregister(struct platform_device *pdev) 222 { 223 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 224 225 of_clk_del_provider(pdev->dev.of_node); 226 227 hisi_clk_unregister_gate(hi3798cv200_gate_clks, 228 ARRAY_SIZE(hi3798cv200_gate_clks), 229 crg->clk_data); 230 hisi_clk_unregister_mux(hi3798cv200_mux_clks, 231 ARRAY_SIZE(hi3798cv200_mux_clks), 232 crg->clk_data); 233 hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, 234 ARRAY_SIZE(hi3798cv200_fixed_rate_clks), 235 crg->clk_data); 236 } 237 238 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { 239 .register_clks = hi3798cv200_clk_register, 240 .unregister_clks = hi3798cv200_clk_unregister, 241 }; 242 243 /* hi3798CV200 sysctrl CRG */ 244 245 #define HI3798CV200_SYSCTRL_NR_CLKS 16 246 247 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { 248 { HISTB_IR_CLK, "clk_ir", "100m", 249 CLK_SET_RATE_PARENT, 0x48, 4, 0, }, 250 { HISTB_TIMER01_CLK, "clk_timer01", "24m", 251 CLK_SET_RATE_PARENT, 0x48, 6, 0, }, 252 { HISTB_UART0_CLK, "clk_uart0", "75m", 253 CLK_SET_RATE_PARENT, 0x48, 10, 0, }, 254 }; 255 256 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( 257 struct platform_device *pdev) 258 { 259 struct hisi_clock_data *clk_data; 260 int ret; 261 262 clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); 263 if (!clk_data) 264 return ERR_PTR(-ENOMEM); 265 266 ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, 267 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 268 clk_data); 269 if (ret) 270 return ERR_PTR(ret); 271 272 ret = of_clk_add_provider(pdev->dev.of_node, 273 of_clk_src_onecell_get, &clk_data->clk_data); 274 if (ret) 275 goto unregister_gate; 276 277 return clk_data; 278 279 unregister_gate: 280 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 281 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 282 clk_data); 283 return ERR_PTR(ret); 284 } 285 286 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) 287 { 288 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 289 290 of_clk_del_provider(pdev->dev.of_node); 291 292 hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, 293 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), 294 crg->clk_data); 295 } 296 297 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { 298 .register_clks = hi3798cv200_sysctrl_clk_register, 299 .unregister_clks = hi3798cv200_sysctrl_clk_unregister, 300 }; 301 302 static const struct of_device_id hi3798cv200_crg_match_table[] = { 303 { .compatible = "hisilicon,hi3798cv200-crg", 304 .data = &hi3798cv200_crg_funcs }, 305 { .compatible = "hisilicon,hi3798cv200-sysctrl", 306 .data = &hi3798cv200_sysctrl_funcs }, 307 { } 308 }; 309 MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); 310 311 static int hi3798cv200_crg_probe(struct platform_device *pdev) 312 { 313 struct hisi_crg_dev *crg; 314 315 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); 316 if (!crg) 317 return -ENOMEM; 318 319 crg->funcs = of_device_get_match_data(&pdev->dev); 320 if (!crg->funcs) 321 return -ENOENT; 322 323 crg->rstc = hisi_reset_init(pdev); 324 if (!crg->rstc) 325 return -ENOMEM; 326 327 crg->clk_data = crg->funcs->register_clks(pdev); 328 if (IS_ERR(crg->clk_data)) { 329 hisi_reset_exit(crg->rstc); 330 return PTR_ERR(crg->clk_data); 331 } 332 333 platform_set_drvdata(pdev, crg); 334 return 0; 335 } 336 337 static int hi3798cv200_crg_remove(struct platform_device *pdev) 338 { 339 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 340 341 hisi_reset_exit(crg->rstc); 342 crg->funcs->unregister_clks(pdev); 343 return 0; 344 } 345 346 static struct platform_driver hi3798cv200_crg_driver = { 347 .probe = hi3798cv200_crg_probe, 348 .remove = hi3798cv200_crg_remove, 349 .driver = { 350 .name = "hi3798cv200-crg", 351 .of_match_table = hi3798cv200_crg_match_table, 352 }, 353 }; 354 355 static int __init hi3798cv200_crg_init(void) 356 { 357 return platform_driver_register(&hi3798cv200_crg_driver); 358 } 359 core_initcall(hi3798cv200_crg_init); 360 361 static void __exit hi3798cv200_crg_exit(void) 362 { 363 platform_driver_unregister(&hi3798cv200_crg_driver); 364 } 365 module_exit(hi3798cv200_crg_exit); 366 367 MODULE_LICENSE("GPL v2"); 368 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); 369