1 /* 2 * Hi3516CV300 Clock and Reset Generator Driver 3 * 4 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <dt-bindings/clock/hi3516cv300-clock.h> 21 #include <linux/clk-provider.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include "clk.h" 26 #include "crg.h" 27 #include "reset.h" 28 29 /* hi3516CV300 core CRG */ 30 #define HI3516CV300_INNER_CLK_OFFSET 64 31 #define HI3516CV300_FIXED_3M 65 32 #define HI3516CV300_FIXED_6M 66 33 #define HI3516CV300_FIXED_24M 67 34 #define HI3516CV300_FIXED_49P5 68 35 #define HI3516CV300_FIXED_50M 69 36 #define HI3516CV300_FIXED_83P3M 70 37 #define HI3516CV300_FIXED_99M 71 38 #define HI3516CV300_FIXED_100M 72 39 #define HI3516CV300_FIXED_148P5M 73 40 #define HI3516CV300_FIXED_198M 74 41 #define HI3516CV300_FIXED_297M 75 42 #define HI3516CV300_UART_MUX 76 43 #define HI3516CV300_FMC_MUX 77 44 #define HI3516CV300_MMC0_MUX 78 45 #define HI3516CV300_MMC1_MUX 79 46 #define HI3516CV300_MMC2_MUX 80 47 #define HI3516CV300_MMC3_MUX 81 48 #define HI3516CV300_PWM_MUX 82 49 #define HI3516CV300_CRG_NR_CLKS 128 50 51 static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = { 52 { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, }, 53 { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, }, 54 { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, }, 55 { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, }, 56 { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, }, 57 { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, }, 58 { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, }, 59 { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, }, 60 { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, }, 61 { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, }, 62 { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, }, 63 { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, }, 64 }; 65 66 static const char *const uart_mux_p[] = {"24m", "6m"}; 67 static const char *const fmc_mux_p[] = { 68 "24m", "83.3m", "148.5m", "198m", "297m" 69 }; 70 static const char *const mmc_mux_p[] = {"49.5m"}; 71 static const char *const mmc2_mux_p[] = {"99m", "49.5m"}; 72 static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"}; 73 74 static u32 uart_mux_table[] = {0, 1}; 75 static u32 fmc_mux_table[] = {0, 1, 2, 3, 4}; 76 static u32 mmc_mux_table[] = {0}; 77 static u32 mmc2_mux_table[] = {0, 2}; 78 static u32 pwm_mux_table[] = {0, 1, 2, 3}; 79 80 static const struct hisi_mux_clock hi3516cv300_mux_clks[] = { 81 { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), 82 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, }, 83 { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), 84 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, }, 85 { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 86 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, }, 87 { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 88 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, }, 89 { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p), 90 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, }, 91 { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 92 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, }, 93 { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p), 94 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, }, 95 }; 96 97 static const struct hisi_gate_clock hi3516cv300_gate_clks[] = { 98 99 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT, 100 0xe4, 15, 0, }, 101 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT, 102 0xe4, 16, 0, }, 103 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT, 104 0xe4, 17, 0, }, 105 106 { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT, 107 0xe4, 13, 0, }, 108 { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT, 109 0xe4, 14, 0, }, 110 111 { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT, 112 0xc0, 1, 0, }, 113 { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT, 114 0xc4, 1, 0, }, 115 { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT, 116 0xc4, 9, 0, }, 117 { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT, 118 0xc4, 17, 0, }, 119 { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT, 120 0xc8, 1, 0, }, 121 122 { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, }, 123 124 { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, }, 125 { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT, 126 0x38, 1, 0, }, 127 128 { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, }, 129 { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0, 130 0xb8, 1, 0, }, 131 { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0, 132 0xb8, 2, 0, }, 133 { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0, 134 0xb8, 3, 0, }, 135 { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0, 136 0xb8, 4, 0, }, 137 { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, }, 138 { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, }, 139 }; 140 141 static struct hisi_clock_data *hi3516cv300_clk_register( 142 struct platform_device *pdev) 143 { 144 struct hisi_clock_data *clk_data; 145 int ret; 146 147 clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS); 148 if (!clk_data) 149 return ERR_PTR(-ENOMEM); 150 151 ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks, 152 ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); 153 if (ret) 154 return ERR_PTR(ret); 155 156 ret = hisi_clk_register_mux(hi3516cv300_mux_clks, 157 ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); 158 if (ret) 159 goto unregister_fixed_rate; 160 161 ret = hisi_clk_register_gate(hi3516cv300_gate_clks, 162 ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); 163 if (ret) 164 goto unregister_mux; 165 166 ret = of_clk_add_provider(pdev->dev.of_node, 167 of_clk_src_onecell_get, &clk_data->clk_data); 168 if (ret) 169 goto unregister_gate; 170 171 return clk_data; 172 173 unregister_gate: 174 hisi_clk_unregister_gate(hi3516cv300_gate_clks, 175 ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); 176 unregister_mux: 177 hisi_clk_unregister_mux(hi3516cv300_mux_clks, 178 ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); 179 unregister_fixed_rate: 180 hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, 181 ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); 182 return ERR_PTR(ret); 183 } 184 185 static void hi3516cv300_clk_unregister(struct platform_device *pdev) 186 { 187 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 188 189 of_clk_del_provider(pdev->dev.of_node); 190 191 hisi_clk_unregister_gate(hi3516cv300_gate_clks, 192 ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data); 193 hisi_clk_unregister_mux(hi3516cv300_mux_clks, 194 ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data); 195 hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, 196 ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data); 197 } 198 199 static const struct hisi_crg_funcs hi3516cv300_crg_funcs = { 200 .register_clks = hi3516cv300_clk_register, 201 .unregister_clks = hi3516cv300_clk_unregister, 202 }; 203 204 /* hi3516CV300 sysctrl CRG */ 205 #define HI3516CV300_SYSCTRL_NR_CLKS 16 206 207 static const char *const wdt_mux_p[] __initconst = { "3m", "apb" }; 208 static u32 wdt_mux_table[] = {0, 1}; 209 210 static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = { 211 { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p), 212 CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, }, 213 }; 214 215 static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register( 216 struct platform_device *pdev) 217 { 218 struct hisi_clock_data *clk_data; 219 int ret; 220 221 clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS); 222 if (!clk_data) 223 return ERR_PTR(-ENOMEM); 224 225 ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks, 226 ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); 227 if (ret) 228 return ERR_PTR(ret); 229 230 231 ret = of_clk_add_provider(pdev->dev.of_node, 232 of_clk_src_onecell_get, &clk_data->clk_data); 233 if (ret) 234 goto unregister_mux; 235 236 return clk_data; 237 238 unregister_mux: 239 hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, 240 ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); 241 return ERR_PTR(ret); 242 } 243 244 static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev) 245 { 246 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 247 248 of_clk_del_provider(pdev->dev.of_node); 249 250 hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, 251 ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), 252 crg->clk_data); 253 } 254 255 static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = { 256 .register_clks = hi3516cv300_sysctrl_clk_register, 257 .unregister_clks = hi3516cv300_sysctrl_clk_unregister, 258 }; 259 260 static const struct of_device_id hi3516cv300_crg_match_table[] = { 261 { 262 .compatible = "hisilicon,hi3516cv300-crg", 263 .data = &hi3516cv300_crg_funcs 264 }, 265 { 266 .compatible = "hisilicon,hi3516cv300-sysctrl", 267 .data = &hi3516cv300_sysctrl_funcs 268 }, 269 { } 270 }; 271 MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table); 272 273 static int hi3516cv300_crg_probe(struct platform_device *pdev) 274 { 275 struct hisi_crg_dev *crg; 276 277 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); 278 if (!crg) 279 return -ENOMEM; 280 281 crg->funcs = of_device_get_match_data(&pdev->dev); 282 if (!crg->funcs) 283 return -ENOENT; 284 285 crg->rstc = hisi_reset_init(pdev); 286 if (!crg->rstc) 287 return -ENOMEM; 288 289 crg->clk_data = crg->funcs->register_clks(pdev); 290 if (IS_ERR(crg->clk_data)) { 291 hisi_reset_exit(crg->rstc); 292 return PTR_ERR(crg->clk_data); 293 } 294 295 platform_set_drvdata(pdev, crg); 296 return 0; 297 } 298 299 static int hi3516cv300_crg_remove(struct platform_device *pdev) 300 { 301 struct hisi_crg_dev *crg = platform_get_drvdata(pdev); 302 303 hisi_reset_exit(crg->rstc); 304 crg->funcs->unregister_clks(pdev); 305 return 0; 306 } 307 308 static struct platform_driver hi3516cv300_crg_driver = { 309 .probe = hi3516cv300_crg_probe, 310 .remove = hi3516cv300_crg_remove, 311 .driver = { 312 .name = "hi3516cv300-crg", 313 .of_match_table = hi3516cv300_crg_match_table, 314 }, 315 }; 316 317 static int __init hi3516cv300_crg_init(void) 318 { 319 return platform_driver_register(&hi3516cv300_crg_driver); 320 } 321 core_initcall(hi3516cv300_crg_init); 322 323 static void __exit hi3516cv300_crg_exit(void) 324 { 325 platform_driver_unregister(&hi3516cv300_crg_driver); 326 } 327 module_exit(hi3516cv300_crg_exit); 328 329 MODULE_LICENSE("GPL v2"); 330 MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver"); 331