1 /* 2 * Hisilicon Hi3620 clock gate driver 3 * 4 * Copyright (c) 2012-2013 Hisilicon Limited. 5 * Copyright (c) 2012-2013 Linaro Limited. 6 * 7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 8 * Xin Li <li.xin@linaro.org> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 23 * 24 */ 25 26 #ifndef __HISI_CLK_H 27 #define __HISI_CLK_H 28 29 #include <linux/clk-provider.h> 30 #include <linux/io.h> 31 #include <linux/spinlock.h> 32 33 struct hisi_clock_data { 34 struct clk_onecell_data clk_data; 35 void __iomem *base; 36 }; 37 38 struct hisi_fixed_rate_clock { 39 unsigned int id; 40 char *name; 41 const char *parent_name; 42 unsigned long flags; 43 unsigned long fixed_rate; 44 }; 45 46 struct hisi_fixed_factor_clock { 47 unsigned int id; 48 char *name; 49 const char *parent_name; 50 unsigned long mult; 51 unsigned long div; 52 unsigned long flags; 53 }; 54 55 struct hisi_mux_clock { 56 unsigned int id; 57 const char *name; 58 const char *const *parent_names; 59 u8 num_parents; 60 unsigned long flags; 61 unsigned long offset; 62 u8 shift; 63 u8 width; 64 u8 mux_flags; 65 u32 *table; 66 const char *alias; 67 }; 68 69 struct hisi_divider_clock { 70 unsigned int id; 71 const char *name; 72 const char *parent_name; 73 unsigned long flags; 74 unsigned long offset; 75 u8 shift; 76 u8 width; 77 u8 div_flags; 78 struct clk_div_table *table; 79 const char *alias; 80 }; 81 82 struct hi6220_divider_clock { 83 unsigned int id; 84 const char *name; 85 const char *parent_name; 86 unsigned long flags; 87 unsigned long offset; 88 u8 shift; 89 u8 width; 90 u32 mask_bit; 91 const char *alias; 92 }; 93 94 struct hisi_gate_clock { 95 unsigned int id; 96 const char *name; 97 const char *parent_name; 98 unsigned long flags; 99 unsigned long offset; 100 u8 bit_idx; 101 u8 gate_flags; 102 const char *alias; 103 }; 104 105 struct clk *hisi_register_clkgate_sep(struct device *, const char *, 106 const char *, unsigned long, 107 void __iomem *, u8, 108 u8, spinlock_t *); 109 struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, 110 const char *parent_name, unsigned long flags, void __iomem *reg, 111 u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); 112 113 struct hisi_clock_data *hisi_clk_init(struct device_node *, int); 114 void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, 115 int, struct hisi_clock_data *); 116 void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, 117 int, struct hisi_clock_data *); 118 void hisi_clk_register_mux(const struct hisi_mux_clock *, int, 119 struct hisi_clock_data *); 120 void hisi_clk_register_divider(const struct hisi_divider_clock *, 121 int, struct hisi_clock_data *); 122 void hisi_clk_register_gate(const struct hisi_gate_clock *, 123 int, struct hisi_clock_data *); 124 void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, 125 int, struct hisi_clock_data *); 126 void hi6220_clk_register_divider(const struct hi6220_divider_clock *, 127 int, struct hisi_clock_data *); 128 #endif /* __HISI_CLK_H */ 129