1 /*
2  * Copyright (c) 2014 Linaro Ltd.
3  * Copyright (c) 2014 Hisilicon Limited.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  */
9 
10 #include <linux/of_address.h>
11 #include <dt-bindings/clock/hix5hd2-clock.h>
12 #include "clk.h"
13 
14 static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
15 	{ HIX5HD2_FIXED_1200M, "1200m", NULL, CLK_IS_ROOT, 1200000000, },
16 	{ HIX5HD2_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
17 	{ HIX5HD2_FIXED_48M, "48m", NULL, CLK_IS_ROOT, 48000000, },
18 	{ HIX5HD2_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
19 	{ HIX5HD2_FIXED_600M, "600m", NULL, CLK_IS_ROOT, 600000000, },
20 	{ HIX5HD2_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
21 	{ HIX5HD2_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
22 	{ HIX5HD2_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
23 	{ HIX5HD2_FIXED_100M, "100m", NULL, CLK_IS_ROOT, 100000000, },
24 	{ HIX5HD2_FIXED_40M, "40m", NULL, CLK_IS_ROOT, 40000000, },
25 	{ HIX5HD2_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
26 	{ HIX5HD2_FIXED_1728M, "1728m", NULL, CLK_IS_ROOT, 1728000000, },
27 	{ HIX5HD2_FIXED_28P8M, "28p8m", NULL, CLK_IS_ROOT, 28000000, },
28 	{ HIX5HD2_FIXED_432M, "432m", NULL, CLK_IS_ROOT, 432000000, },
29 	{ HIX5HD2_FIXED_345P6M, "345p6m", NULL, CLK_IS_ROOT, 345000000, },
30 	{ HIX5HD2_FIXED_288M, "288m", NULL, CLK_IS_ROOT, 288000000, },
31 	{ HIX5HD2_FIXED_60M,	"60m", NULL, CLK_IS_ROOT, 60000000, },
32 	{ HIX5HD2_FIXED_750M, "750m", NULL, CLK_IS_ROOT, 750000000, },
33 	{ HIX5HD2_FIXED_500M, "500m", NULL, CLK_IS_ROOT, 500000000, },
34 	{ HIX5HD2_FIXED_54M,	"54m", NULL, CLK_IS_ROOT, 54000000, },
35 	{ HIX5HD2_FIXED_27M, "27m", NULL, CLK_IS_ROOT, 27000000, },
36 	{ HIX5HD2_FIXED_1500M, "1500m", NULL, CLK_IS_ROOT, 1500000000, },
37 	{ HIX5HD2_FIXED_375M, "375m", NULL, CLK_IS_ROOT, 375000000, },
38 	{ HIX5HD2_FIXED_187M, "187m", NULL, CLK_IS_ROOT, 187000000, },
39 	{ HIX5HD2_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
40 	{ HIX5HD2_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
41 	{ HIX5HD2_FIXED_2P02M, "2m", NULL, CLK_IS_ROOT, 2000000, },
42 	{ HIX5HD2_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
43 	{ HIX5HD2_FIXED_25M, "25m", NULL, CLK_IS_ROOT, 25000000, },
44 	{ HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },
45 };
46 
47 static const char *sfc_mux_p[] __initconst = {
48 		"24m", "150m", "200m", "100m", "75m", };
49 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
50 
51 static const char *sdio1_mux_p[] __initconst = {
52 		"75m", "100m", "50m", "15m", };
53 static u32 sdio1_mux_table[] = {0, 1, 2, 3};
54 
55 static const char *fephy_mux_p[] __initconst = { "25m", "125m"};
56 static u32 fephy_mux_table[] = {0, 1};
57 
58 
59 static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
60 	{ HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
61 		CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 	{ HIX5HD2_MMC_MUX, "mmc_mux", sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p),
63 		CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio1_mux_table, },
64 	{ HIX5HD2_FEPHY_MUX, "fephy_mux",
65 		fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
66 		CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
67 };
68 
69 static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
70 	/*sfc*/
71 	{ HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
72 		CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
73 	{ HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
74 		CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
75 	/*sdio1*/
76 	{ HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
77 		CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
78 	{ HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
79 		CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
80 	{ HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
81 		CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
82 };
83 
84 static void __init hix5hd2_clk_init(struct device_node *np)
85 {
86 	struct hisi_clock_data *clk_data;
87 
88 	clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
89 	if (!clk_data)
90 		return;
91 
92 	hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
93 				     ARRAY_SIZE(hix5hd2_fixed_rate_clks),
94 				     clk_data);
95 	hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
96 					clk_data);
97 	hisi_clk_register_gate(hix5hd2_gate_clks,
98 			ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
99 }
100 
101 CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
102