1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
4  * Author: chenjun <chenjun14@huawei.com>
5  *
6  * Copyright (c) 2018, Linaro Ltd.
7  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8  */
9 
10 #include <dt-bindings/clock/hi3670-clock.h>
11 #include <linux/clk-provider.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include "clk.h"
15 
16 static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
17 	{ HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
18 	{ HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
19 	{ HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
20 	{ HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
21 	{ HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
22 	{ HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
23 	{ HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
24 	{ HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
25 	{ HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
26 	{ HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
27 	{ HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
28 	{ HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
29 	{ HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
30 	{ HI3670_PCLK, "pclk", NULL, 0, 20000000, },
31 	{ HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
32 	{ HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
33 	{ HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
34 	{ HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
35 	{ HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
36 	{ HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
37 };
38 
39 /* crgctrl */
40 static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = {
41 	{ HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus",
42 	  1, 7, 0, },
43 	{ HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys",
44 	  1, 6, 0, },
45 	{ HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt",
46 	  1, 6, 0, },
47 	{ HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt",
48 	  1, 6, 0, },
49 	{ HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt",
50 	  1, 4, 0, },
51 	{ HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt",
52 	  1, 5, 0, },
53 	{ HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl",
54 	  1, 1, 0, },
55 	{ HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0",
56 	  1, 1, 0, },
57 	{ HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0",
58 	  1, 60, 0, },
59 	{ HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en",
60 	  1, 1, 0, },
61 	{ HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys",
62 	  1, 1, 0, },
63 	{ HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold",
64 	  1, 1, 0, },
65 	{ HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle",
66 	  1, 1, 0, },
67 	{ HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold",
68 	  1, 1, 0, },
69 	{ HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold",
70 	  1, 1, 0, },
71 	{ HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold",
72 	  1, 1, 0, },
73 	{ HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
74 	  1, 10, 0, },
75 	{ HI3670_CLK_FACTOR_RXDPHY, "clk_factor_rxdphy", "clk_andgt_rxdphy",
76 	  1, 6, 0, },
77 };
78 
79 static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
80 	{ HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1",
81 	  CLK_SET_RATE_PARENT, 0x0, 0, 0, },
82 	{ HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2",
83 	  CLK_SET_RATE_PARENT, 0x0, 3, 0, },
84 	{ HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3",
85 	  CLK_SET_RATE_PARENT, 0x0, 27, 0, },
86 	{ HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1",
87 	  CLK_SET_RATE_PARENT, 0x460, 16, 0, },
88 	{ HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2",
89 	  CLK_SET_RATE_PARENT, 0x460, 18, 0, },
90 	{ HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3",
91 	  CLK_SET_RATE_PARENT, 0x460, 20, 0, },
92 	{ HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2",
93 	  CLK_SET_RATE_PARENT, 0x410, 27, 0, },
94 	{ HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3",
95 	  CLK_SET_RATE_PARENT, 0x410, 28, 0, },
96 	{ HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4",
97 	  CLK_SET_RATE_PARENT, 0x410, 26, 0, },
98 	{ HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6",
99 	  CLK_SET_RATE_PARENT, 0x410, 30, 0, },
100 	{ HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7",
101 	  CLK_SET_RATE_PARENT, 0x410, 29, 0, },
102 	{ HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
103 	  CLK_SET_RATE_PARENT, 0x10, 0, 0, },
104 	{ HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
105 	  CLK_SET_RATE_PARENT, 0x10, 1, 0, },
106 	{ HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
107 	  CLK_SET_RATE_PARENT, 0x10, 2, 0, },
108 	{ HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
109 	  CLK_SET_RATE_PARENT, 0x10, 3, 0, },
110 	{ HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
111 	  CLK_SET_RATE_PARENT, 0x10, 4, 0, },
112 	{ HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
113 	  CLK_SET_RATE_PARENT, 0x10, 5, 0, },
114 	{ HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
115 	  CLK_SET_RATE_PARENT, 0x10, 6, 0, },
116 	{ HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
117 	  CLK_SET_RATE_PARENT, 0x10, 7, 0, },
118 	{ HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
119 	  CLK_SET_RATE_PARENT, 0x10, 8, 0, },
120 	{ HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
121 	  CLK_SET_RATE_PARENT, 0x10, 9, 0, },
122 	{ HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
123 	  CLK_SET_RATE_PARENT, 0x10, 10, 0, },
124 	{ HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
125 	  CLK_SET_RATE_PARENT, 0x10, 11, 0, },
126 	{ HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
127 	  CLK_SET_RATE_PARENT, 0x10, 12, 0, },
128 	{ HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
129 	  CLK_SET_RATE_PARENT, 0x10, 13, 0, },
130 	{ HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
131 	  CLK_SET_RATE_PARENT, 0x10, 14, 0, },
132 	{ HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
133 	  CLK_SET_RATE_PARENT, 0x10, 15, 0, },
134 	{ HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
135 	  CLK_SET_RATE_PARENT, 0x10, 16, 0, },
136 	{ HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
137 	  CLK_SET_RATE_PARENT, 0x10, 17, 0, },
138 	{ HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
139 	  CLK_SET_RATE_PARENT, 0x10, 20, 0, },
140 	{ HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
141 	  CLK_SET_RATE_PARENT, 0x10, 21, 0, },
142 	{ HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
143 	  CLK_SET_RATE_PARENT, 0x50, 28, 0, },
144 	{ HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
145 	  CLK_SET_RATE_PARENT, 0x50, 29, 0, },
146 	{ HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus",
147 	  CLK_SET_RATE_PARENT, 0x0, 25, 0, },
148 	{ HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus",
149 	  CLK_SET_RATE_PARENT, 0x40, 1, 0, },
150 	{ HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus",
151 	  CLK_SET_RATE_PARENT, 0x0, 21, 0, },
152 	{ HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
153 	  CLK_SET_RATE_PARENT, 0x420, 7, 0, },
154 	{ HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie",
155 	  CLK_SET_RATE_PARENT, 0x420, 9, 0, },
156 	{ HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie",
157 	  CLK_SET_RATE_PARENT, 0x30, 12, 0, },
158 	{ HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus",
159 	  CLK_SET_RATE_PARENT, 0x40, 13, 0, },
160 	{ HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus",
161 	  CLK_SET_RATE_PARENT, 0x420, 21, 0, },
162 	{ HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
163 	  CLK_SET_RATE_PARENT, 0x30, 1, 0, },
164 	{ HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus",
165 	  CLK_SET_RATE_PARENT, 0x0, 5, 0, },
166 	{ HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq",
167 	  CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
168 	{ HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq",
169 	  CLK_SET_RATE_PARENT, 0x50, 14, 0, },
170 	{ HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
171 	  CLK_SET_RATE_PARENT, 0x40, 17, 0, },
172 	{ HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
173 	  CLK_SET_RATE_PARENT, 0x0, 30, 0, },
174 	{ HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys",
175 	  CLK_SET_RATE_PARENT, 0x40, 19, 0, },
176 	{ HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm",
177 	  CLK_SET_RATE_PARENT, 0x050, 9, 0, },
178 	{ HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm",
179 	  CLK_SET_RATE_PARENT, 0x050, 13, 0, },
180 	{ HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm",
181 	  CLK_SET_RATE_PARENT, 0x480, 10, 0, },
182 	{ HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm",
183 	  CLK_SET_RATE_PARENT, 0x480, 9, 0, },
184 	{ HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm",
185 	  CLK_SET_RATE_PARENT, 0x480, 15, 0, },
186 	{ HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm",
187 	  CLK_SET_RATE_PARENT, 0x050, 15, 0, },
188 	{ HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm",
189 	  CLK_SET_RATE_PARENT, 0x050, 12, 0, },
190 	{ HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm",
191 	  CLK_SET_RATE_PARENT, 0x050, 11, 0, },
192 	{ HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
193 	  CLK_SET_RATE_PARENT, 0x20, 11, 0, },
194 	{ HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
195 	  CLK_SET_RATE_PARENT, 0x20, 14, 0, },
196 	{ HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth",
197 	  CLK_SET_RATE_PARENT, 0x20, 11, 0, },
198 	{ HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth",
199 	  CLK_SET_RATE_PARENT, 0x20, 14, 0, },
200 	{ HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl",
201 	  CLK_SET_RATE_PARENT, 0x20, 12, 0, },
202 	{ HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl",
203 	  CLK_SET_RATE_PARENT, 0x20, 15, 0, },
204 	{ HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl",
205 	  CLK_SET_RATE_PARENT, 0x20, 12, 0, },
206 	{ HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl",
207 	  CLK_SET_RATE_PARENT, 0x20, 15, 0, },
208 	{ HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0",
209 	  CLK_SET_RATE_PARENT, 0x20, 10, 0, },
210 	{ HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
211 	  CLK_SET_RATE_PARENT, 0x20, 7, 0, },
212 	{ HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
213 	  CLK_SET_RATE_PARENT, 0x20, 27, 0, },
214 	{ HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
215 	  CLK_SET_RATE_PARENT, 0x10, 31, 0, },
216 	{ HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c",
217 	  CLK_SET_RATE_PARENT, 0x20, 7, 0, },
218 	{ HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c",
219 	  CLK_SET_RATE_PARENT, 0x20, 27, 0, },
220 	{ HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c",
221 	  CLK_SET_RATE_PARENT, 0x10, 31, 0, },
222 	{ HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
223 	  CLK_SET_RATE_PARENT, 0x20, 9, 0, },
224 	{ HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
225 	  CLK_SET_RATE_PARENT, 0x40, 4, 0, },
226 	{ HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi",
227 	  CLK_SET_RATE_PARENT, 0x20, 9, 0, },
228 	{ HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi",
229 	  CLK_SET_RATE_PARENT, 0x40, 4, 0, },
230 	{ HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys",
231 	  CLK_SET_RATE_PARENT, 0x40, 0, 0, },
232 	{ HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys",
233 	  CLK_SET_RATE_PARENT, 0x410, 19, 0, },
234 	{ HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
235 	  CLK_SET_RATE_PARENT, 0x420, 8, 0, },
236 	{ HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi",
237 	  CLK_SET_RATE_PARENT, 0x420, 5, 0, },
238 	{ HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi",
239 	  CLK_SET_RATE_PARENT, 0x050, 4, 0, },
240 	{ HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie",
241 	  CLK_SET_RATE_PARENT, 0x470, 14, 0, },
242 	{ HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie",
243 	  CLK_SET_RATE_PARENT, 0x470, 12, 0, },
244 	{ HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie",
245 	  CLK_SET_RATE_PARENT, 0x470, 13, 0, },
246 	{ HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie",
247 	  CLK_SET_RATE_PARENT, 0x470, 15, 0, },
248 	{ HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp",
249 	  CLK_SET_RATE_PARENT, 0x0, 26, 0, },
250 	{ HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp",
251 	  CLK_SET_RATE_PARENT, 0x20, 31, 0, },
252 	{ HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans",
253 	  CLK_SET_RATE_PARENT, 0x30, 24, 0, },
254 	{ HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans",
255 	  CLK_SET_RATE_PARENT, 0x30, 25, 0, },
256 	{ HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp",
257 	  CLK_SET_RATE_PARENT, 0x20, 0, 0, },
258 	{ HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192",
259 	  CLK_SET_RATE_PARENT, 0x30, 8, 0, },
260 	{ HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192",
261 	  CLK_SET_RATE_PARENT, 0x30, 9, 0, },
262 	{ HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0",
263 	  CLK_SET_RATE_PARENT, 0x30, 19, 0, },
264 	{ HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1",
265 	  CLK_SET_RATE_PARENT, 0x40, 20, 0, },
266 	{ HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao",
267 	  CLK_SET_RATE_PARENT, 0x00, 13, 0, },
268 	{ HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
269 	  CLK_SET_RATE_PARENT, 0, 1, 0, },
270 	{ HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys",
271 	  CLK_SET_RATE_PARENT, 0, 1, 0, },
272 	{ HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0",
273 	  CLK_SET_RATE_PARENT, 0x50, 16, 0, },
274 	{ HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1",
275 	  CLK_SET_RATE_PARENT, 0x50, 17, 0, },
276 	{ HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2",
277 	  CLK_SET_RATE_PARENT, 0x50, 18, 0, },
278 	{ HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg",
279 	  CLK_SET_RATE_PARENT, 0x030, 20, 0, },
280 	{ HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg",
281 	  CLK_SET_RATE_PARENT, 0x030, 21, 0, },
282 	{ HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg",
283 	  CLK_SET_RATE_PARENT, 0x030, 22, 0, },
284 	{ HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
285 	  CLK_SET_RATE_PARENT, 0x030, 28, 0, },
286 	{ HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
287 	  CLK_SET_RATE_PARENT, 0x030, 29, 0, },
288 	{ HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
289 	  CLK_SET_RATE_PARENT, 0x030, 30, 0, },
290 	{ HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
291 	  CLK_SET_RATE_PARENT, 0x030, 31, 0, },
292 	{ HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys",
293 	  CLK_SET_RATE_PARENT, 0x40, 6, 0, },
294 };
295 
296 static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
297 	{ HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
298 	  CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
299 	{ HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
300 	  CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
301 	{ HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m",
302 	  CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, },
303 	{ HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus",
304 	  CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, },
305 	{ HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
306 	  CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, },
307 	{ HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys",
308 	  CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, },
309 	{ HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
310 	  CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, },
311 	{ HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys",
312 	  CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, },
313 	{ HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
314 	  CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, },
315 	{ HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
316 	  CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, },
317 	{ HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
318 	  CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, },
319 	{ HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m",
320 	  CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, },
321 	{ HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
322 	  CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, },
323 	{ HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
324 	  CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, },
325 	{ HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi",
326 	  CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, },
327 	{ HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp",
328 	  CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, },
329 	{ HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2",
330 	  CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, },
331 	{ HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
332 	  CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
333 	{ HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
334 	  CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
335 	{ HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
336 	  CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
337 	{ HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
338 	  CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
339 	{ HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
340 	  CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, },
341 	{ HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
342 	  CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, },
343 	{ HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
344 	  CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, },
345 	{ HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm",
346 	  CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
347 	{ HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm",
348 	  CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, },
349 	{ HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics",
350 	  CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, },
351 	{ HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus",
352 	  CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, },
353 };
354 
355 static const char *const
356 clk_mux_sysbus_p[] = { "clk_ppll1", "clk_ppll0", };
357 static const char *const
358 clk_mux_vcodecbus_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0",
359 			  "clk_invalid", "clk_ppll2", "clk_invalid",
360 			  "clk_invalid", "clk_invalid", "clk_ppll3",
361 			  "clk_invalid", "clk_invalid", "clk_invalid",
362 			  "clk_invalid", "clk_invalid", "clk_invalid",
363 			  "clk_invalid", };
364 static const char *const
365 clk_mux_sd_sys_p[] = { "clk_sd_sys", "clk_div_sd", };
366 static const char *const
367 clk_mux_sd_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
368 static const char *const
369 clk_mux_sdio_sys_p[] = { "clk_sdio_sys", "clk_div_sdio", };
370 static const char *const
371 clk_mux_sdio_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
372 static const char *const
373 clk_mux_a53hpm_p[] = { "clk_ppll0", "clk_ppll2", };
374 static const char *const
375 clk_mux_320m_p[] = { "clk_ppll2", "clk_ppll0", };
376 static const char *const
377 clk_mux_uarth_p[] = { "clkin_sys", "clk_div_uarth", };
378 static const char *const
379 clk_mux_uartl_p[] = { "clkin_sys", "clk_div_uartl", };
380 static const char *const
381 clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", };
382 static const char *const
383 clk_mux_i2c_p[] = { "clkin_sys", "clk_div_i2c", };
384 static const char *const
385 clk_mux_spi_p[] = { "clkin_sys", "clk_div_spi", };
386 static const char *const
387 clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", };
388 static const char *const
389 clk_mux_ao_asp_p[] = { "clk_ppll2", "clk_ppll3", };
390 static const char *const
391 clk_mux_vdec_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
392 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
393 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
394 		     "clk_invalid", "clk_invalid", "clk_invalid",
395 		     "clk_invalid", };
396 static const char *const
397 clk_mux_venc_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
398 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
399 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
400 		     "clk_invalid", "clk_invalid", "clk_invalid",
401 		     "clk_invalid", };
402 static const char *const
403 clk_isp_snclk_mux0_p[] = { "clkin_sys", "clk_isp_snclk_div0", };
404 static const char *const
405 clk_isp_snclk_mux1_p[] = { "clkin_sys", "clk_isp_snclk_div1", };
406 static const char *const
407 clk_isp_snclk_mux2_p[] = { "clkin_sys", "clk_isp_snclk_div2", };
408 static const char *const
409 clk_mux_rxdphy_cfg_p[] = { "clk_factor_rxdphy", "clkin_sys", };
410 static const char *const
411 clk_mux_ics_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
412 		    "clk_ppll2", "clk_invalid", "clk_invalid", "clk_invalid",
413 		    "clk_ppll3", "clk_invalid", "clk_invalid", "clk_invalid",
414 		    "clk_invalid", "clk_invalid", "clk_invalid",
415 		    "clk_invalid", };
416 
417 static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = {
418 	{ HI3670_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
419 	  ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT,
420 	  0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
421 	{ HI3670_CLK_MUX_VCODECBUS, "clk_mux_vcodecbus", clk_mux_vcodecbus_p,
422 	  ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT,
423 	  0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
424 	{ HI3670_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
425 	  ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT,
426 	  0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
427 	{ HI3670_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_sd_pll_p,
428 	  ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT,
429 	  0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
430 	{ HI3670_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
431 	  ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT,
432 	  0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
433 	{ HI3670_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_sdio_pll_p,
434 	  ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT,
435 	  0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
436 	{ HI3670_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_a53hpm_p,
437 	  ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT,
438 	  0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
439 	{ HI3670_CLK_MUX_320M, "clk_mux_320m", clk_mux_320m_p,
440 	  ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT,
441 	  0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
442 	{ HI3670_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
443 	  ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT,
444 	  0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
445 	{ HI3670_CLK_MUX_UARTL, "clk_mux_uartl", clk_mux_uartl_p,
446 	  ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT,
447 	  0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
448 	{ HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
449 	  ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,
450 	  0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
451 	{ HI3670_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
452 	  ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT,
453 	  0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },
454 	{ HI3670_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
455 	  ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT,
456 	  0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
457 	{ HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,
458 	  ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,
459 	  0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
460 	{ HI3670_CLK_MUX_AO_ASP, "clk_mux_ao_asp", clk_mux_ao_asp_p,
461 	  ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT,
462 	  0x100, 6, 1, CLK_MUX_HIWORD_MASK, },
463 	{ HI3670_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_vdec_p,
464 	  ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT,
465 	  0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
466 	{ HI3670_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
467 	  ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT,
468 	  0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
469 	{ HI3670_CLK_ISP_SNCLK_MUX0, "clk_isp_snclk_mux0", clk_isp_snclk_mux0_p,
470 	  ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT,
471 	  0x108, 3, 1, CLK_MUX_HIWORD_MASK, },
472 	{ HI3670_CLK_ISP_SNCLK_MUX1, "clk_isp_snclk_mux1", clk_isp_snclk_mux1_p,
473 	  ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT,
474 	  0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },
475 	{ HI3670_CLK_ISP_SNCLK_MUX2, "clk_isp_snclk_mux2", clk_isp_snclk_mux2_p,
476 	  ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT,
477 	  0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },
478 	{ HI3670_CLK_MUX_RXDPHY_CFG, "clk_mux_rxdphy_cfg", clk_mux_rxdphy_cfg_p,
479 	  ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT,
480 	  0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },
481 	{ HI3670_CLK_MUX_ICS, "clk_mux_ics", clk_mux_ics_p,
482 	  ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT,
483 	  0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },
484 };
485 
486 static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = {
487 	{ HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
488 	  CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
489 	{ HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
490 	  CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
491 	{ HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
492 	  CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
493 	{ HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie",
494 	  CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
495 	{ HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt",
496 	  CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
497 	{ HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
498 	  CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
499 	{ HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
500 	  CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
501 	{ HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
502 	  CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
503 	{ HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl",
504 	  CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
505 	{ HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
506 	  CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
507 	{ HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
508 	  CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
509 	{ HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
510 	  CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
511 	{ HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi",
512 	  CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
513 	{ HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt",
514 	  CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
515 	{ HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans",
516 	  CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
517 	{ HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans",
518 	  CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, },
519 	{ HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp",
520 	  CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
521 	{ HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0",
522 	  CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, },
523 	{ HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1",
524 	  CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
525 	{ HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao",
526 	  CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
527 	{ HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
528 	  CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
529 	{ HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
530 	  CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
531 	{ HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac",
532 	  CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
533 	{ HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac",
534 	  CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, },
535 	{ HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac",
536 	  CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, },
537 	{ HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics",
538 	  CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, },
539 };
540 
541 /* clk_pmuctrl */
542 static const struct hisi_gate_clock hi3670_pmu_gate_clks[] = {
543 	{ HI3670_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
544 	  CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, },
545 };
546 
547 /* clk_pctrl */
548 static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = {
549 	{ HI3670_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en", "clk_gate_abb_192",
550 	  CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, },
551 	{ HI3670_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
552 	  CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
553 };
554 
555 /* clk_sctrl */
556 static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
557 	{ HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0",
558 	  CLK_SET_RATE_PARENT, 0x190, 26, 0, },
559 	{ HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0",
560 	  CLK_SET_RATE_PARENT, 0x190, 15, 0, },
561 	{ HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0",
562 	  CLK_SET_RATE_PARENT, 0x1b0, 6, 0, },
563 	{ HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus",
564 	  CLK_SET_RATE_PARENT, 0x1B0, 9, 0, },
565 	{ HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus",
566 	  CLK_SET_RATE_PARENT, 0x1B0, 8, 0, },
567 	{ HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi",
568 	  CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
569 	{ HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi",
570 	  CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
571 	{ HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys",
572 	  CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
573 	{ HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys",
574 	  CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
575 	{ HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
576 	  CLK_SET_RATE_PARENT, 0x160, 11, 0, },
577 	{ HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
578 	  CLK_SET_RATE_PARENT, 0x160, 12, 0, },
579 	{ HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
580 	  CLK_SET_RATE_PARENT, 0x160, 13, 0, },
581 	{ HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
582 	  CLK_SET_RATE_PARENT, 0x160, 14, 0, },
583 	{ HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
584 	  CLK_SET_RATE_PARENT, 0x160, 21, 0, },
585 	{ HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
586 	  CLK_SET_RATE_PARENT, 0x160, 22, 0, },
587 	{ HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
588 	  CLK_SET_RATE_PARENT, 0x160, 25, 0, },
589 	{ HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0",
590 	  CLK_SET_RATE_PARENT, 0x160, 16, 0, },
591 	{ HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1",
592 	  CLK_SET_RATE_PARENT, 0x160, 17, 0, },
593 	{ HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus",
594 	  CLK_SET_RATE_PARENT, 0x160, 19, 0, },
595 	{ HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys",
596 	  CLK_SET_RATE_PARENT, 0x160, 20, 0, },
597 	{ HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri",
598 	  "clk_mux_asp_subsys_peri",
599 	  CLK_SET_RATE_PARENT, 0x170, 6, 0, },
600 	{ HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll",
601 	  CLK_SET_RATE_PARENT, 0x170, 4, 0, },
602 	{ HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys",
603 	  CLK_SET_RATE_PARENT, 0x160, 27, 0, },
604 	{ HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll",
605 	  "clk_gate_dp_audio_pll_ao",
606 	  CLK_SET_RATE_PARENT, 0x1B0, 7, 0, },
607 };
608 
609 static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = {
610 	{ HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0",
611 	  CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, },
612 	{ HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri",
613 	  "clk_ppll0",
614 	  CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, },
615 	{ HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0",
616 	  CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, },
617 };
618 
619 static const char *const
620 clk_mux_ufs_subsys_p[] = { "clkin_sys", "clk_ppll0", };
621 static const char *const
622 clk_mux_clkout0_p[] = { "clkin_ref", "clk_div_clkout0_tcxo",
623 			"clk_div_clkout0_pll", "clk_div_clkout0_pll", };
624 static const char *const
625 clk_mux_clkout1_p[] = { "clkin_ref", "clk_div_clkout1_tcxo",
626 			"clk_div_clkout1_pll", "clk_div_clkout1_pll", };
627 static const char *const
628 clk_mux_asp_subsys_peri_p[] = { "clk_ppll0", "clk_fll_src", };
629 static const char *const
630 clk_mux_asp_pll_p[] = { "clk_ppll0", "clk_fll_src", "clk_gate_ao_asp",
631 			"clk_pciepll_rev", };
632 
633 static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = {
634 	{ HI3670_CLK_MUX_UFS_SUBSYS, "clk_mux_ufs_subsys", clk_mux_ufs_subsys_p,
635 	  ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT,
636 	  0x274, 8, 1, CLK_MUX_HIWORD_MASK, },
637 	{ HI3670_CLK_MUX_CLKOUT0, "clk_mux_clkout0", clk_mux_clkout0_p,
638 	  ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT,
639 	  0x254, 12, 2, CLK_MUX_HIWORD_MASK, },
640 	{ HI3670_CLK_MUX_CLKOUT1, "clk_mux_clkout1", clk_mux_clkout1_p,
641 	  ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT,
642 	  0x254, 14, 2, CLK_MUX_HIWORD_MASK, },
643 	{ HI3670_CLK_MUX_ASP_SUBSYS_PERI, "clk_mux_asp_subsys_peri",
644 	  clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p),
645 	  CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },
646 	{ HI3670_CLK_MUX_ASP_PLL, "clk_mux_asp_pll", clk_mux_asp_pll_p,
647 	  ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT,
648 	  0x268, 9, 2, CLK_MUX_HIWORD_MASK, },
649 };
650 
651 static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = {
652 	{ HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
653 	  CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
654 	{ HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys",
655 	  CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
656 	{ HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi",
657 	  CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
658 	{ HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys",
659 	  CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, },
660 	{ HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys",
661 	  CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, },
662 	{ HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri",
663 	  CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
664 	{ HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys",
665 	  CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
666 };
667 
668 /* clk_iomcu */
669 static const struct hisi_fixed_factor_clock hi3670_iomcu_fixed_factor_clks[] = {
670 	{ HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, },
671 	{ HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, },
672 	{ HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, },
673 	{ HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, },
674 	{ HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, },
675 	{ HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, },
676 };
677 
678 static const struct hisi_gate_clock hi3670_iomcu_gate_sep_clks[] = {
679 	{ HI3670_CLK_I2C0_GATE_IOMCU, "clk_i2c0_gate_iomcu", "clk_fll_src",
680 	  CLK_SET_RATE_PARENT, 0x10, 3, 0, },
681 	{ HI3670_CLK_I2C1_GATE_IOMCU, "clk_i2c1_gate_iomcu", "clk_fll_src",
682 	  CLK_SET_RATE_PARENT, 0x10, 4, 0, },
683 	{ HI3670_CLK_I2C2_GATE_IOMCU, "clk_i2c2_gate_iomcu", "clk_fll_src",
684 	  CLK_SET_RATE_PARENT, 0x10, 5, 0, },
685 	{ HI3670_CLK_SPI0_GATE_IOMCU, "clk_spi0_gate_iomcu", "clk_fll_src",
686 	  CLK_SET_RATE_PARENT, 0x10, 10, 0, },
687 	{ HI3670_CLK_SPI2_GATE_IOMCU, "clk_spi2_gate_iomcu", "clk_fll_src",
688 	  CLK_SET_RATE_PARENT, 0x10, 30, 0, },
689 	{ HI3670_CLK_UART3_GATE_IOMCU, "clk_uart3_gate_iomcu", "clk_gate_iomcu_peri0",
690 	  CLK_SET_RATE_PARENT, 0x10, 11, 0, },
691 	{ HI3670_CLK_GATE_PERI0_IOMCU, "clk_gate_iomcu_peri0", "clk_ppll0",
692 	  CLK_SET_RATE_PARENT, 0x90, 0, 0, },
693 };
694 
695 /* clk_media1 */
696 static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
697 	{ HI3670_ACLK_GATE_NOC_DSS, "aclk_gate_noc_dss", "aclk_gate_disp_noc_subsys",
698 	  CLK_SET_RATE_PARENT, 0x10, 21, 0, },
699 	{ HI3670_PCLK_GATE_NOC_DSS_CFG, "pclk_gate_noc_dss_cfg", "pclk_gate_disp_noc_subsys",
700 	  CLK_SET_RATE_PARENT, 0x10, 22, 0, },
701 	{ HI3670_PCLK_GATE_MMBUF_CFG, "pclk_gate_mmbuf_cfg", "pclk_gate_disp_noc_subsys",
702 	  CLK_SET_RATE_PARENT, 0x20, 5, 0, },
703 	{ HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus",
704 	  CLK_SET_RATE_PARENT, 0x10, 18, 0, },
705 	{ HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq",
706 	  CLK_SET_RATE_PARENT, 0x10, 17, 0, },
707 	{ HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys",
708 	  CLK_SET_RATE_PARENT, 0x00, 14, 0, },
709 	{ HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys",
710 	  CLK_SET_RATE_PARENT, 0x00, 19, 0, },
711 	{ HI3670_CLK_GATE_VIVOBUSFREQ, "clk_gate_vivobusfreq", "clk_div_vivobus",
712 	  CLK_SET_RATE_PARENT, 0x00, 18, 0, },
713 	{ HI3670_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
714 	  CLK_SET_RATE_PARENT, 0x00, 15, 0, },
715 	{ HI3670_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
716 	  CLK_SET_RATE_PARENT, 0x00, 16, 0, },
717 	{ HI3670_CLK_GATE_LDI1FREQ, "clk_gate_ldi1freq", "clk_div_ldi1",
718 	  CLK_SET_RATE_PARENT, 0x00, 17, 0, },
719 	{ HI3670_CLK_GATE_BRG, "clk_gate_brg", "clk_media_common_div",
720 	  CLK_SET_RATE_PARENT, 0x00, 29, 0, },
721 	{ HI3670_ACLK_GATE_ASC, "aclk_gate_asc", "clk_gate_mmbuf",
722 	  CLK_SET_RATE_PARENT, 0x20, 3, 0, },
723 	{ HI3670_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "clk_gate_mmbuf",
724 	  CLK_SET_RATE_PARENT, 0x20, 4, 0, },
725 	{ HI3670_CLK_GATE_MMBUF, "clk_gate_mmbuf", "aclk_div_mmbuf",
726 	  CLK_SET_RATE_PARENT, 0x20, 0, 0, },
727 	{ HI3670_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
728 	  CLK_SET_RATE_PARENT, 0x20, 1, 0, },
729 	{ HI3670_CLK_GATE_ATDIV_VIVO, "clk_gate_atdiv_vivo", "clk_div_vivobus",
730 	  CLK_SET_RATE_PARENT, 0x010, 1, 0, },
731 };
732 
733 static const struct hisi_gate_clock hi3670_media1_gate_clks[] = {
734 	{ HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus",
735 	  CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, },
736 	{ HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
737 	  CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, },
738 	{ HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
739 	  CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, },
740 	{ HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
741 	  CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, },
742 	{ HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf",
743 	  CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, },
744 	{ HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf",
745 	  CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, },
746 };
747 
748 static const char *const
749 clk_mux_vivobus_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
750 			"clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
751 			"clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
752 			"clk_invalid", "clk_invalid", "clk_invalid",
753 			"clk_invalid", "clk_invalid", "clk_invalid",
754 			"clk_invalid", };
755 static const char *const
756 clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
757 		     "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
758 		     "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
759 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
760 		     "clk_invalid", "clk_invalid", "clk_invalid", };
761 static const char *const
762 clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media",
763 		     "clk_gate_ppll0_media", "clk_invalid",
764 		     "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
765 		     "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
766 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
767 		     "clk_invalid", "clk_invalid", };
768 static const char *const
769 clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media",
770 		     "clk_gate_ppll0_media", "clk_invalid",
771 		     "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
772 		     "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
773 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
774 		     "clk_invalid", "clk_invalid", };
775 static const char *const
776 clk_sw_mmbuf_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
777 		     "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
778 		     "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
779 		     "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
780 		     "clk_invalid", "clk_invalid", "clk_invalid", };
781 
782 static const struct hisi_mux_clock hi3670_media1_mux_clks[] = {
783 	{ HI3670_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_vivobus_p,
784 	  ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT,
785 	  0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
786 	{ HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
787 	  ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
788 	  0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
789 	{ HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
790 	  ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
791 	  0x60, 6, 4, CLK_MUX_HIWORD_MASK, },
792 	{ HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p,
793 	  ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,
794 	  0x64, 6, 4, CLK_MUX_HIWORD_MASK, },
795 	{ HI3670_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
796 	  ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT,
797 	  0x88, 0, 4, CLK_MUX_HIWORD_MASK, },
798 };
799 
800 static const struct hisi_divider_clock hi3670_media1_divider_clks[] = {
801 	{ HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt",
802 	  CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
803 	{ HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
804 	  CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
805 	{ HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
806 	  CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
807 	{ HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
808 	  CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
809 	{ HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
810 	  CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
811 	{ HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
812 	  CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
813 };
814 
815 /* clk_media2 */
816 static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = {
817 	{ HI3670_CLK_GATE_VDECFREQ, "clk_gate_vdecfreq", "clk_div_vdec",
818 	  CLK_SET_RATE_PARENT, 0x00, 8, 0, },
819 	{ HI3670_CLK_GATE_VENCFREQ, "clk_gate_vencfreq", "clk_div_venc",
820 	  CLK_SET_RATE_PARENT, 0x00, 5, 0, },
821 	{ HI3670_CLK_GATE_ICSFREQ, "clk_gate_icsfreq", "clk_div_ics",
822 	  CLK_SET_RATE_PARENT, 0x00, 2, 0, },
823 };
824 
825 static void hi3670_clk_crgctrl_init(struct device_node *np)
826 {
827 	struct hisi_clock_data *clk_data;
828 
829 	int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
830 		 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) +
831 		 ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
832 		 ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
833 		 ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
834 		 ARRAY_SIZE(hi3670_crgctrl_divider_clks);
835 
836 	clk_data = hisi_clk_init(np, nr);
837 	if (!clk_data)
838 		return;
839 
840 	hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks,
841 				     ARRAY_SIZE(hi3670_fixed_rate_clks),
842 				     clk_data);
843 	hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks,
844 				   ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
845 				   clk_data);
846 	hisi_clk_register_gate(hi3670_crgctrl_gate_clks,
847 			       ARRAY_SIZE(hi3670_crgctrl_gate_clks),
848 			       clk_data);
849 	hisi_clk_register_mux(hi3670_crgctrl_mux_clks,
850 			      ARRAY_SIZE(hi3670_crgctrl_mux_clks),
851 			      clk_data);
852 	hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks,
853 				       ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
854 				       clk_data);
855 	hisi_clk_register_divider(hi3670_crgctrl_divider_clks,
856 				  ARRAY_SIZE(hi3670_crgctrl_divider_clks),
857 				  clk_data);
858 }
859 
860 static void hi3670_clk_pctrl_init(struct device_node *np)
861 {
862 	struct hisi_clock_data *clk_data;
863 	int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks);
864 
865 	clk_data = hisi_clk_init(np, nr);
866 	if (!clk_data)
867 		return;
868 	hisi_clk_register_gate(hi3670_pctrl_gate_clks,
869 			       ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data);
870 }
871 
872 static void hi3670_clk_pmuctrl_init(struct device_node *np)
873 {
874 	struct hisi_clock_data *clk_data;
875 	int nr = ARRAY_SIZE(hi3670_pmu_gate_clks);
876 
877 	clk_data = hisi_clk_init(np, nr);
878 	if (!clk_data)
879 		return;
880 
881 	hisi_clk_register_gate(hi3670_pmu_gate_clks,
882 			       ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data);
883 }
884 
885 static void hi3670_clk_sctrl_init(struct device_node *np)
886 {
887 	struct hisi_clock_data *clk_data;
888 	int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) +
889 		 ARRAY_SIZE(hi3670_sctrl_gate_clks) +
890 		 ARRAY_SIZE(hi3670_sctrl_mux_clks) +
891 		 ARRAY_SIZE(hi3670_sctrl_divider_clks);
892 
893 	clk_data = hisi_clk_init(np, nr);
894 	if (!clk_data)
895 		return;
896 
897 	hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks,
898 				   ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
899 				   clk_data);
900 	hisi_clk_register_gate(hi3670_sctrl_gate_clks,
901 			       ARRAY_SIZE(hi3670_sctrl_gate_clks),
902 			       clk_data);
903 	hisi_clk_register_mux(hi3670_sctrl_mux_clks,
904 			      ARRAY_SIZE(hi3670_sctrl_mux_clks),
905 			      clk_data);
906 	hisi_clk_register_divider(hi3670_sctrl_divider_clks,
907 				  ARRAY_SIZE(hi3670_sctrl_divider_clks),
908 				  clk_data);
909 }
910 
911 static void hi3670_clk_iomcu_init(struct device_node *np)
912 {
913 	struct hisi_clock_data *clk_data;
914 	int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) +
915 			ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks);
916 
917 	clk_data = hisi_clk_init(np, nr);
918 	if (!clk_data)
919 		return;
920 
921 	hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks,
922 			       ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data);
923 
924 	hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks,
925 				       ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
926 				       clk_data);
927 }
928 
929 static void hi3670_clk_media1_init(struct device_node *np)
930 {
931 	struct hisi_clock_data *clk_data;
932 
933 	int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) +
934 		 ARRAY_SIZE(hi3670_media1_gate_clks) +
935 		 ARRAY_SIZE(hi3670_media1_mux_clks) +
936 		 ARRAY_SIZE(hi3670_media1_divider_clks);
937 
938 	clk_data = hisi_clk_init(np, nr);
939 	if (!clk_data)
940 		return;
941 
942 	hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks,
943 				   ARRAY_SIZE(hi3670_media1_gate_sep_clks),
944 				   clk_data);
945 	hisi_clk_register_gate(hi3670_media1_gate_clks,
946 			       ARRAY_SIZE(hi3670_media1_gate_clks),
947 			       clk_data);
948 	hisi_clk_register_mux(hi3670_media1_mux_clks,
949 			      ARRAY_SIZE(hi3670_media1_mux_clks),
950 			      clk_data);
951 	hisi_clk_register_divider(hi3670_media1_divider_clks,
952 				  ARRAY_SIZE(hi3670_media1_divider_clks),
953 				  clk_data);
954 }
955 
956 static void hi3670_clk_media2_init(struct device_node *np)
957 {
958 	struct hisi_clock_data *clk_data;
959 
960 	int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks);
961 
962 	clk_data = hisi_clk_init(np, nr);
963 	if (!clk_data)
964 		return;
965 
966 	hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks,
967 				   ARRAY_SIZE(hi3670_media2_gate_sep_clks),
968 				   clk_data);
969 }
970 
971 static const struct of_device_id hi3670_clk_match_table[] = {
972 	{ .compatible = "hisilicon,hi3670-crgctrl",
973 	  .data = hi3670_clk_crgctrl_init },
974 	{ .compatible = "hisilicon,hi3670-pctrl",
975 	  .data = hi3670_clk_pctrl_init },
976 	{ .compatible = "hisilicon,hi3670-pmuctrl",
977 	  .data = hi3670_clk_pmuctrl_init },
978 	{ .compatible = "hisilicon,hi3670-sctrl",
979 	  .data = hi3670_clk_sctrl_init },
980 	{ .compatible = "hisilicon,hi3670-iomcu",
981 	  .data = hi3670_clk_iomcu_init },
982 	{ .compatible = "hisilicon,hi3670-media1-crg",
983 	  .data = hi3670_clk_media1_init },
984 	{ .compatible = "hisilicon,hi3670-media2-crg",
985 	  .data = hi3670_clk_media2_init },
986 	{ }
987 };
988 
989 static int hi3670_clk_probe(struct platform_device *pdev)
990 {
991 	struct device *dev = &pdev->dev;
992 	struct device_node *np = pdev->dev.of_node;
993 	void (*init_func)(struct device_node *np);
994 
995 	init_func = of_device_get_match_data(dev);
996 	if (!init_func)
997 		return -ENODEV;
998 
999 	init_func(np);
1000 
1001 	return 0;
1002 }
1003 
1004 static struct platform_driver hi3670_clk_driver = {
1005 	.probe          = hi3670_clk_probe,
1006 	.driver         = {
1007 		.name   = "hi3670-clk",
1008 		.of_match_table = hi3670_clk_match_table,
1009 	},
1010 };
1011 
1012 static int __init hi3670_clk_init(void)
1013 {
1014 	return platform_driver_register(&hi3670_clk_driver);
1015 }
1016 core_initcall(hi3670_clk_init);
1017