1 /* 2 * Hi3519 Clock Driver 3 * 4 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <dt-bindings/clock/hi3519-clock.h> 21 #include <linux/clk-provider.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include "clk.h" 25 #include "reset.h" 26 27 #define HI3519_INNER_CLK_OFFSET 64 28 #define HI3519_FIXED_24M 65 29 #define HI3519_FIXED_50M 66 30 #define HI3519_FIXED_75M 67 31 #define HI3519_FIXED_125M 68 32 #define HI3519_FIXED_150M 69 33 #define HI3519_FIXED_200M 70 34 #define HI3519_FIXED_250M 71 35 #define HI3519_FIXED_300M 72 36 #define HI3519_FIXED_400M 73 37 #define HI3519_FMC_MUX 74 38 39 #define HI3519_NR_CLKS 128 40 41 struct hi3519_crg_data { 42 struct hisi_clock_data *clk_data; 43 struct hisi_reset_controller *rstc; 44 }; 45 46 static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = { 47 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, }, 48 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, }, 49 { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, }, 50 { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, }, 51 { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, }, 52 { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, }, 53 { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, }, 54 { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, }, 55 { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, }, 56 }; 57 58 static const char *const fmc_mux_p[] = { 59 "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", }; 60 static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; 61 62 static const struct hisi_mux_clock hi3519_mux_clks[] = { 63 { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), 64 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, }, 65 }; 66 67 static const struct hisi_gate_clock hi3519_gate_clks[] = { 68 { HI3519_FMC_CLK, "clk_fmc", "fmc_mux", 69 CLK_SET_RATE_PARENT, 0xc0, 1, 0, }, 70 { HI3519_UART0_CLK, "clk_uart0", "24m", 71 CLK_SET_RATE_PARENT, 0xe4, 20, 0, }, 72 { HI3519_UART1_CLK, "clk_uart1", "24m", 73 CLK_SET_RATE_PARENT, 0xe4, 21, 0, }, 74 { HI3519_UART2_CLK, "clk_uart2", "24m", 75 CLK_SET_RATE_PARENT, 0xe4, 22, 0, }, 76 { HI3519_UART3_CLK, "clk_uart3", "24m", 77 CLK_SET_RATE_PARENT, 0xe4, 23, 0, }, 78 { HI3519_UART4_CLK, "clk_uart4", "24m", 79 CLK_SET_RATE_PARENT, 0xe4, 24, 0, }, 80 { HI3519_SPI0_CLK, "clk_spi0", "50m", 81 CLK_SET_RATE_PARENT, 0xe4, 16, 0, }, 82 { HI3519_SPI1_CLK, "clk_spi1", "50m", 83 CLK_SET_RATE_PARENT, 0xe4, 17, 0, }, 84 { HI3519_SPI2_CLK, "clk_spi2", "50m", 85 CLK_SET_RATE_PARENT, 0xe4, 18, 0, }, 86 }; 87 88 static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev) 89 { 90 struct hisi_clock_data *clk_data; 91 int ret; 92 93 clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS); 94 if (!clk_data) 95 return ERR_PTR(-ENOMEM); 96 97 ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks, 98 ARRAY_SIZE(hi3519_fixed_rate_clks), 99 clk_data); 100 if (ret) 101 return ERR_PTR(ret); 102 103 ret = hisi_clk_register_mux(hi3519_mux_clks, 104 ARRAY_SIZE(hi3519_mux_clks), 105 clk_data); 106 if (ret) 107 goto unregister_fixed_rate; 108 109 ret = hisi_clk_register_gate(hi3519_gate_clks, 110 ARRAY_SIZE(hi3519_gate_clks), 111 clk_data); 112 if (ret) 113 goto unregister_mux; 114 115 ret = of_clk_add_provider(pdev->dev.of_node, 116 of_clk_src_onecell_get, &clk_data->clk_data); 117 if (ret) 118 goto unregister_gate; 119 120 return clk_data; 121 122 unregister_fixed_rate: 123 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, 124 ARRAY_SIZE(hi3519_fixed_rate_clks), 125 clk_data); 126 127 unregister_mux: 128 hisi_clk_unregister_mux(hi3519_mux_clks, 129 ARRAY_SIZE(hi3519_mux_clks), 130 clk_data); 131 unregister_gate: 132 hisi_clk_unregister_gate(hi3519_gate_clks, 133 ARRAY_SIZE(hi3519_gate_clks), 134 clk_data); 135 return ERR_PTR(ret); 136 } 137 138 static void hi3519_clk_unregister(struct platform_device *pdev) 139 { 140 struct hi3519_crg_data *crg = platform_get_drvdata(pdev); 141 142 of_clk_del_provider(pdev->dev.of_node); 143 144 hisi_clk_unregister_gate(hi3519_gate_clks, 145 ARRAY_SIZE(hi3519_mux_clks), 146 crg->clk_data); 147 hisi_clk_unregister_mux(hi3519_mux_clks, 148 ARRAY_SIZE(hi3519_mux_clks), 149 crg->clk_data); 150 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, 151 ARRAY_SIZE(hi3519_fixed_rate_clks), 152 crg->clk_data); 153 } 154 155 static int hi3519_clk_probe(struct platform_device *pdev) 156 { 157 struct hi3519_crg_data *crg; 158 159 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); 160 if (!crg) 161 return -ENOMEM; 162 163 crg->rstc = hisi_reset_init(pdev); 164 if (!crg->rstc) 165 return -ENOMEM; 166 167 crg->clk_data = hi3519_clk_register(pdev); 168 if (IS_ERR(crg->clk_data)) { 169 hisi_reset_exit(crg->rstc); 170 return PTR_ERR(crg->clk_data); 171 } 172 173 platform_set_drvdata(pdev, crg); 174 return 0; 175 } 176 177 static int hi3519_clk_remove(struct platform_device *pdev) 178 { 179 struct hi3519_crg_data *crg = platform_get_drvdata(pdev); 180 181 hisi_reset_exit(crg->rstc); 182 hi3519_clk_unregister(pdev); 183 return 0; 184 } 185 186 187 static const struct of_device_id hi3519_clk_match_table[] = { 188 { .compatible = "hisilicon,hi3519-crg" }, 189 { } 190 }; 191 MODULE_DEVICE_TABLE(of, hi3519_clk_match_table); 192 193 static struct platform_driver hi3519_clk_driver = { 194 .probe = hi3519_clk_probe, 195 .remove = hi3519_clk_remove, 196 .driver = { 197 .name = "hi3519-clk", 198 .of_match_table = hi3519_clk_match_table, 199 }, 200 }; 201 202 static int __init hi3519_clk_init(void) 203 { 204 return platform_driver_register(&hi3519_clk_driver); 205 } 206 core_initcall(hi3519_clk_init); 207 208 static void __exit hi3519_clk_exit(void) 209 { 210 platform_driver_unregister(&hi3519_clk_driver); 211 } 212 module_exit(hi3519_clk_exit); 213 214 MODULE_LICENSE("GPL v2"); 215 MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver"); 216