1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PSC clock descriptions for TI DA850/OMAP-L138/AM18XX 4 * 5 * Copyright (C) 2018 David Lechner <david@lechnology.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/clk.h> 10 #include <linux/clkdev.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/types.h> 15 16 #include "psc.h" 17 18 LPSC_CLKDEV2(emifa_clkdev, NULL, "ti-aemif", 19 "aemif", "davinci_nand.0"); 20 LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); 21 LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0"); 22 LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); 23 /* REVISIT: used dev_id instead of con_id */ 24 LPSC_CLKDEV1(arm_clkdev, "arm", NULL); 25 LPSC_CLKDEV1(dsp_clkdev, NULL, "davinci-rproc.0"); 26 27 static const struct davinci_lpsc_clk_info da850_psc0_info[] = { 28 LPSC(0, 0, tpcc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 29 LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 30 LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 31 LPSC(3, 0, emifa, async1, emifa_clkdev, 0), 32 LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), 33 LPSC(5, 0, mmcsd0, pll0_sysclk2, mmcsd0_clkdev, 0), 34 LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), 35 LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 36 LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0), 37 LPSC(13, 0, pruss, pll0_sysclk2, NULL, 0), 38 LPSC(14, 0, arm, pll0_sysclk6, arm_clkdev, LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT), 39 LPSC(15, 1, dsp, pll0_sysclk1, dsp_clkdev, LPSC_FORCE | LPSC_LOCAL_RESET), 40 { } 41 }; 42 43 LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", 44 NULL, "musb-da8xx", 45 NULL, "cppi41-dmaengine"); 46 LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); 47 /* REVISIT: gpio-davinci.c should be modified to drop con_id */ 48 LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); 49 LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", 50 "fck", "davinci_mdio.0"); 51 LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); 52 LPSC_CLKDEV1(sata_clkdev, "fck", "ahci_da850"); 53 LPSC_CLKDEV1(vpif_clkdev, NULL, "vpif"); 54 LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); 55 LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2"); 56 LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); 57 LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); 58 LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0"); 59 LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1"); 60 LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0"); 61 LPSC_CLKDEV3(ehrpwm_clkdev, "fck", "ehrpwm.0", 62 "fck", "ehrpwm.1", 63 NULL, "da830-tbclksync"); 64 LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1"); 65 LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0", 66 "fck", "ecap.1", 67 "fck", "ecap.2"); 68 69 static int da850_psc0_init(struct device *dev, void __iomem *base) 70 { 71 return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base); 72 } 73 74 static int of_da850_psc0_init(struct device *dev, void __iomem *base) 75 { 76 return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base); 77 } 78 79 static struct clk_bulk_data da850_psc0_parent_clks[] = { 80 { .id = "pll0_sysclk1" }, 81 { .id = "pll0_sysclk2" }, 82 { .id = "pll0_sysclk4" }, 83 { .id = "pll0_sysclk6" }, 84 { .id = "async1" }, 85 }; 86 87 const struct davinci_psc_init_data da850_psc0_init_data = { 88 .parent_clks = da850_psc0_parent_clks, 89 .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks), 90 .psc_init = &da850_psc0_init, 91 }; 92 93 const struct davinci_psc_init_data of_da850_psc0_init_data = { 94 .parent_clks = da850_psc0_parent_clks, 95 .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks), 96 .psc_init = &of_da850_psc0_init, 97 }; 98 99 static const struct davinci_lpsc_clk_info da850_psc1_info[] = { 100 LPSC(0, 0, tpcc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 101 LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0), 102 LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0), 103 LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0), 104 LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0), 105 LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 106 LPSC(7, 0, mcasp0, async3, mcasp0_clkdev, 0), 107 LPSC(8, 0, sata, pll0_sysclk2, sata_clkdev, LPSC_FORCE), 108 LPSC(9, 0, vpif, pll0_sysclk2, vpif_clkdev, 0), 109 LPSC(10, 0, spi1, async3, spi1_clkdev, 0), 110 LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0), 111 LPSC(12, 0, uart1, async3, uart1_clkdev, 0), 112 LPSC(13, 0, uart2, async3, uart2_clkdev, 0), 113 LPSC(14, 0, mcbsp0, async3, mcbsp0_clkdev, 0), 114 LPSC(15, 0, mcbsp1, async3, mcbsp1_clkdev, 0), 115 LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0), 116 LPSC(17, 0, ehrpwm, async3, ehrpwm_clkdev, 0), 117 LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0), 118 LPSC(20, 0, ecap, async3, ecap_clkdev, 0), 119 LPSC(21, 0, tptc2, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), 120 { } 121 }; 122 123 static int da850_psc1_init(struct device *dev, void __iomem *base) 124 { 125 return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base); 126 } 127 128 static int of_da850_psc1_init(struct device *dev, void __iomem *base) 129 { 130 return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base); 131 } 132 133 static struct clk_bulk_data da850_psc1_parent_clks[] = { 134 { .id = "pll0_sysclk2" }, 135 { .id = "pll0_sysclk4" }, 136 { .id = "async3" }, 137 }; 138 139 const struct davinci_psc_init_data da850_psc1_init_data = { 140 .parent_clks = da850_psc1_parent_clks, 141 .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks), 142 .psc_init = &da850_psc1_init, 143 }; 144 145 const struct davinci_psc_init_data of_da850_psc1_init_data = { 146 .parent_clks = da850_psc1_parent_clks, 147 .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks), 148 .psc_init = &of_da850_psc1_init, 149 }; 150