1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Clock driver for TI Davinci PSC controllers 4 * 5 * Copyright (C) 2018 David Lechner <david@lechnology.com> 6 */ 7 8 #ifndef __CLK_DAVINCI_PLL_H___ 9 #define __CLK_DAVINCI_PLL_H___ 10 11 #include <linux/bitops.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/types.h> 15 16 #define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */ 17 #define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */ 18 #define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */ 19 #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */ 20 #define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */ 21 #define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */ 22 #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */ 23 #define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */ 24 #define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */ 25 #define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */ 26 27 /** davinci_pll_clk_info - controller-specific PLL info 28 * @name: The name of the PLL 29 * @unlock_reg: Option CFGCHIP register for unlocking PLL 30 * @unlock_mask: Bitmask used with @unlock_reg 31 * @pllm_mask: Bitmask for PLLM[PLLM] value 32 * @pllm_min: Minimum allowable value for PLLM[PLLM] 33 * @pllm_max: Maximum allowable value for PLLM[PLLM] 34 * @pllout_min_rate: Minimum allowable rate for PLLOUT 35 * @pllout_max_rate: Maximum allowable rate for PLLOUT 36 * @flags: Bitmap of PLL_* flags. 37 */ 38 struct davinci_pll_clk_info { 39 const char *name; 40 u32 unlock_reg; 41 u32 unlock_mask; 42 u32 pllm_mask; 43 u32 pllm_min; 44 u32 pllm_max; 45 unsigned long pllout_min_rate; 46 unsigned long pllout_max_rate; 47 u32 flags; 48 }; 49 50 #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */ 51 #define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */ 52 #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */ 53 54 /** davinci_pll_sysclk_info - SYSCLKn-specific info 55 * @name: The name of the clock 56 * @parent_name: The name of the parent clock 57 * @id: "n" in "SYSCLKn" 58 * @ratio_width: Width (in bits) of RATIO in PLLDIVn register 59 * @flags: Bitmap of SYSCLK_* flags. 60 */ 61 struct davinci_pll_sysclk_info { 62 const char *name; 63 const char *parent_name; 64 u32 id; 65 u32 ratio_width; 66 u32 flags; 67 }; 68 69 #define SYSCLK(i, n, p, w, f) \ 70 static const struct davinci_pll_sysclk_info n = { \ 71 .name = #n, \ 72 .parent_name = #p, \ 73 .id = (i), \ 74 .ratio_width = (w), \ 75 .flags = (f), \ 76 } 77 78 /** davinci_pll_obsclk_info - OBSCLK-specific info 79 * @name: The name of the clock 80 * @parent_names: Array of names of the parent clocks 81 * @num_parents: Length of @parent_names 82 * @table: Array of values to write to OCSEL[OCSRC] cooresponding to 83 * @parent_names 84 * @ocsrc_mask: Bitmask for OCSEL[OCSRC] 85 */ 86 struct davinci_pll_obsclk_info { 87 const char *name; 88 const char * const *parent_names; 89 u8 num_parents; 90 u32 *table; 91 u32 ocsrc_mask; 92 }; 93 94 struct clk *davinci_pll_clk_register(struct device *dev, 95 const struct davinci_pll_clk_info *info, 96 const char *parent_name, 97 void __iomem *base); 98 struct clk *davinci_pll_auxclk_register(struct device *dev, 99 const char *name, 100 void __iomem *base); 101 struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev, 102 const char *name, 103 void __iomem *base); 104 struct clk * 105 davinci_pll_obsclk_register(struct device *dev, 106 const struct davinci_pll_obsclk_info *info, 107 void __iomem *base); 108 struct clk * 109 davinci_pll_sysclk_register(struct device *dev, 110 const struct davinci_pll_sysclk_info *info, 111 void __iomem *base); 112 113 int of_davinci_pll_init(struct device *dev, 114 const struct davinci_pll_clk_info *info, 115 const struct davinci_pll_obsclk_info *obsclk_info, 116 const struct davinci_pll_sysclk_info **div_info, 117 u8 max_sysclk_id, 118 void __iomem *base); 119 120 /* Platform-specific callbacks */ 121 122 int da830_pll_init(struct device *dev, void __iomem *base); 123 124 int da850_pll0_init(struct device *dev, void __iomem *base); 125 int da850_pll1_init(struct device *dev, void __iomem *base); 126 int of_da850_pll0_init(struct device *dev, void __iomem *base); 127 int of_da850_pll1_init(struct device *dev, void __iomem *base); 128 129 int dm355_pll1_init(struct device *dev, void __iomem *base); 130 int dm355_pll2_init(struct device *dev, void __iomem *base); 131 132 int dm365_pll1_init(struct device *dev, void __iomem *base); 133 int dm365_pll2_init(struct device *dev, void __iomem *base); 134 135 int dm644x_pll1_init(struct device *dev, void __iomem *base); 136 int dm644x_pll2_init(struct device *dev, void __iomem *base); 137 138 int dm646x_pll1_init(struct device *dev, void __iomem *base); 139 int dm646x_pll2_init(struct device *dev, void __iomem *base); 140 141 #endif /* __CLK_DAVINCI_PLL_H___ */ 142