1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX 4 * 5 * Copyright (C) 2018 David Lechner <david@lechnology.com> 6 */ 7 8 #include <linux/clkdev.h> 9 #include <linux/bitops.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 13 #include "pll.h" 14 15 static const struct davinci_pll_clk_info da830_pll_info = { 16 .name = "pll0", 17 .pllm_mask = GENMASK(4, 0), 18 .pllm_min = 4, 19 .pllm_max = 32, 20 .pllout_min_rate = 300000000, 21 .pllout_max_rate = 600000000, 22 .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 23 }; 24 25 /* 26 * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", 27 * meaning that we could change the divider as long as we keep the correct 28 * ratio between all of the clocks, but we don't support that because there is 29 * currently not a need for it. 30 */ 31 32 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); 33 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); 34 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); 35 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); 36 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); 37 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); 38 39 int da830_pll_init(struct device *dev, void __iomem *base) 40 { 41 struct clk *clk; 42 43 davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base); 44 45 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); 46 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); 47 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); 48 49 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); 50 clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); 51 52 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); 53 clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0"); 54 clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1"); 55 56 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); 57 clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1"); 58 59 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); 60 clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0"); 61 62 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); 63 64 clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); 65 clk_register_clkdev(clk, NULL, "i2c_davinci.1"); 66 clk_register_clkdev(clk, "timer0", NULL); 67 clk_register_clkdev(clk, NULL, "davinci-wdt"); 68 69 return 0; 70 } 71