1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX 4 * 5 * Copyright (C) 2018 David Lechner <david@lechnology.com> 6 */ 7 8 #include <linux/clkdev.h> 9 #include <linux/clk/davinci.h> 10 #include <linux/bitops.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 14 #include "pll.h" 15 16 static const struct davinci_pll_clk_info da830_pll_info = { 17 .name = "pll0", 18 .pllm_mask = GENMASK(4, 0), 19 .pllm_min = 4, 20 .pllm_max = 32, 21 .pllout_min_rate = 300000000, 22 .pllout_max_rate = 600000000, 23 .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV, 24 }; 25 26 /* 27 * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", 28 * meaning that we could change the divider as long as we keep the correct 29 * ratio between all of the clocks, but we don't support that because there is 30 * currently not a need for it. 31 */ 32 33 SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); 34 SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); 35 SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); 36 SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); 37 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); 38 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); 39 40 int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) 41 { 42 struct clk *clk; 43 44 davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip); 45 46 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); 47 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); 48 clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); 49 50 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); 51 clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); 52 53 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); 54 clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0"); 55 clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1"); 56 57 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); 58 clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1"); 59 60 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); 61 clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0"); 62 63 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); 64 65 clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); 66 clk_register_clkdev(clk, NULL, "i2c_davinci.1"); 67 clk_register_clkdev(clk, "timer0", NULL); 68 clk_register_clkdev(clk, NULL, "davinci-wdt"); 69 70 return 0; 71 } 72