1 /* 2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface 3 * 4 * Copyright (c) 2013, Applied Micro Circuits Corporation 5 * Author: Loc Ho <lho@apm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 * 22 */ 23 #include <linux/module.h> 24 #include <linux/spinlock.h> 25 #include <linux/io.h> 26 #include <linux/of.h> 27 #include <linux/clkdev.h> 28 #include <linux/clk-provider.h> 29 #include <linux/of_address.h> 30 #include <asm/setup.h> 31 32 /* Register SCU_PCPPLL bit fields */ 33 #define N_DIV_RD(src) (((src) & 0x000001ff)) 34 35 /* Register SCU_SOCPLL bit fields */ 36 #define CLKR_RD(src) (((src) & 0x07000000)>>24) 37 #define CLKOD_RD(src) (((src) & 0x00300000)>>20) 38 #define REGSPEC_RESET_F1_MASK 0x00010000 39 #define CLKF_RD(src) (((src) & 0x000001ff)) 40 41 #define XGENE_CLK_DRIVER_VER "0.1" 42 43 static DEFINE_SPINLOCK(clk_lock); 44 45 static inline u32 xgene_clk_read(void __iomem *csr) 46 { 47 return readl_relaxed(csr); 48 } 49 50 static inline void xgene_clk_write(u32 data, void __iomem *csr) 51 { 52 return writel_relaxed(data, csr); 53 } 54 55 /* PLL Clock */ 56 enum xgene_pll_type { 57 PLL_TYPE_PCP = 0, 58 PLL_TYPE_SOC = 1, 59 }; 60 61 struct xgene_clk_pll { 62 struct clk_hw hw; 63 const char *name; 64 void __iomem *reg; 65 spinlock_t *lock; 66 u32 pll_offset; 67 enum xgene_pll_type type; 68 }; 69 70 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw) 71 72 static int xgene_clk_pll_is_enabled(struct clk_hw *hw) 73 { 74 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); 75 u32 data; 76 77 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 78 pr_debug("%s pll %s\n", pllclk->name, 79 data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled"); 80 81 return data & REGSPEC_RESET_F1_MASK ? 0 : 1; 82 } 83 84 static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, 85 unsigned long parent_rate) 86 { 87 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); 88 unsigned long fref; 89 unsigned long fvco; 90 u32 pll; 91 u32 nref; 92 u32 nout; 93 u32 nfb; 94 95 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 96 97 if (pllclk->type == PLL_TYPE_PCP) { 98 /* 99 * PLL VCO = Reference clock * NF 100 * PCP PLL = PLL_VCO / 2 101 */ 102 nout = 2; 103 fvco = parent_rate * (N_DIV_RD(pll) + 4); 104 } else { 105 /* 106 * Fref = Reference Clock / NREF; 107 * Fvco = Fref * NFB; 108 * Fout = Fvco / NOUT; 109 */ 110 nref = CLKR_RD(pll) + 1; 111 nout = CLKOD_RD(pll) + 1; 112 nfb = CLKF_RD(pll); 113 fref = parent_rate / nref; 114 fvco = fref * nfb; 115 } 116 pr_debug("%s pll recalc rate %ld parent %ld\n", pllclk->name, 117 fvco / nout, parent_rate); 118 119 return fvco / nout; 120 } 121 122 static const struct clk_ops xgene_clk_pll_ops = { 123 .is_enabled = xgene_clk_pll_is_enabled, 124 .recalc_rate = xgene_clk_pll_recalc_rate, 125 }; 126 127 static struct clk *xgene_register_clk_pll(struct device *dev, 128 const char *name, const char *parent_name, 129 unsigned long flags, void __iomem *reg, u32 pll_offset, 130 u32 type, spinlock_t *lock) 131 { 132 struct xgene_clk_pll *apmclk; 133 struct clk *clk; 134 struct clk_init_data init; 135 136 /* allocate the APM clock structure */ 137 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); 138 if (!apmclk) { 139 pr_err("%s: could not allocate APM clk\n", __func__); 140 return ERR_PTR(-ENOMEM); 141 } 142 143 init.name = name; 144 init.ops = &xgene_clk_pll_ops; 145 init.flags = flags; 146 init.parent_names = parent_name ? &parent_name : NULL; 147 init.num_parents = parent_name ? 1 : 0; 148 149 apmclk->name = name; 150 apmclk->reg = reg; 151 apmclk->lock = lock; 152 apmclk->pll_offset = pll_offset; 153 apmclk->type = type; 154 apmclk->hw.init = &init; 155 156 /* Register the clock */ 157 clk = clk_register(dev, &apmclk->hw); 158 if (IS_ERR(clk)) { 159 pr_err("%s: could not register clk %s\n", __func__, name); 160 kfree(apmclk); 161 return NULL; 162 } 163 return clk; 164 } 165 166 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) 167 { 168 const char *clk_name = np->full_name; 169 struct clk *clk; 170 void __iomem *reg; 171 172 reg = of_iomap(np, 0); 173 if (reg == NULL) { 174 pr_err("Unable to map CSR register for %s\n", np->full_name); 175 return; 176 } 177 of_property_read_string(np, "clock-output-names", &clk_name); 178 clk = xgene_register_clk_pll(NULL, 179 clk_name, of_clk_get_parent_name(np, 0), 180 CLK_IS_ROOT, reg, 0, pll_type, &clk_lock); 181 if (!IS_ERR(clk)) { 182 of_clk_add_provider(np, of_clk_src_simple_get, clk); 183 clk_register_clkdev(clk, clk_name, NULL); 184 pr_debug("Add %s clock PLL\n", clk_name); 185 } 186 } 187 188 static void xgene_socpllclk_init(struct device_node *np) 189 { 190 xgene_pllclk_init(np, PLL_TYPE_SOC); 191 } 192 193 static void xgene_pcppllclk_init(struct device_node *np) 194 { 195 xgene_pllclk_init(np, PLL_TYPE_PCP); 196 } 197 198 /* IP Clock */ 199 struct xgene_dev_parameters { 200 void __iomem *csr_reg; /* CSR for IP clock */ 201 u32 reg_clk_offset; /* Offset to clock enable CSR */ 202 u32 reg_clk_mask; /* Mask bit for clock enable */ 203 u32 reg_csr_offset; /* Offset to CSR reset */ 204 u32 reg_csr_mask; /* Mask bit for disable CSR reset */ 205 void __iomem *divider_reg; /* CSR for divider */ 206 u32 reg_divider_offset; /* Offset to divider register */ 207 u32 reg_divider_shift; /* Bit shift to divider field */ 208 u32 reg_divider_width; /* Width of the bit to divider field */ 209 }; 210 211 struct xgene_clk { 212 struct clk_hw hw; 213 const char *name; 214 spinlock_t *lock; 215 struct xgene_dev_parameters param; 216 }; 217 218 #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw) 219 220 static int xgene_clk_enable(struct clk_hw *hw) 221 { 222 struct xgene_clk *pclk = to_xgene_clk(hw); 223 unsigned long flags = 0; 224 u32 data; 225 phys_addr_t reg; 226 227 if (pclk->lock) 228 spin_lock_irqsave(pclk->lock, flags); 229 230 if (pclk->param.csr_reg != NULL) { 231 pr_debug("%s clock enabled\n", pclk->name); 232 reg = __pa(pclk->param.csr_reg); 233 /* First enable the clock */ 234 data = xgene_clk_read(pclk->param.csr_reg + 235 pclk->param.reg_clk_offset); 236 data |= pclk->param.reg_clk_mask; 237 xgene_clk_write(data, pclk->param.csr_reg + 238 pclk->param.reg_clk_offset); 239 pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n", 240 pclk->name, ®, 241 pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, 242 data); 243 244 /* Second enable the CSR */ 245 data = xgene_clk_read(pclk->param.csr_reg + 246 pclk->param.reg_csr_offset); 247 data &= ~pclk->param.reg_csr_mask; 248 xgene_clk_write(data, pclk->param.csr_reg + 249 pclk->param.reg_csr_offset); 250 pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n", 251 pclk->name, ®, 252 pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, 253 data); 254 } 255 256 if (pclk->lock) 257 spin_unlock_irqrestore(pclk->lock, flags); 258 259 return 0; 260 } 261 262 static void xgene_clk_disable(struct clk_hw *hw) 263 { 264 struct xgene_clk *pclk = to_xgene_clk(hw); 265 unsigned long flags = 0; 266 u32 data; 267 268 if (pclk->lock) 269 spin_lock_irqsave(pclk->lock, flags); 270 271 if (pclk->param.csr_reg != NULL) { 272 pr_debug("%s clock disabled\n", pclk->name); 273 /* First put the CSR in reset */ 274 data = xgene_clk_read(pclk->param.csr_reg + 275 pclk->param.reg_csr_offset); 276 data |= pclk->param.reg_csr_mask; 277 xgene_clk_write(data, pclk->param.csr_reg + 278 pclk->param.reg_csr_offset); 279 280 /* Second disable the clock */ 281 data = xgene_clk_read(pclk->param.csr_reg + 282 pclk->param.reg_clk_offset); 283 data &= ~pclk->param.reg_clk_mask; 284 xgene_clk_write(data, pclk->param.csr_reg + 285 pclk->param.reg_clk_offset); 286 } 287 288 if (pclk->lock) 289 spin_unlock_irqrestore(pclk->lock, flags); 290 } 291 292 static int xgene_clk_is_enabled(struct clk_hw *hw) 293 { 294 struct xgene_clk *pclk = to_xgene_clk(hw); 295 u32 data = 0; 296 297 if (pclk->param.csr_reg != NULL) { 298 pr_debug("%s clock checking\n", pclk->name); 299 data = xgene_clk_read(pclk->param.csr_reg + 300 pclk->param.reg_clk_offset); 301 pr_debug("%s clock is %s\n", pclk->name, 302 data & pclk->param.reg_clk_mask ? "enabled" : 303 "disabled"); 304 } 305 306 if (pclk->param.csr_reg == NULL) 307 return 1; 308 return data & pclk->param.reg_clk_mask ? 1 : 0; 309 } 310 311 static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, 312 unsigned long parent_rate) 313 { 314 struct xgene_clk *pclk = to_xgene_clk(hw); 315 u32 data; 316 317 if (pclk->param.divider_reg) { 318 data = xgene_clk_read(pclk->param.divider_reg + 319 pclk->param.reg_divider_offset); 320 data >>= pclk->param.reg_divider_shift; 321 data &= (1 << pclk->param.reg_divider_width) - 1; 322 323 pr_debug("%s clock recalc rate %ld parent %ld\n", 324 pclk->name, parent_rate / data, parent_rate); 325 return parent_rate / data; 326 } else { 327 pr_debug("%s clock recalc rate %ld parent %ld\n", 328 pclk->name, parent_rate, parent_rate); 329 return parent_rate; 330 } 331 } 332 333 static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, 334 unsigned long parent_rate) 335 { 336 struct xgene_clk *pclk = to_xgene_clk(hw); 337 unsigned long flags = 0; 338 u32 data; 339 u32 divider; 340 u32 divider_save; 341 342 if (pclk->lock) 343 spin_lock_irqsave(pclk->lock, flags); 344 345 if (pclk->param.divider_reg) { 346 /* Let's compute the divider */ 347 if (rate > parent_rate) 348 rate = parent_rate; 349 divider_save = divider = parent_rate / rate; /* Rounded down */ 350 divider &= (1 << pclk->param.reg_divider_width) - 1; 351 divider <<= pclk->param.reg_divider_shift; 352 353 /* Set new divider */ 354 data = xgene_clk_read(pclk->param.divider_reg + 355 pclk->param.reg_divider_offset); 356 data &= ~((1 << pclk->param.reg_divider_width) - 1); 357 data |= divider; 358 xgene_clk_write(data, pclk->param.divider_reg + 359 pclk->param.reg_divider_offset); 360 pr_debug("%s clock set rate %ld\n", pclk->name, 361 parent_rate / divider_save); 362 } else { 363 divider_save = 1; 364 } 365 366 if (pclk->lock) 367 spin_unlock_irqrestore(pclk->lock, flags); 368 369 return parent_rate / divider_save; 370 } 371 372 static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate, 373 unsigned long *prate) 374 { 375 struct xgene_clk *pclk = to_xgene_clk(hw); 376 unsigned long parent_rate = *prate; 377 u32 divider; 378 379 if (pclk->param.divider_reg) { 380 /* Let's compute the divider */ 381 if (rate > parent_rate) 382 rate = parent_rate; 383 divider = parent_rate / rate; /* Rounded down */ 384 } else { 385 divider = 1; 386 } 387 388 return parent_rate / divider; 389 } 390 391 static const struct clk_ops xgene_clk_ops = { 392 .enable = xgene_clk_enable, 393 .disable = xgene_clk_disable, 394 .is_enabled = xgene_clk_is_enabled, 395 .recalc_rate = xgene_clk_recalc_rate, 396 .set_rate = xgene_clk_set_rate, 397 .round_rate = xgene_clk_round_rate, 398 }; 399 400 static struct clk *xgene_register_clk(struct device *dev, 401 const char *name, const char *parent_name, 402 struct xgene_dev_parameters *parameters, spinlock_t *lock) 403 { 404 struct xgene_clk *apmclk; 405 struct clk *clk; 406 struct clk_init_data init; 407 int rc; 408 409 /* allocate the APM clock structure */ 410 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); 411 if (!apmclk) { 412 pr_err("%s: could not allocate APM clk\n", __func__); 413 return ERR_PTR(-ENOMEM); 414 } 415 416 init.name = name; 417 init.ops = &xgene_clk_ops; 418 init.flags = 0; 419 init.parent_names = parent_name ? &parent_name : NULL; 420 init.num_parents = parent_name ? 1 : 0; 421 422 apmclk->name = name; 423 apmclk->lock = lock; 424 apmclk->hw.init = &init; 425 apmclk->param = *parameters; 426 427 /* Register the clock */ 428 clk = clk_register(dev, &apmclk->hw); 429 if (IS_ERR(clk)) { 430 pr_err("%s: could not register clk %s\n", __func__, name); 431 kfree(apmclk); 432 return clk; 433 } 434 435 /* Register the clock for lookup */ 436 rc = clk_register_clkdev(clk, name, NULL); 437 if (rc != 0) { 438 pr_err("%s: could not register lookup clk %s\n", 439 __func__, name); 440 } 441 return clk; 442 } 443 444 static void __init xgene_devclk_init(struct device_node *np) 445 { 446 const char *clk_name = np->full_name; 447 struct clk *clk; 448 struct resource res; 449 int rc; 450 struct xgene_dev_parameters parameters; 451 int i; 452 453 /* Check if the entry is disabled */ 454 if (!of_device_is_available(np)) 455 return; 456 457 /* Parse the DTS register for resource */ 458 parameters.csr_reg = NULL; 459 parameters.divider_reg = NULL; 460 for (i = 0; i < 2; i++) { 461 void __iomem *map_res; 462 rc = of_address_to_resource(np, i, &res); 463 if (rc != 0) { 464 if (i == 0) { 465 pr_err("no DTS register for %s\n", 466 np->full_name); 467 return; 468 } 469 break; 470 } 471 map_res = of_iomap(np, i); 472 if (map_res == NULL) { 473 pr_err("Unable to map resource %d for %s\n", 474 i, np->full_name); 475 goto err; 476 } 477 if (strcmp(res.name, "div-reg") == 0) 478 parameters.divider_reg = map_res; 479 else /* if (strcmp(res->name, "csr-reg") == 0) */ 480 parameters.csr_reg = map_res; 481 } 482 if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset)) 483 parameters.reg_csr_offset = 0; 484 if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask)) 485 parameters.reg_csr_mask = 0xF; 486 if (of_property_read_u32(np, "enable-offset", 487 ¶meters.reg_clk_offset)) 488 parameters.reg_clk_offset = 0x8; 489 if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask)) 490 parameters.reg_clk_mask = 0xF; 491 if (of_property_read_u32(np, "divider-offset", 492 ¶meters.reg_divider_offset)) 493 parameters.reg_divider_offset = 0; 494 if (of_property_read_u32(np, "divider-width", 495 ¶meters.reg_divider_width)) 496 parameters.reg_divider_width = 0; 497 if (of_property_read_u32(np, "divider-shift", 498 ¶meters.reg_divider_shift)) 499 parameters.reg_divider_shift = 0; 500 of_property_read_string(np, "clock-output-names", &clk_name); 501 502 clk = xgene_register_clk(NULL, clk_name, 503 of_clk_get_parent_name(np, 0), ¶meters, &clk_lock); 504 if (IS_ERR(clk)) 505 goto err; 506 pr_debug("Add %s clock\n", clk_name); 507 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 508 if (rc != 0) 509 pr_err("%s: could register provider clk %s\n", __func__, 510 np->full_name); 511 512 return; 513 514 err: 515 if (parameters.csr_reg) 516 iounmap(parameters.csr_reg); 517 if (parameters.divider_reg) 518 iounmap(parameters.divider_reg); 519 } 520 521 CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); 522 CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); 523 CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init); 524