1 /* 2 * Clock implementation for VIA/Wondermedia SoC's 3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/slab.h> 20 #include <linux/bitops.h> 21 #include <linux/clkdev.h> 22 #include <linux/clk-provider.h> 23 24 #define LEGACY_PMC_BASE 0xD8130000 25 26 /* All clocks share the same lock as none can be changed concurrently */ 27 static DEFINE_SPINLOCK(_lock); 28 29 struct clk_device { 30 struct clk_hw hw; 31 void __iomem *div_reg; 32 unsigned int div_mask; 33 void __iomem *en_reg; 34 int en_bit; 35 spinlock_t *lock; 36 }; 37 38 /* 39 * Add new PLL_TYPE_x definitions here as required. Use the first known model 40 * to support the new type as the name. 41 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and 42 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x 43 */ 44 45 #define PLL_TYPE_VT8500 0 46 #define PLL_TYPE_WM8650 1 47 #define PLL_TYPE_WM8750 2 48 #define PLL_TYPE_WM8850 3 49 50 struct clk_pll { 51 struct clk_hw hw; 52 void __iomem *reg; 53 spinlock_t *lock; 54 int type; 55 }; 56 57 static void __iomem *pmc_base; 58 59 static __init void vtwm_set_pmc_base(void) 60 { 61 struct device_node *np = 62 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc"); 63 64 if (np) 65 pmc_base = of_iomap(np, 0); 66 else 67 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); 68 of_node_put(np); 69 70 if (!pmc_base) 71 pr_err("%s:of_iomap(pmc) failed\n", __func__); 72 } 73 74 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw) 75 76 #define VT8500_PMC_BUSY_MASK 0x18 77 78 static void vt8500_pmc_wait_busy(void) 79 { 80 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK) 81 cpu_relax(); 82 } 83 84 static int vt8500_dclk_enable(struct clk_hw *hw) 85 { 86 struct clk_device *cdev = to_clk_device(hw); 87 u32 en_val; 88 unsigned long flags = 0; 89 90 spin_lock_irqsave(cdev->lock, flags); 91 92 en_val = readl(cdev->en_reg); 93 en_val |= BIT(cdev->en_bit); 94 writel(en_val, cdev->en_reg); 95 96 spin_unlock_irqrestore(cdev->lock, flags); 97 return 0; 98 } 99 100 static void vt8500_dclk_disable(struct clk_hw *hw) 101 { 102 struct clk_device *cdev = to_clk_device(hw); 103 u32 en_val; 104 unsigned long flags = 0; 105 106 spin_lock_irqsave(cdev->lock, flags); 107 108 en_val = readl(cdev->en_reg); 109 en_val &= ~BIT(cdev->en_bit); 110 writel(en_val, cdev->en_reg); 111 112 spin_unlock_irqrestore(cdev->lock, flags); 113 } 114 115 static int vt8500_dclk_is_enabled(struct clk_hw *hw) 116 { 117 struct clk_device *cdev = to_clk_device(hw); 118 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); 119 120 return en_val ? 1 : 0; 121 } 122 123 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw, 124 unsigned long parent_rate) 125 { 126 struct clk_device *cdev = to_clk_device(hw); 127 u32 div = readl(cdev->div_reg) & cdev->div_mask; 128 129 /* Special case for SDMMC devices */ 130 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) 131 div = 64 * (div & 0x1f); 132 133 /* div == 0 is actually the highest divisor */ 134 if (div == 0) 135 div = (cdev->div_mask + 1); 136 137 return parent_rate / div; 138 } 139 140 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, 141 unsigned long *prate) 142 { 143 struct clk_device *cdev = to_clk_device(hw); 144 u32 divisor; 145 146 if (rate == 0) 147 return 0; 148 149 divisor = *prate / rate; 150 151 /* If prate / rate would be decimal, incr the divisor */ 152 if (rate * divisor < *prate) 153 divisor++; 154 155 /* 156 * If this is a request for SDMMC we have to adjust the divisor 157 * when >31 to use the fixed predivisor 158 */ 159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 160 divisor = 64 * ((divisor / 64) + 1); 161 } 162 163 return *prate / divisor; 164 } 165 166 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 167 unsigned long parent_rate) 168 { 169 struct clk_device *cdev = to_clk_device(hw); 170 u32 divisor; 171 unsigned long flags = 0; 172 173 if (rate == 0) 174 return 0; 175 176 divisor = parent_rate / rate; 177 178 if (divisor == cdev->div_mask + 1) 179 divisor = 0; 180 181 /* SDMMC mask may need to be corrected before testing if its valid */ 182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 183 /* 184 * Bit 5 is a fixed /64 predivisor. If the requested divisor 185 * is >31 then correct for the fixed divisor being required. 186 */ 187 divisor = 0x20 + (divisor / 64); 188 } 189 190 if (divisor > cdev->div_mask) { 191 pr_err("%s: invalid divisor for clock\n", __func__); 192 return -EINVAL; 193 } 194 195 spin_lock_irqsave(cdev->lock, flags); 196 197 vt8500_pmc_wait_busy(); 198 writel(divisor, cdev->div_reg); 199 vt8500_pmc_wait_busy(); 200 201 spin_unlock_irqrestore(cdev->lock, flags); 202 203 return 0; 204 } 205 206 207 static const struct clk_ops vt8500_gated_clk_ops = { 208 .enable = vt8500_dclk_enable, 209 .disable = vt8500_dclk_disable, 210 .is_enabled = vt8500_dclk_is_enabled, 211 }; 212 213 static const struct clk_ops vt8500_divisor_clk_ops = { 214 .round_rate = vt8500_dclk_round_rate, 215 .set_rate = vt8500_dclk_set_rate, 216 .recalc_rate = vt8500_dclk_recalc_rate, 217 }; 218 219 static const struct clk_ops vt8500_gated_divisor_clk_ops = { 220 .enable = vt8500_dclk_enable, 221 .disable = vt8500_dclk_disable, 222 .is_enabled = vt8500_dclk_is_enabled, 223 .round_rate = vt8500_dclk_round_rate, 224 .set_rate = vt8500_dclk_set_rate, 225 .recalc_rate = vt8500_dclk_recalc_rate, 226 }; 227 228 #define CLK_INIT_GATED BIT(0) 229 #define CLK_INIT_DIVISOR BIT(1) 230 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED) 231 232 static __init void vtwm_device_clk_init(struct device_node *node) 233 { 234 u32 en_reg, div_reg; 235 struct clk_hw *hw; 236 struct clk_device *dev_clk; 237 const char *clk_name = node->name; 238 const char *parent_name; 239 struct clk_init_data init; 240 int rc; 241 int clk_init_flags = 0; 242 243 if (!pmc_base) 244 vtwm_set_pmc_base(); 245 246 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL); 247 if (WARN_ON(!dev_clk)) 248 return; 249 250 dev_clk->lock = &_lock; 251 252 rc = of_property_read_u32(node, "enable-reg", &en_reg); 253 if (!rc) { 254 dev_clk->en_reg = pmc_base + en_reg; 255 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit); 256 if (rc) { 257 pr_err("%s: enable-bit property required for gated clock\n", 258 __func__); 259 return; 260 } 261 clk_init_flags |= CLK_INIT_GATED; 262 } 263 264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); 265 if (!rc) { 266 dev_clk->div_reg = pmc_base + div_reg; 267 /* 268 * use 0x1f as the default mask since it covers 269 * almost all the clocks and reduces dts properties 270 */ 271 dev_clk->div_mask = 0x1f; 272 273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); 274 clk_init_flags |= CLK_INIT_DIVISOR; 275 } 276 277 of_property_read_string(node, "clock-output-names", &clk_name); 278 279 switch (clk_init_flags) { 280 case CLK_INIT_GATED: 281 init.ops = &vt8500_gated_clk_ops; 282 break; 283 case CLK_INIT_DIVISOR: 284 init.ops = &vt8500_divisor_clk_ops; 285 break; 286 case CLK_INIT_GATED_DIVISOR: 287 init.ops = &vt8500_gated_divisor_clk_ops; 288 break; 289 default: 290 pr_err("%s: Invalid clock description in device tree\n", 291 __func__); 292 kfree(dev_clk); 293 return; 294 } 295 296 init.name = clk_name; 297 init.flags = 0; 298 parent_name = of_clk_get_parent_name(node, 0); 299 init.parent_names = &parent_name; 300 init.num_parents = 1; 301 302 dev_clk->hw.init = &init; 303 304 hw = &dev_clk->hw; 305 rc = clk_hw_register(NULL, hw); 306 if (WARN_ON(rc)) { 307 kfree(dev_clk); 308 return; 309 } 310 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); 311 clk_hw_register_clkdev(hw, clk_name, NULL); 312 } 313 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init); 314 315 /* PLL clock related functions */ 316 317 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) 318 319 /* Helper macros for PLL_VT8500 */ 320 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1) 321 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2) 322 323 #define VT8500_BITS_TO_FREQ(r, m, d) \ 324 ((r / d) * m) 325 326 #define VT8500_BITS_TO_VAL(m, d) \ 327 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F)) 328 329 /* Helper macros for PLL_WM8650 */ 330 #define WM8650_PLL_MUL(x) (x & 0x3FF) 331 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3))) 332 333 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \ 334 (r * m / (d1 * (1 << d2))) 335 336 #define WM8650_BITS_TO_VAL(m, d1, d2) \ 337 ((d2 << 13) | (d1 << 10) | (m & 0x3FF)) 338 339 /* Helper macros for PLL_WM8750 */ 340 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1) 341 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7))) 342 343 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \ 344 (r * (m+1) / ((d1+1) * (1 << d2))) 345 346 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \ 347 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2) 348 349 /* Helper macros for PLL_WM8850 */ 350 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2) 351 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3))) 352 353 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \ 354 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2))) 355 356 #define WM8850_BITS_TO_VAL(m, d1, d2) \ 357 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2) 358 359 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, 360 u32 *multiplier, u32 *prediv) 361 { 362 unsigned long tclk; 363 364 /* sanity check */ 365 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { 366 pr_err("%s: requested rate out of range\n", __func__); 367 *multiplier = 0; 368 *prediv = 1; 369 return -EINVAL; 370 } 371 if (rate <= parent_rate * 31) 372 /* use the prediv to double the resolution */ 373 *prediv = 2; 374 else 375 *prediv = 1; 376 377 *multiplier = rate / (parent_rate / *prediv); 378 tclk = (parent_rate / *prediv) * *multiplier; 379 380 if (tclk != rate) 381 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, 382 rate, tclk); 383 384 return 0; 385 } 386 387 /* 388 * M * parent [O1] => / P [O2] => / D [O3] 389 * Where O1 is 900MHz...3GHz; 390 * O2 is 600MHz >= (M * parent) / P >= 300MHz; 391 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8. 392 * Possible ranges (O3): 393 * D = 8: 37,5MHz...75MHz 394 * D = 4: 75MHz...150MHz 395 * D = 2: 150MHz...300MHz 396 * D = 1: 300MHz...600MHz 397 */ 398 static int wm8650_find_pll_bits(unsigned long rate, 399 unsigned long parent_rate, u32 *multiplier, u32 *divisor1, 400 u32 *divisor2) 401 { 402 unsigned long O1, min_err, rate_err; 403 404 if (!parent_rate || (rate < 37500000) || (rate > 600000000)) 405 return -EINVAL; 406 407 *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 : 408 rate <= 300000000 ? 1 : 0; 409 /* 410 * Divisor P cannot be calculated. Test all divisors and find where M 411 * will be as close as possible to the requested rate. 412 */ 413 min_err = ULONG_MAX; 414 for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) { 415 O1 = rate * *divisor1 * (1 << (*divisor2)); 416 rate_err = O1 % parent_rate; 417 if (rate_err < min_err) { 418 *multiplier = O1 / parent_rate; 419 if (rate_err == 0) 420 return 0; 421 422 min_err = rate_err; 423 } 424 } 425 426 if ((*multiplier < 3) || (*multiplier > 1023)) 427 return -EINVAL; 428 429 pr_warn("%s: rate error is %lu\n", __func__, min_err); 430 431 return 0; 432 } 433 434 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1) 435 { 436 /* calculate frequency (MHz) after pre-divisor */ 437 u32 freq = (parent_rate / 1000000) / (divisor1 + 1); 438 439 if ((freq < 10) || (freq > 200)) 440 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", 441 __func__, freq); 442 443 if (freq >= 166) 444 return 7; 445 else if (freq >= 104) 446 return 6; 447 else if (freq >= 65) 448 return 5; 449 else if (freq >= 42) 450 return 4; 451 else if (freq >= 26) 452 return 3; 453 else if (freq >= 16) 454 return 2; 455 else if (freq >= 10) 456 return 1; 457 458 return 0; 459 } 460 461 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate, 462 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2) 463 { 464 u32 mul; 465 int div1, div2; 466 unsigned long tclk, rate_err, best_err; 467 468 best_err = (unsigned long)-1; 469 470 /* Find the closest match (lower or equal to requested) */ 471 for (div1 = 1; div1 >= 0; div1--) 472 for (div2 = 7; div2 >= 0; div2--) 473 for (mul = 0; mul <= 255; mul++) { 474 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); 475 if (tclk > rate) 476 continue; 477 /* error will always be +ve */ 478 rate_err = rate - tclk; 479 if (rate_err == 0) { 480 *filter = wm8750_get_filter(parent_rate, div1); 481 *multiplier = mul; 482 *divisor1 = div1; 483 *divisor2 = div2; 484 return 0; 485 } 486 487 if (rate_err < best_err) { 488 best_err = rate_err; 489 *multiplier = mul; 490 *divisor1 = div1; 491 *divisor2 = div2; 492 } 493 } 494 495 if (best_err == (unsigned long)-1) { 496 pr_warn("%s: impossible rate %lu\n", __func__, rate); 497 return -EINVAL; 498 } 499 500 /* if we got here, it wasn't an exact match */ 501 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 502 rate - best_err); 503 504 *filter = wm8750_get_filter(parent_rate, *divisor1); 505 506 return 0; 507 } 508 509 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate, 510 u32 *multiplier, u32 *divisor1, u32 *divisor2) 511 { 512 u32 mul; 513 int div1, div2; 514 unsigned long tclk, rate_err, best_err; 515 516 best_err = (unsigned long)-1; 517 518 /* Find the closest match (lower or equal to requested) */ 519 for (div1 = 1; div1 >= 0; div1--) 520 for (div2 = 3; div2 >= 0; div2--) 521 for (mul = 0; mul <= 127; mul++) { 522 tclk = parent_rate * ((mul + 1) * 2) / 523 ((div1 + 1) * (1 << div2)); 524 if (tclk > rate) 525 continue; 526 /* error will always be +ve */ 527 rate_err = rate - tclk; 528 if (rate_err == 0) { 529 *multiplier = mul; 530 *divisor1 = div1; 531 *divisor2 = div2; 532 return 0; 533 } 534 535 if (rate_err < best_err) { 536 best_err = rate_err; 537 *multiplier = mul; 538 *divisor1 = div1; 539 *divisor2 = div2; 540 } 541 } 542 543 if (best_err == (unsigned long)-1) { 544 pr_warn("%s: impossible rate %lu\n", __func__, rate); 545 return -EINVAL; 546 } 547 548 /* if we got here, it wasn't an exact match */ 549 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 550 rate - best_err); 551 552 return 0; 553 } 554 555 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, 556 unsigned long parent_rate) 557 { 558 struct clk_pll *pll = to_clk_pll(hw); 559 u32 filter, mul, div1, div2; 560 u32 pll_val; 561 unsigned long flags = 0; 562 int ret; 563 564 /* sanity check */ 565 566 switch (pll->type) { 567 case PLL_TYPE_VT8500: 568 ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1); 569 if (!ret) 570 pll_val = VT8500_BITS_TO_VAL(mul, div1); 571 break; 572 case PLL_TYPE_WM8650: 573 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); 574 if (!ret) 575 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); 576 break; 577 case PLL_TYPE_WM8750: 578 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); 579 if (!ret) 580 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); 581 break; 582 case PLL_TYPE_WM8850: 583 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); 584 if (!ret) 585 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2); 586 break; 587 default: 588 pr_err("%s: invalid pll type\n", __func__); 589 ret = -EINVAL; 590 } 591 592 if (ret) 593 return ret; 594 595 spin_lock_irqsave(pll->lock, flags); 596 597 vt8500_pmc_wait_busy(); 598 writel(pll_val, pll->reg); 599 vt8500_pmc_wait_busy(); 600 601 spin_unlock_irqrestore(pll->lock, flags); 602 603 return 0; 604 } 605 606 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, 607 unsigned long *prate) 608 { 609 struct clk_pll *pll = to_clk_pll(hw); 610 u32 filter, mul, div1, div2; 611 long round_rate; 612 int ret; 613 614 switch (pll->type) { 615 case PLL_TYPE_VT8500: 616 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1); 617 if (!ret) 618 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); 619 break; 620 case PLL_TYPE_WM8650: 621 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); 622 if (!ret) 623 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); 624 break; 625 case PLL_TYPE_WM8750: 626 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); 627 if (!ret) 628 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); 629 break; 630 case PLL_TYPE_WM8850: 631 ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2); 632 if (!ret) 633 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); 634 break; 635 default: 636 ret = -EINVAL; 637 } 638 639 if (ret) 640 return ret; 641 642 return round_rate; 643 } 644 645 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw, 646 unsigned long parent_rate) 647 { 648 struct clk_pll *pll = to_clk_pll(hw); 649 u32 pll_val = readl(pll->reg); 650 unsigned long pll_freq; 651 652 switch (pll->type) { 653 case PLL_TYPE_VT8500: 654 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val); 655 pll_freq /= VT8500_PLL_DIV(pll_val); 656 break; 657 case PLL_TYPE_WM8650: 658 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val); 659 pll_freq /= WM8650_PLL_DIV(pll_val); 660 break; 661 case PLL_TYPE_WM8750: 662 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val); 663 pll_freq /= WM8750_PLL_DIV(pll_val); 664 break; 665 case PLL_TYPE_WM8850: 666 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val); 667 pll_freq /= WM8850_PLL_DIV(pll_val); 668 break; 669 default: 670 pll_freq = 0; 671 } 672 673 return pll_freq; 674 } 675 676 static const struct clk_ops vtwm_pll_ops = { 677 .round_rate = vtwm_pll_round_rate, 678 .set_rate = vtwm_pll_set_rate, 679 .recalc_rate = vtwm_pll_recalc_rate, 680 }; 681 682 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) 683 { 684 u32 reg; 685 struct clk_hw *hw; 686 struct clk_pll *pll_clk; 687 const char *clk_name = node->name; 688 const char *parent_name; 689 struct clk_init_data init; 690 int rc; 691 692 if (!pmc_base) 693 vtwm_set_pmc_base(); 694 695 rc = of_property_read_u32(node, "reg", ®); 696 if (WARN_ON(rc)) 697 return; 698 699 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 700 if (WARN_ON(!pll_clk)) 701 return; 702 703 pll_clk->reg = pmc_base + reg; 704 pll_clk->lock = &_lock; 705 pll_clk->type = pll_type; 706 707 of_property_read_string(node, "clock-output-names", &clk_name); 708 709 init.name = clk_name; 710 init.ops = &vtwm_pll_ops; 711 init.flags = 0; 712 parent_name = of_clk_get_parent_name(node, 0); 713 init.parent_names = &parent_name; 714 init.num_parents = 1; 715 716 pll_clk->hw.init = &init; 717 718 hw = &pll_clk->hw; 719 rc = clk_hw_register(NULL, &pll_clk->hw); 720 if (WARN_ON(rc)) { 721 kfree(pll_clk); 722 return; 723 } 724 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); 725 clk_hw_register_clkdev(hw, clk_name, NULL); 726 } 727 728 729 /* Wrappers for initialization functions */ 730 731 static void __init vt8500_pll_init(struct device_node *node) 732 { 733 vtwm_pll_clk_init(node, PLL_TYPE_VT8500); 734 } 735 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init); 736 737 static void __init wm8650_pll_init(struct device_node *node) 738 { 739 vtwm_pll_clk_init(node, PLL_TYPE_WM8650); 740 } 741 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init); 742 743 static void __init wm8750_pll_init(struct device_node *node) 744 { 745 vtwm_pll_clk_init(node, PLL_TYPE_WM8750); 746 } 747 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init); 748 749 static void __init wm8850_pll_init(struct device_node *node) 750 { 751 vtwm_pll_clk_init(node, PLL_TYPE_WM8850); 752 } 753 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init); 754