1 /* 2 * Clock implementation for VIA/Wondermedia SoC's 3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/slab.h> 19 #include <linux/bitops.h> 20 #include <linux/clkdev.h> 21 #include <linux/clk-provider.h> 22 23 /* All clocks share the same lock as none can be changed concurrently */ 24 static DEFINE_SPINLOCK(_lock); 25 26 struct clk_device { 27 struct clk_hw hw; 28 void __iomem *div_reg; 29 unsigned int div_mask; 30 void __iomem *en_reg; 31 int en_bit; 32 spinlock_t *lock; 33 }; 34 35 /* 36 * Add new PLL_TYPE_x definitions here as required. Use the first known model 37 * to support the new type as the name. 38 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and 39 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x 40 */ 41 42 #define PLL_TYPE_VT8500 0 43 #define PLL_TYPE_WM8650 1 44 #define PLL_TYPE_WM8750 2 45 #define PLL_TYPE_WM8850 3 46 47 struct clk_pll { 48 struct clk_hw hw; 49 void __iomem *reg; 50 spinlock_t *lock; 51 int type; 52 }; 53 54 static void __iomem *pmc_base; 55 56 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw) 57 58 #define VT8500_PMC_BUSY_MASK 0x18 59 60 static void vt8500_pmc_wait_busy(void) 61 { 62 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK) 63 cpu_relax(); 64 } 65 66 static int vt8500_dclk_enable(struct clk_hw *hw) 67 { 68 struct clk_device *cdev = to_clk_device(hw); 69 u32 en_val; 70 unsigned long flags = 0; 71 72 spin_lock_irqsave(cdev->lock, flags); 73 74 en_val = readl(cdev->en_reg); 75 en_val |= BIT(cdev->en_bit); 76 writel(en_val, cdev->en_reg); 77 78 spin_unlock_irqrestore(cdev->lock, flags); 79 return 0; 80 } 81 82 static void vt8500_dclk_disable(struct clk_hw *hw) 83 { 84 struct clk_device *cdev = to_clk_device(hw); 85 u32 en_val; 86 unsigned long flags = 0; 87 88 spin_lock_irqsave(cdev->lock, flags); 89 90 en_val = readl(cdev->en_reg); 91 en_val &= ~BIT(cdev->en_bit); 92 writel(en_val, cdev->en_reg); 93 94 spin_unlock_irqrestore(cdev->lock, flags); 95 } 96 97 static int vt8500_dclk_is_enabled(struct clk_hw *hw) 98 { 99 struct clk_device *cdev = to_clk_device(hw); 100 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); 101 102 return en_val ? 1 : 0; 103 } 104 105 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw, 106 unsigned long parent_rate) 107 { 108 struct clk_device *cdev = to_clk_device(hw); 109 u32 div = readl(cdev->div_reg) & cdev->div_mask; 110 111 /* Special case for SDMMC devices */ 112 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) 113 div = 64 * (div & 0x1f); 114 115 /* div == 0 is actually the highest divisor */ 116 if (div == 0) 117 div = (cdev->div_mask + 1); 118 119 return parent_rate / div; 120 } 121 122 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, 123 unsigned long *prate) 124 { 125 struct clk_device *cdev = to_clk_device(hw); 126 u32 divisor; 127 128 if (rate == 0) 129 return 0; 130 131 divisor = *prate / rate; 132 133 /* If prate / rate would be decimal, incr the divisor */ 134 if (rate * divisor < *prate) 135 divisor++; 136 137 /* 138 * If this is a request for SDMMC we have to adjust the divisor 139 * when >31 to use the fixed predivisor 140 */ 141 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 142 divisor = 64 * ((divisor / 64) + 1); 143 } 144 145 return *prate / divisor; 146 } 147 148 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 149 unsigned long parent_rate) 150 { 151 struct clk_device *cdev = to_clk_device(hw); 152 u32 divisor; 153 unsigned long flags = 0; 154 155 if (rate == 0) 156 return 0; 157 158 divisor = parent_rate / rate; 159 160 if (divisor == cdev->div_mask + 1) 161 divisor = 0; 162 163 /* SDMMC mask may need to be corrected before testing if its valid */ 164 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 165 /* 166 * Bit 5 is a fixed /64 predivisor. If the requested divisor 167 * is >31 then correct for the fixed divisor being required. 168 */ 169 divisor = 0x20 + (divisor / 64); 170 } 171 172 if (divisor > cdev->div_mask) { 173 pr_err("%s: invalid divisor for clock\n", __func__); 174 return -EINVAL; 175 } 176 177 spin_lock_irqsave(cdev->lock, flags); 178 179 vt8500_pmc_wait_busy(); 180 writel(divisor, cdev->div_reg); 181 vt8500_pmc_wait_busy(); 182 183 spin_unlock_irqrestore(cdev->lock, flags); 184 185 return 0; 186 } 187 188 189 static const struct clk_ops vt8500_gated_clk_ops = { 190 .enable = vt8500_dclk_enable, 191 .disable = vt8500_dclk_disable, 192 .is_enabled = vt8500_dclk_is_enabled, 193 }; 194 195 static const struct clk_ops vt8500_divisor_clk_ops = { 196 .round_rate = vt8500_dclk_round_rate, 197 .set_rate = vt8500_dclk_set_rate, 198 .recalc_rate = vt8500_dclk_recalc_rate, 199 }; 200 201 static const struct clk_ops vt8500_gated_divisor_clk_ops = { 202 .enable = vt8500_dclk_enable, 203 .disable = vt8500_dclk_disable, 204 .is_enabled = vt8500_dclk_is_enabled, 205 .round_rate = vt8500_dclk_round_rate, 206 .set_rate = vt8500_dclk_set_rate, 207 .recalc_rate = vt8500_dclk_recalc_rate, 208 }; 209 210 #define CLK_INIT_GATED BIT(0) 211 #define CLK_INIT_DIVISOR BIT(1) 212 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED) 213 214 static __init void vtwm_device_clk_init(struct device_node *node) 215 { 216 u32 en_reg, div_reg; 217 struct clk *clk; 218 struct clk_device *dev_clk; 219 const char *clk_name = node->name; 220 const char *parent_name; 221 struct clk_init_data init; 222 int rc; 223 int clk_init_flags = 0; 224 225 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL); 226 if (WARN_ON(!dev_clk)) 227 return; 228 229 dev_clk->lock = &_lock; 230 231 rc = of_property_read_u32(node, "enable-reg", &en_reg); 232 if (!rc) { 233 dev_clk->en_reg = pmc_base + en_reg; 234 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit); 235 if (rc) { 236 pr_err("%s: enable-bit property required for gated clock\n", 237 __func__); 238 return; 239 } 240 clk_init_flags |= CLK_INIT_GATED; 241 } 242 243 rc = of_property_read_u32(node, "divisor-reg", &div_reg); 244 if (!rc) { 245 dev_clk->div_reg = pmc_base + div_reg; 246 /* 247 * use 0x1f as the default mask since it covers 248 * almost all the clocks and reduces dts properties 249 */ 250 dev_clk->div_mask = 0x1f; 251 252 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); 253 clk_init_flags |= CLK_INIT_DIVISOR; 254 } 255 256 of_property_read_string(node, "clock-output-names", &clk_name); 257 258 switch (clk_init_flags) { 259 case CLK_INIT_GATED: 260 init.ops = &vt8500_gated_clk_ops; 261 break; 262 case CLK_INIT_DIVISOR: 263 init.ops = &vt8500_divisor_clk_ops; 264 break; 265 case CLK_INIT_GATED_DIVISOR: 266 init.ops = &vt8500_gated_divisor_clk_ops; 267 break; 268 default: 269 pr_err("%s: Invalid clock description in device tree\n", 270 __func__); 271 kfree(dev_clk); 272 return; 273 } 274 275 init.name = clk_name; 276 init.flags = 0; 277 parent_name = of_clk_get_parent_name(node, 0); 278 init.parent_names = &parent_name; 279 init.num_parents = 1; 280 281 dev_clk->hw.init = &init; 282 283 clk = clk_register(NULL, &dev_clk->hw); 284 if (WARN_ON(IS_ERR(clk))) { 285 kfree(dev_clk); 286 return; 287 } 288 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 289 clk_register_clkdev(clk, clk_name, NULL); 290 } 291 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init); 292 293 /* PLL clock related functions */ 294 295 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) 296 297 /* Helper macros for PLL_VT8500 */ 298 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1) 299 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2) 300 301 #define VT8500_BITS_TO_FREQ(r, m, d) \ 302 ((r / d) * m) 303 304 #define VT8500_BITS_TO_VAL(m, d) \ 305 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F)) 306 307 /* Helper macros for PLL_WM8650 */ 308 #define WM8650_PLL_MUL(x) (x & 0x3FF) 309 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3))) 310 311 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \ 312 (r * m / (d1 * (1 << d2))) 313 314 #define WM8650_BITS_TO_VAL(m, d1, d2) \ 315 ((d2 << 13) | (d1 << 10) | (m & 0x3FF)) 316 317 /* Helper macros for PLL_WM8750 */ 318 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1) 319 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7))) 320 321 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \ 322 (r * (m+1) / ((d1+1) * (1 << d2))) 323 324 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \ 325 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2) 326 327 /* Helper macros for PLL_WM8850 */ 328 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2) 329 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3))) 330 331 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \ 332 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2))) 333 334 #define WM8850_BITS_TO_VAL(m, d1, d2) \ 335 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2) 336 337 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, 338 u32 *multiplier, u32 *prediv) 339 { 340 unsigned long tclk; 341 342 /* sanity check */ 343 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { 344 pr_err("%s: requested rate out of range\n", __func__); 345 *multiplier = 0; 346 *prediv = 1; 347 return; 348 } 349 if (rate <= parent_rate * 31) 350 /* use the prediv to double the resolution */ 351 *prediv = 2; 352 else 353 *prediv = 1; 354 355 *multiplier = rate / (parent_rate / *prediv); 356 tclk = (parent_rate / *prediv) * *multiplier; 357 358 if (tclk != rate) 359 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, 360 rate, tclk); 361 } 362 363 static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, 364 u32 *multiplier, u32 *divisor1, u32 *divisor2) 365 { 366 u32 mul, div1, div2; 367 u32 best_mul, best_div1, best_div2; 368 unsigned long tclk, rate_err, best_err; 369 370 best_err = (unsigned long)-1; 371 372 /* Find the closest match (lower or equal to requested) */ 373 for (div1 = 5; div1 >= 3; div1--) 374 for (div2 = 3; div2 >= 0; div2--) 375 for (mul = 3; mul <= 1023; mul++) { 376 tclk = parent_rate * mul / (div1 * (1 << div2)); 377 if (tclk > rate) 378 continue; 379 /* error will always be +ve */ 380 rate_err = rate - tclk; 381 if (rate_err == 0) { 382 *multiplier = mul; 383 *divisor1 = div1; 384 *divisor2 = div2; 385 return; 386 } 387 388 if (rate_err < best_err) { 389 best_err = rate_err; 390 best_mul = mul; 391 best_div1 = div1; 392 best_div2 = div2; 393 } 394 } 395 396 /* if we got here, it wasn't an exact match */ 397 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 398 rate - best_err); 399 *multiplier = best_mul; 400 *divisor1 = best_div1; 401 *divisor2 = best_div2; 402 } 403 404 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1) 405 { 406 /* calculate frequency (MHz) after pre-divisor */ 407 u32 freq = (parent_rate / 1000000) / (divisor1 + 1); 408 409 if ((freq < 10) || (freq > 200)) 410 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", 411 __func__, freq); 412 413 if (freq >= 166) 414 return 7; 415 else if (freq >= 104) 416 return 6; 417 else if (freq >= 65) 418 return 5; 419 else if (freq >= 42) 420 return 4; 421 else if (freq >= 26) 422 return 3; 423 else if (freq >= 16) 424 return 2; 425 else if (freq >= 10) 426 return 1; 427 428 return 0; 429 } 430 431 static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate, 432 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2) 433 { 434 u32 mul, div1, div2; 435 u32 best_mul, best_div1, best_div2; 436 unsigned long tclk, rate_err, best_err; 437 438 best_err = (unsigned long)-1; 439 440 /* Find the closest match (lower or equal to requested) */ 441 for (div1 = 1; div1 >= 0; div1--) 442 for (div2 = 7; div2 >= 0; div2--) 443 for (mul = 0; mul <= 255; mul++) { 444 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); 445 if (tclk > rate) 446 continue; 447 /* error will always be +ve */ 448 rate_err = rate - tclk; 449 if (rate_err == 0) { 450 *filter = wm8750_get_filter(parent_rate, div1); 451 *multiplier = mul; 452 *divisor1 = div1; 453 *divisor2 = div2; 454 return; 455 } 456 457 if (rate_err < best_err) { 458 best_err = rate_err; 459 best_mul = mul; 460 best_div1 = div1; 461 best_div2 = div2; 462 } 463 } 464 465 /* if we got here, it wasn't an exact match */ 466 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 467 rate - best_err); 468 469 *filter = wm8750_get_filter(parent_rate, best_div1); 470 *multiplier = best_mul; 471 *divisor1 = best_div1; 472 *divisor2 = best_div2; 473 } 474 475 static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate, 476 u32 *multiplier, u32 *divisor1, u32 *divisor2) 477 { 478 u32 mul, div1, div2; 479 u32 best_mul, best_div1, best_div2; 480 unsigned long tclk, rate_err, best_err; 481 482 best_err = (unsigned long)-1; 483 484 /* Find the closest match (lower or equal to requested) */ 485 for (div1 = 1; div1 >= 0; div1--) 486 for (div2 = 3; div2 >= 0; div2--) 487 for (mul = 0; mul <= 127; mul++) { 488 tclk = parent_rate * ((mul + 1) * 2) / 489 ((div1 + 1) * (1 << div2)); 490 if (tclk > rate) 491 continue; 492 /* error will always be +ve */ 493 rate_err = rate - tclk; 494 if (rate_err == 0) { 495 *multiplier = mul; 496 *divisor1 = div1; 497 *divisor2 = div2; 498 return; 499 } 500 501 if (rate_err < best_err) { 502 best_err = rate_err; 503 best_mul = mul; 504 best_div1 = div1; 505 best_div2 = div2; 506 } 507 } 508 509 /* if we got here, it wasn't an exact match */ 510 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 511 rate - best_err); 512 513 *multiplier = best_mul; 514 *divisor1 = best_div1; 515 *divisor2 = best_div2; 516 } 517 518 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, 519 unsigned long parent_rate) 520 { 521 struct clk_pll *pll = to_clk_pll(hw); 522 u32 filter, mul, div1, div2; 523 u32 pll_val; 524 unsigned long flags = 0; 525 526 /* sanity check */ 527 528 switch (pll->type) { 529 case PLL_TYPE_VT8500: 530 vt8500_find_pll_bits(rate, parent_rate, &mul, &div1); 531 pll_val = VT8500_BITS_TO_VAL(mul, div1); 532 break; 533 case PLL_TYPE_WM8650: 534 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); 535 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); 536 break; 537 case PLL_TYPE_WM8750: 538 wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); 539 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); 540 break; 541 case PLL_TYPE_WM8850: 542 wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); 543 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2); 544 break; 545 default: 546 pr_err("%s: invalid pll type\n", __func__); 547 return 0; 548 } 549 550 spin_lock_irqsave(pll->lock, flags); 551 552 vt8500_pmc_wait_busy(); 553 writel(pll_val, pll->reg); 554 vt8500_pmc_wait_busy(); 555 556 spin_unlock_irqrestore(pll->lock, flags); 557 558 return 0; 559 } 560 561 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, 562 unsigned long *prate) 563 { 564 struct clk_pll *pll = to_clk_pll(hw); 565 u32 filter, mul, div1, div2; 566 long round_rate; 567 568 switch (pll->type) { 569 case PLL_TYPE_VT8500: 570 vt8500_find_pll_bits(rate, *prate, &mul, &div1); 571 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); 572 break; 573 case PLL_TYPE_WM8650: 574 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); 575 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); 576 break; 577 case PLL_TYPE_WM8750: 578 wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); 579 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); 580 break; 581 case PLL_TYPE_WM8850: 582 wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2); 583 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); 584 break; 585 default: 586 round_rate = 0; 587 } 588 589 return round_rate; 590 } 591 592 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw, 593 unsigned long parent_rate) 594 { 595 struct clk_pll *pll = to_clk_pll(hw); 596 u32 pll_val = readl(pll->reg); 597 unsigned long pll_freq; 598 599 switch (pll->type) { 600 case PLL_TYPE_VT8500: 601 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val); 602 pll_freq /= VT8500_PLL_DIV(pll_val); 603 break; 604 case PLL_TYPE_WM8650: 605 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val); 606 pll_freq /= WM8650_PLL_DIV(pll_val); 607 break; 608 case PLL_TYPE_WM8750: 609 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val); 610 pll_freq /= WM8750_PLL_DIV(pll_val); 611 break; 612 case PLL_TYPE_WM8850: 613 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val); 614 pll_freq /= WM8850_PLL_DIV(pll_val); 615 break; 616 default: 617 pll_freq = 0; 618 } 619 620 return pll_freq; 621 } 622 623 const struct clk_ops vtwm_pll_ops = { 624 .round_rate = vtwm_pll_round_rate, 625 .set_rate = vtwm_pll_set_rate, 626 .recalc_rate = vtwm_pll_recalc_rate, 627 }; 628 629 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) 630 { 631 u32 reg; 632 struct clk *clk; 633 struct clk_pll *pll_clk; 634 const char *clk_name = node->name; 635 const char *parent_name; 636 struct clk_init_data init; 637 int rc; 638 639 rc = of_property_read_u32(node, "reg", ®); 640 if (WARN_ON(rc)) 641 return; 642 643 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 644 if (WARN_ON(!pll_clk)) 645 return; 646 647 pll_clk->reg = pmc_base + reg; 648 pll_clk->lock = &_lock; 649 pll_clk->type = pll_type; 650 651 of_property_read_string(node, "clock-output-names", &clk_name); 652 653 init.name = clk_name; 654 init.ops = &vtwm_pll_ops; 655 init.flags = 0; 656 parent_name = of_clk_get_parent_name(node, 0); 657 init.parent_names = &parent_name; 658 init.num_parents = 1; 659 660 pll_clk->hw.init = &init; 661 662 clk = clk_register(NULL, &pll_clk->hw); 663 if (WARN_ON(IS_ERR(clk))) { 664 kfree(pll_clk); 665 return; 666 } 667 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 668 clk_register_clkdev(clk, clk_name, NULL); 669 } 670 671 672 /* Wrappers for initialization functions */ 673 674 static void __init vt8500_pll_init(struct device_node *node) 675 { 676 vtwm_pll_clk_init(node, PLL_TYPE_VT8500); 677 } 678 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init); 679 680 static void __init wm8650_pll_init(struct device_node *node) 681 { 682 vtwm_pll_clk_init(node, PLL_TYPE_WM8650); 683 } 684 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init); 685 686 static void __init wm8750_pll_init(struct device_node *node) 687 { 688 vtwm_pll_clk_init(node, PLL_TYPE_WM8750); 689 } 690 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init); 691 692 static void __init wm8850_pll_init(struct device_node *node) 693 { 694 vtwm_pll_clk_init(node, PLL_TYPE_WM8850); 695 } 696 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init); 697 698 void __init vtwm_clk_init(void __iomem *base) 699 { 700 if (!base) 701 return; 702 703 pmc_base = base; 704 705 of_clk_init(NULL); 706 } 707