1 /* 2 * Driver for IDT Versaclock 5 3 * 4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * Possible optimizations: 19 * - Use spread spectrum 20 * - Use integer divider in FOD if applicable 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/interrupt.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_platform.h> 32 #include <linux/rational.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 /* VersaClock5 registers */ 37 #define VC5_OTP_CONTROL 0x00 38 39 /* Factory-reserved register block */ 40 #define VC5_RSVD_DEVICE_ID 0x01 41 #define VC5_RSVD_ADC_GAIN_7_0 0x02 42 #define VC5_RSVD_ADC_GAIN_15_8 0x03 43 #define VC5_RSVD_ADC_OFFSET_7_0 0x04 44 #define VC5_RSVD_ADC_OFFSET_15_8 0x05 45 #define VC5_RSVD_TEMPY 0x06 46 #define VC5_RSVD_OFFSET_TBIN 0x07 47 #define VC5_RSVD_GAIN 0x08 48 #define VC5_RSVD_TEST_NP 0x09 49 #define VC5_RSVD_UNUSED 0x0a 50 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b 51 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c 52 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d 53 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e 54 #define VC5_RSVD_CLK_AMP_123 0x0f 55 56 /* Configuration register block */ 57 #define VC5_PRIM_SRC_SHDN 0x10 58 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) 59 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) 60 #define VC5_PRIM_SRC_SHDN_SP BIT(1) 61 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) 62 63 #define VC5_VCO_BAND 0x11 64 #define VC5_XTAL_X1_LOAD_CAP 0x12 65 #define VC5_XTAL_X2_LOAD_CAP 0x13 66 #define VC5_REF_DIVIDER 0x15 67 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) 68 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) 69 70 #define VC5_VCO_CTRL_AND_PREDIV 0x16 71 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) 72 73 #define VC5_FEEDBACK_INT_DIV 0x17 74 #define VC5_FEEDBACK_INT_DIV_BITS 0x18 75 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) 76 #define VC5_RC_CONTROL0 0x1e 77 #define VC5_RC_CONTROL1 0x1f 78 /* Register 0x20 is factory reserved */ 79 80 /* Output divider control for divider 1,2,3,4 */ 81 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) 82 #define VC5_OUT_DIV_CONTROL_RESET BIT(7) 83 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) 84 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) 85 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) 86 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) 87 88 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) 89 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) 90 91 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) 92 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) 93 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) 94 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) 95 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) 96 /* Registers 0x30, 0x40, 0x50 are factory reserved */ 97 98 /* Clock control register for clock 1,2 */ 99 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) 100 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) 101 102 #define VC5_CLK_OE_SHDN 0x68 103 #define VC5_CLK_OS_SHDN 0x69 104 105 #define VC5_GLOBAL_REGISTER 0x76 106 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) 107 108 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ 109 #define VC5_PLL_VCO_MIN 2500000000UL 110 #define VC5_PLL_VCO_MAX 3000000000UL 111 112 /* VC5 Input mux settings */ 113 #define VC5_MUX_IN_XIN BIT(0) 114 #define VC5_MUX_IN_CLKIN BIT(1) 115 116 /* Maximum number of clk_out supported by this driver */ 117 #define VC5_MAX_CLK_OUT_NUM 5 118 119 /* Maximum number of FODs supported by this driver */ 120 #define VC5_MAX_FOD_NUM 4 121 122 /* flags to describe chip features */ 123 /* chip has built-in oscilator */ 124 #define VC5_HAS_INTERNAL_XTAL BIT(0) 125 126 /* Supported IDT VC5 models. */ 127 enum vc5_model { 128 IDT_VC5_5P49V5923, 129 IDT_VC5_5P49V5933, 130 IDT_VC5_5P49V5935, 131 }; 132 133 /* Structure to describe features of a particular VC5 model */ 134 struct vc5_chip_info { 135 const enum vc5_model model; 136 const unsigned int clk_fod_cnt; 137 const unsigned int clk_out_cnt; 138 const u32 flags; 139 }; 140 141 struct vc5_driver_data; 142 143 struct vc5_hw_data { 144 struct clk_hw hw; 145 struct vc5_driver_data *vc5; 146 u32 div_int; 147 u32 div_frc; 148 unsigned int num; 149 }; 150 151 struct vc5_driver_data { 152 struct i2c_client *client; 153 struct regmap *regmap; 154 const struct vc5_chip_info *chip_info; 155 156 struct clk *pin_xin; 157 struct clk *pin_clkin; 158 unsigned char clk_mux_ins; 159 struct clk_hw clk_mux; 160 struct vc5_hw_data clk_pll; 161 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; 162 struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM]; 163 }; 164 165 static const char * const vc5_mux_names[] = { 166 "mux" 167 }; 168 169 static const char * const vc5_pll_names[] = { 170 "pll" 171 }; 172 173 static const char * const vc5_fod_names[] = { 174 "fod0", "fod1", "fod2", "fod3", 175 }; 176 177 static const char * const vc5_clk_out_names[] = { 178 "out0_sel_i2cb", "out1", "out2", "out3", "out4", 179 }; 180 181 /* 182 * VersaClock5 i2c regmap 183 */ 184 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) 185 { 186 /* Factory reserved regs, make them read-only */ 187 if (reg <= 0xf) 188 return false; 189 190 /* Factory reserved regs, make them read-only */ 191 if (reg == 0x14 || reg == 0x1c || reg == 0x1d) 192 return false; 193 194 return true; 195 } 196 197 static const struct regmap_config vc5_regmap_config = { 198 .reg_bits = 8, 199 .val_bits = 8, 200 .cache_type = REGCACHE_RBTREE, 201 .max_register = 0x76, 202 .writeable_reg = vc5_regmap_is_writeable, 203 }; 204 205 /* 206 * VersaClock5 input multiplexer between XTAL and CLKIN divider 207 */ 208 static unsigned char vc5_mux_get_parent(struct clk_hw *hw) 209 { 210 struct vc5_driver_data *vc5 = 211 container_of(hw, struct vc5_driver_data, clk_mux); 212 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 213 unsigned int src; 214 215 regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); 216 src &= mask; 217 218 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) 219 return 0; 220 221 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) 222 return 1; 223 224 dev_warn(&vc5->client->dev, 225 "Invalid clock input configuration (%02x)\n", src); 226 return 0; 227 } 228 229 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) 230 { 231 struct vc5_driver_data *vc5 = 232 container_of(hw, struct vc5_driver_data, clk_mux); 233 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 234 u8 src; 235 236 if ((index > 1) || !vc5->clk_mux_ins) 237 return -EINVAL; 238 239 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { 240 if (index == 0) 241 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 242 if (index == 1) 243 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 244 } else { 245 if (index != 0) 246 return -EINVAL; 247 248 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) 249 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 250 if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) 251 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 252 } 253 254 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); 255 } 256 257 static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw, 258 unsigned long parent_rate) 259 { 260 struct vc5_driver_data *vc5 = 261 container_of(hw, struct vc5_driver_data, clk_mux); 262 unsigned int prediv, div; 263 264 regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); 265 266 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 267 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) 268 return parent_rate; 269 270 regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); 271 272 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ 273 if (div & VC5_REF_DIVIDER_SEL_PREDIV2) 274 return parent_rate / 2; 275 else 276 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); 277 } 278 279 static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate, 280 unsigned long *parent_rate) 281 { 282 unsigned long idiv; 283 284 /* PLL cannot operate with input clock above 50 MHz. */ 285 if (rate > 50000000) 286 return -EINVAL; 287 288 /* CLKIN within range of PLL input, feed directly to PLL. */ 289 if (*parent_rate <= 50000000) 290 return *parent_rate; 291 292 idiv = DIV_ROUND_UP(*parent_rate, rate); 293 if (idiv > 127) 294 return -EINVAL; 295 296 return *parent_rate / idiv; 297 } 298 299 static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate, 300 unsigned long parent_rate) 301 { 302 struct vc5_driver_data *vc5 = 303 container_of(hw, struct vc5_driver_data, clk_mux); 304 unsigned long idiv; 305 u8 div; 306 307 /* CLKIN within range of PLL input, feed directly to PLL. */ 308 if (parent_rate <= 50000000) { 309 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 310 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 311 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 312 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); 313 return 0; 314 } 315 316 idiv = DIV_ROUND_UP(parent_rate, rate); 317 318 /* We have dedicated div-2 predivider. */ 319 if (idiv == 2) 320 div = VC5_REF_DIVIDER_SEL_PREDIV2; 321 else 322 div = VC5_REF_DIVIDER_REF_DIV(idiv); 323 324 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); 325 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 326 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0); 327 328 return 0; 329 } 330 331 static const struct clk_ops vc5_mux_ops = { 332 .set_parent = vc5_mux_set_parent, 333 .get_parent = vc5_mux_get_parent, 334 .recalc_rate = vc5_mux_recalc_rate, 335 .round_rate = vc5_mux_round_rate, 336 .set_rate = vc5_mux_set_rate, 337 }; 338 339 /* 340 * VersaClock5 PLL/VCO 341 */ 342 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, 343 unsigned long parent_rate) 344 { 345 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 346 struct vc5_driver_data *vc5 = hwdata->vc5; 347 u32 div_int, div_frc; 348 u8 fb[5]; 349 350 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 351 352 div_int = (fb[0] << 4) | (fb[1] >> 4); 353 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; 354 355 /* The PLL divider has 12 integer bits and 24 fractional bits */ 356 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); 357 } 358 359 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 360 unsigned long *parent_rate) 361 { 362 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 363 u32 div_int; 364 u64 div_frc; 365 366 if (rate < VC5_PLL_VCO_MIN) 367 rate = VC5_PLL_VCO_MIN; 368 if (rate > VC5_PLL_VCO_MAX) 369 rate = VC5_PLL_VCO_MAX; 370 371 /* Determine integer part, which is 12 bit wide */ 372 div_int = rate / *parent_rate; 373 if (div_int > 0xfff) 374 rate = *parent_rate * 0xfff; 375 376 /* Determine best fractional part, which is 24 bit wide */ 377 div_frc = rate % *parent_rate; 378 div_frc *= BIT(24) - 1; 379 do_div(div_frc, *parent_rate); 380 381 hwdata->div_int = div_int; 382 hwdata->div_frc = (u32)div_frc; 383 384 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); 385 } 386 387 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, 388 unsigned long parent_rate) 389 { 390 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 391 struct vc5_driver_data *vc5 = hwdata->vc5; 392 u8 fb[5]; 393 394 fb[0] = hwdata->div_int >> 4; 395 fb[1] = hwdata->div_int << 4; 396 fb[2] = hwdata->div_frc >> 16; 397 fb[3] = hwdata->div_frc >> 8; 398 fb[4] = hwdata->div_frc; 399 400 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 401 } 402 403 static const struct clk_ops vc5_pll_ops = { 404 .recalc_rate = vc5_pll_recalc_rate, 405 .round_rate = vc5_pll_round_rate, 406 .set_rate = vc5_pll_set_rate, 407 }; 408 409 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, 410 unsigned long parent_rate) 411 { 412 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 413 struct vc5_driver_data *vc5 = hwdata->vc5; 414 /* VCO frequency is divided by two before entering FOD */ 415 u32 f_in = parent_rate / 2; 416 u32 div_int, div_frc; 417 u8 od_int[2]; 418 u8 od_frc[4]; 419 420 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), 421 od_int, 2); 422 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 423 od_frc, 4); 424 425 div_int = (od_int[0] << 4) | (od_int[1] >> 4); 426 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | 427 (od_frc[2] << 6) | (od_frc[3] >> 2); 428 429 /* The PLL divider has 12 integer bits and 30 fractional bits */ 430 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 431 } 432 433 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, 434 unsigned long *parent_rate) 435 { 436 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 437 /* VCO frequency is divided by two before entering FOD */ 438 u32 f_in = *parent_rate / 2; 439 u32 div_int; 440 u64 div_frc; 441 442 /* Determine integer part, which is 12 bit wide */ 443 div_int = f_in / rate; 444 /* 445 * WARNING: The clock chip does not output signal if the integer part 446 * of the divider is 0xfff and fractional part is non-zero. 447 * Clamp the divider at 0xffe to keep the code simple. 448 */ 449 if (div_int > 0xffe) { 450 div_int = 0xffe; 451 rate = f_in / div_int; 452 } 453 454 /* Determine best fractional part, which is 30 bit wide */ 455 div_frc = f_in % rate; 456 div_frc <<= 24; 457 do_div(div_frc, rate); 458 459 hwdata->div_int = div_int; 460 hwdata->div_frc = (u32)div_frc; 461 462 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 463 } 464 465 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, 466 unsigned long parent_rate) 467 { 468 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 469 struct vc5_driver_data *vc5 = hwdata->vc5; 470 u8 data[14] = { 471 hwdata->div_frc >> 22, hwdata->div_frc >> 14, 472 hwdata->div_frc >> 6, hwdata->div_frc << 2, 473 0, 0, 0, 0, 0, 474 0, 0, 475 hwdata->div_int >> 4, hwdata->div_int << 4, 476 0 477 }; 478 479 regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 480 data, 14); 481 482 /* 483 * Toggle magic bit in undocumented register for unknown reason. 484 * This is what the IDT timing commander tool does and the chip 485 * datasheet somewhat implies this is needed, but the register 486 * and the bit is not documented. 487 */ 488 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 489 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0); 490 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 491 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 492 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 493 return 0; 494 } 495 496 static const struct clk_ops vc5_fod_ops = { 497 .recalc_rate = vc5_fod_recalc_rate, 498 .round_rate = vc5_fod_round_rate, 499 .set_rate = vc5_fod_set_rate, 500 }; 501 502 static int vc5_clk_out_prepare(struct clk_hw *hw) 503 { 504 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 505 struct vc5_driver_data *vc5 = hwdata->vc5; 506 507 /* Enable the clock buffer */ 508 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 509 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 510 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 511 return 0; 512 } 513 514 static void vc5_clk_out_unprepare(struct clk_hw *hw) 515 { 516 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 517 struct vc5_driver_data *vc5 = hwdata->vc5; 518 519 /* Enable the clock buffer */ 520 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 521 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0); 522 } 523 524 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) 525 { 526 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 527 struct vc5_driver_data *vc5 = hwdata->vc5; 528 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 529 VC5_OUT_DIV_CONTROL_SEL_EXT | 530 VC5_OUT_DIV_CONTROL_EN_FOD; 531 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | 532 VC5_OUT_DIV_CONTROL_EN_FOD; 533 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 534 VC5_OUT_DIV_CONTROL_SEL_EXT; 535 unsigned int src; 536 537 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 538 src &= mask; 539 540 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) 541 return 0; 542 543 if (src == extclk) 544 return 1; 545 546 dev_warn(&vc5->client->dev, 547 "Invalid clock output configuration (%02x)\n", src); 548 return 0; 549 } 550 551 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) 552 { 553 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 554 struct vc5_driver_data *vc5 = hwdata->vc5; 555 const u8 mask = VC5_OUT_DIV_CONTROL_RESET | 556 VC5_OUT_DIV_CONTROL_SELB_NORM | 557 VC5_OUT_DIV_CONTROL_SEL_EXT | 558 VC5_OUT_DIV_CONTROL_EN_FOD; 559 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 560 VC5_OUT_DIV_CONTROL_SEL_EXT; 561 u8 src = VC5_OUT_DIV_CONTROL_RESET; 562 563 if (index == 0) 564 src |= VC5_OUT_DIV_CONTROL_EN_FOD; 565 else 566 src |= extclk; 567 568 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), 569 mask, src); 570 } 571 572 static const struct clk_ops vc5_clk_out_ops = { 573 .prepare = vc5_clk_out_prepare, 574 .unprepare = vc5_clk_out_unprepare, 575 .set_parent = vc5_clk_out_set_parent, 576 .get_parent = vc5_clk_out_get_parent, 577 }; 578 579 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, 580 void *data) 581 { 582 struct vc5_driver_data *vc5 = data; 583 unsigned int idx = clkspec->args[0]; 584 585 if (idx >= vc5->chip_info->clk_out_cnt) 586 return ERR_PTR(-EINVAL); 587 588 return &vc5->clk_out[idx].hw; 589 } 590 591 static int vc5_map_index_to_output(const enum vc5_model model, 592 const unsigned int n) 593 { 594 switch (model) { 595 case IDT_VC5_5P49V5933: 596 return (n == 0) ? 0 : 3; 597 case IDT_VC5_5P49V5923: 598 case IDT_VC5_5P49V5935: 599 default: 600 return n; 601 } 602 } 603 604 static const struct of_device_id clk_vc5_of_match[]; 605 606 static int vc5_probe(struct i2c_client *client, 607 const struct i2c_device_id *id) 608 { 609 struct vc5_driver_data *vc5; 610 struct clk_init_data init; 611 const char *parent_names[2]; 612 unsigned int n, idx = 0; 613 int ret; 614 615 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); 616 if (vc5 == NULL) 617 return -ENOMEM; 618 619 i2c_set_clientdata(client, vc5); 620 vc5->client = client; 621 vc5->chip_info = of_device_get_match_data(&client->dev); 622 623 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); 624 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) 625 return -EPROBE_DEFER; 626 627 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); 628 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) 629 return -EPROBE_DEFER; 630 631 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); 632 if (IS_ERR(vc5->regmap)) { 633 dev_err(&client->dev, "failed to allocate register map\n"); 634 return PTR_ERR(vc5->regmap); 635 } 636 637 /* Register clock input mux */ 638 memset(&init, 0, sizeof(init)); 639 640 if (!IS_ERR(vc5->pin_xin)) { 641 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 642 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 643 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { 644 vc5->pin_xin = clk_register_fixed_rate(&client->dev, 645 "internal-xtal", NULL, 646 0, 25000000); 647 if (IS_ERR(vc5->pin_xin)) 648 return PTR_ERR(vc5->pin_xin); 649 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 650 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 651 } 652 653 if (!IS_ERR(vc5->pin_clkin)) { 654 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; 655 parent_names[init.num_parents++] = 656 __clk_get_name(vc5->pin_clkin); 657 } 658 659 if (!init.num_parents) { 660 dev_err(&client->dev, "no input clock specified!\n"); 661 return -EINVAL; 662 } 663 664 init.name = vc5_mux_names[0]; 665 init.ops = &vc5_mux_ops; 666 init.flags = 0; 667 init.parent_names = parent_names; 668 vc5->clk_mux.init = &init; 669 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); 670 if (ret) { 671 dev_err(&client->dev, "unable to register %s\n", init.name); 672 goto err_clk; 673 } 674 675 /* Register PLL */ 676 memset(&init, 0, sizeof(init)); 677 init.name = vc5_pll_names[0]; 678 init.ops = &vc5_pll_ops; 679 init.flags = CLK_SET_RATE_PARENT; 680 init.parent_names = vc5_mux_names; 681 init.num_parents = 1; 682 vc5->clk_pll.num = 0; 683 vc5->clk_pll.vc5 = vc5; 684 vc5->clk_pll.hw.init = &init; 685 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); 686 if (ret) { 687 dev_err(&client->dev, "unable to register %s\n", init.name); 688 goto err_clk; 689 } 690 691 /* Register FODs */ 692 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { 693 idx = vc5_map_index_to_output(vc5->chip_info->model, n); 694 memset(&init, 0, sizeof(init)); 695 init.name = vc5_fod_names[idx]; 696 init.ops = &vc5_fod_ops; 697 init.flags = CLK_SET_RATE_PARENT; 698 init.parent_names = vc5_pll_names; 699 init.num_parents = 1; 700 vc5->clk_fod[n].num = idx; 701 vc5->clk_fod[n].vc5 = vc5; 702 vc5->clk_fod[n].hw.init = &init; 703 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); 704 if (ret) { 705 dev_err(&client->dev, "unable to register %s\n", 706 init.name); 707 goto err_clk; 708 } 709 } 710 711 /* Register MUX-connected OUT0_I2C_SELB output */ 712 memset(&init, 0, sizeof(init)); 713 init.name = vc5_clk_out_names[0]; 714 init.ops = &vc5_clk_out_ops; 715 init.flags = CLK_SET_RATE_PARENT; 716 init.parent_names = vc5_mux_names; 717 init.num_parents = 1; 718 vc5->clk_out[0].num = idx; 719 vc5->clk_out[0].vc5 = vc5; 720 vc5->clk_out[0].hw.init = &init; 721 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); 722 if (ret) { 723 dev_err(&client->dev, "unable to register %s\n", 724 init.name); 725 goto err_clk; 726 } 727 728 /* Register FOD-connected OUTx outputs */ 729 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { 730 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1); 731 parent_names[0] = vc5_fod_names[idx]; 732 if (n == 1) 733 parent_names[1] = vc5_mux_names[0]; 734 else 735 parent_names[1] = vc5_clk_out_names[n - 1]; 736 737 memset(&init, 0, sizeof(init)); 738 init.name = vc5_clk_out_names[idx + 1]; 739 init.ops = &vc5_clk_out_ops; 740 init.flags = CLK_SET_RATE_PARENT; 741 init.parent_names = parent_names; 742 init.num_parents = 2; 743 vc5->clk_out[n].num = idx; 744 vc5->clk_out[n].vc5 = vc5; 745 vc5->clk_out[n].hw.init = &init; 746 ret = devm_clk_hw_register(&client->dev, 747 &vc5->clk_out[n].hw); 748 if (ret) { 749 dev_err(&client->dev, "unable to register %s\n", 750 init.name); 751 goto err_clk; 752 } 753 } 754 755 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); 756 if (ret) { 757 dev_err(&client->dev, "unable to add clk provider\n"); 758 goto err_clk; 759 } 760 761 return 0; 762 763 err_clk: 764 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 765 clk_unregister_fixed_rate(vc5->pin_xin); 766 return ret; 767 } 768 769 static int vc5_remove(struct i2c_client *client) 770 { 771 struct vc5_driver_data *vc5 = i2c_get_clientdata(client); 772 773 of_clk_del_provider(client->dev.of_node); 774 775 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 776 clk_unregister_fixed_rate(vc5->pin_xin); 777 778 return 0; 779 } 780 781 static const struct vc5_chip_info idt_5p49v5923_info = { 782 .model = IDT_VC5_5P49V5923, 783 .clk_fod_cnt = 2, 784 .clk_out_cnt = 3, 785 .flags = 0, 786 }; 787 788 static const struct vc5_chip_info idt_5p49v5933_info = { 789 .model = IDT_VC5_5P49V5933, 790 .clk_fod_cnt = 2, 791 .clk_out_cnt = 3, 792 .flags = VC5_HAS_INTERNAL_XTAL, 793 }; 794 795 static const struct vc5_chip_info idt_5p49v5935_info = { 796 .model = IDT_VC5_5P49V5935, 797 .clk_fod_cnt = 4, 798 .clk_out_cnt = 5, 799 .flags = VC5_HAS_INTERNAL_XTAL, 800 }; 801 802 static const struct i2c_device_id vc5_id[] = { 803 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 }, 804 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, 805 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 }, 806 { } 807 }; 808 MODULE_DEVICE_TABLE(i2c, vc5_id); 809 810 static const struct of_device_id clk_vc5_of_match[] = { 811 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info }, 812 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, 813 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, 814 { }, 815 }; 816 MODULE_DEVICE_TABLE(of, clk_vc5_of_match); 817 818 static struct i2c_driver vc5_driver = { 819 .driver = { 820 .name = "vc5", 821 .of_match_table = clk_vc5_of_match, 822 }, 823 .probe = vc5_probe, 824 .remove = vc5_remove, 825 .id_table = vc5_id, 826 }; 827 module_i2c_driver(vc5_driver); 828 829 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); 830 MODULE_DESCRIPTION("IDT VersaClock 5 driver"); 831 MODULE_LICENSE("GPL"); 832