1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for IDT Versaclock 5 4 * 5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 /* 9 * Possible optimizations: 10 * - Use spread spectrum 11 * - Use integer divider in FOD if applicable 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include <dt-bindings/clock/versaclock.h> 28 29 /* VersaClock5 registers */ 30 #define VC5_OTP_CONTROL 0x00 31 32 /* Factory-reserved register block */ 33 #define VC5_RSVD_DEVICE_ID 0x01 34 #define VC5_RSVD_ADC_GAIN_7_0 0x02 35 #define VC5_RSVD_ADC_GAIN_15_8 0x03 36 #define VC5_RSVD_ADC_OFFSET_7_0 0x04 37 #define VC5_RSVD_ADC_OFFSET_15_8 0x05 38 #define VC5_RSVD_TEMPY 0x06 39 #define VC5_RSVD_OFFSET_TBIN 0x07 40 #define VC5_RSVD_GAIN 0x08 41 #define VC5_RSVD_TEST_NP 0x09 42 #define VC5_RSVD_UNUSED 0x0a 43 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b 44 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c 45 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d 46 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e 47 #define VC5_RSVD_CLK_AMP_123 0x0f 48 49 /* Configuration register block */ 50 #define VC5_PRIM_SRC_SHDN 0x10 51 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) 52 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) 53 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) 54 #define VC5_PRIM_SRC_SHDN_SP BIT(1) 55 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) 56 57 #define VC5_VCO_BAND 0x11 58 #define VC5_XTAL_X1_LOAD_CAP 0x12 59 #define VC5_XTAL_X2_LOAD_CAP 0x13 60 #define VC5_REF_DIVIDER 0x15 61 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) 62 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) 63 64 #define VC5_VCO_CTRL_AND_PREDIV 0x16 65 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) 66 67 #define VC5_FEEDBACK_INT_DIV 0x17 68 #define VC5_FEEDBACK_INT_DIV_BITS 0x18 69 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) 70 #define VC5_RC_CONTROL0 0x1e 71 #define VC5_RC_CONTROL1 0x1f 72 73 /* These registers are named "Unused Factory Reserved Registers" */ 74 #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10)) 75 #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */ 76 77 /* Output divider control for divider 1,2,3,4 */ 78 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) 79 #define VC5_OUT_DIV_CONTROL_RESET BIT(7) 80 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) 81 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) 82 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) 83 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) 84 85 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) 86 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) 87 88 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) 89 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) 90 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) 91 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) 92 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) 93 94 /* Clock control register for clock 1,2 */ 95 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) 96 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 97 #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) 98 99 #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL) 100 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) 101 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33) 102 #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) 103 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) 104 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) 105 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25) 106 107 #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 108 #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 109 #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 110 #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 111 #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 112 #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0 113 #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 114 #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 115 #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 116 #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 117 #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 118 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) 119 120 #define VC5_CLK_OE_SHDN 0x68 121 #define VC5_CLK_OS_SHDN 0x69 122 123 #define VC5_GLOBAL_REGISTER 0x76 124 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) 125 126 /* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */ 127 #define VC5_PLL_VCO_MIN 2500000000UL 128 129 /* VC5 Input mux settings */ 130 #define VC5_MUX_IN_XIN BIT(0) 131 #define VC5_MUX_IN_CLKIN BIT(1) 132 133 /* Maximum number of clk_out supported by this driver */ 134 #define VC5_MAX_CLK_OUT_NUM 5 135 136 /* Maximum number of FODs supported by this driver */ 137 #define VC5_MAX_FOD_NUM 4 138 139 /* flags to describe chip features */ 140 /* chip has built-in oscilator */ 141 #define VC5_HAS_INTERNAL_XTAL BIT(0) 142 /* chip has PFD requency doubler */ 143 #define VC5_HAS_PFD_FREQ_DBL BIT(1) 144 /* chip has bits to disable FOD sync */ 145 #define VC5_HAS_BYPASS_SYNC_BIT BIT(2) 146 147 /* Supported IDT VC5 models. */ 148 enum vc5_model { 149 IDT_VC5_5P49V5923, 150 IDT_VC5_5P49V5925, 151 IDT_VC5_5P49V5933, 152 IDT_VC5_5P49V5935, 153 IDT_VC6_5P49V60, 154 IDT_VC6_5P49V6901, 155 IDT_VC6_5P49V6965, 156 IDT_VC6_5P49V6975, 157 }; 158 159 /* Structure to describe features of a particular VC5 model */ 160 struct vc5_chip_info { 161 const enum vc5_model model; 162 const unsigned int clk_fod_cnt; 163 const unsigned int clk_out_cnt; 164 const u32 flags; 165 const unsigned long vco_max; 166 }; 167 168 struct vc5_driver_data; 169 170 struct vc5_hw_data { 171 struct clk_hw hw; 172 struct vc5_driver_data *vc5; 173 u32 div_int; 174 u32 div_frc; 175 unsigned int num; 176 }; 177 178 struct vc5_out_data { 179 struct clk_hw hw; 180 struct vc5_driver_data *vc5; 181 unsigned int num; 182 unsigned int clk_output_cfg0; 183 unsigned int clk_output_cfg0_mask; 184 }; 185 186 struct vc5_driver_data { 187 struct i2c_client *client; 188 struct regmap *regmap; 189 const struct vc5_chip_info *chip_info; 190 191 struct clk *pin_xin; 192 struct clk *pin_clkin; 193 unsigned char clk_mux_ins; 194 struct clk_hw clk_mux; 195 struct clk_hw clk_mul; 196 struct clk_hw clk_pfd; 197 struct vc5_hw_data clk_pll; 198 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; 199 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM]; 200 }; 201 202 /* 203 * VersaClock5 i2c regmap 204 */ 205 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) 206 { 207 /* Factory reserved regs, make them read-only */ 208 if (reg <= 0xf) 209 return false; 210 211 /* Factory reserved regs, make them read-only */ 212 if (reg == 0x14 || reg == 0x1c || reg == 0x1d) 213 return false; 214 215 return true; 216 } 217 218 static const struct regmap_config vc5_regmap_config = { 219 .reg_bits = 8, 220 .val_bits = 8, 221 .cache_type = REGCACHE_RBTREE, 222 .max_register = 0x76, 223 .writeable_reg = vc5_regmap_is_writeable, 224 }; 225 226 /* 227 * VersaClock5 input multiplexer between XTAL and CLKIN divider 228 */ 229 static unsigned char vc5_mux_get_parent(struct clk_hw *hw) 230 { 231 struct vc5_driver_data *vc5 = 232 container_of(hw, struct vc5_driver_data, clk_mux); 233 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 234 unsigned int src; 235 int ret; 236 237 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); 238 if (ret) 239 return 0; 240 241 src &= mask; 242 243 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) 244 return 0; 245 246 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) 247 return 1; 248 249 dev_warn(&vc5->client->dev, 250 "Invalid clock input configuration (%02x)\n", src); 251 return 0; 252 } 253 254 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) 255 { 256 struct vc5_driver_data *vc5 = 257 container_of(hw, struct vc5_driver_data, clk_mux); 258 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 259 u8 src; 260 261 if ((index > 1) || !vc5->clk_mux_ins) 262 return -EINVAL; 263 264 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { 265 if (index == 0) 266 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 267 if (index == 1) 268 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 269 } else { 270 if (index != 0) 271 return -EINVAL; 272 273 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) 274 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 275 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) 276 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 277 else /* Invalid; should have been caught by vc5_probe() */ 278 return -EINVAL; 279 } 280 281 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); 282 } 283 284 static const struct clk_ops vc5_mux_ops = { 285 .determine_rate = clk_hw_determine_rate_no_reparent, 286 .set_parent = vc5_mux_set_parent, 287 .get_parent = vc5_mux_get_parent, 288 }; 289 290 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, 291 unsigned long parent_rate) 292 { 293 struct vc5_driver_data *vc5 = 294 container_of(hw, struct vc5_driver_data, clk_mul); 295 unsigned int premul; 296 int ret; 297 298 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); 299 if (ret) 300 return 0; 301 302 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) 303 parent_rate *= 2; 304 305 return parent_rate; 306 } 307 308 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, 309 unsigned long *parent_rate) 310 { 311 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) 312 return rate; 313 else 314 return -EINVAL; 315 } 316 317 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, 318 unsigned long parent_rate) 319 { 320 struct vc5_driver_data *vc5 = 321 container_of(hw, struct vc5_driver_data, clk_mul); 322 u32 mask; 323 324 if ((parent_rate * 2) == rate) 325 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; 326 else 327 mask = 0; 328 329 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, 330 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, 331 mask); 332 } 333 334 static const struct clk_ops vc5_dbl_ops = { 335 .recalc_rate = vc5_dbl_recalc_rate, 336 .round_rate = vc5_dbl_round_rate, 337 .set_rate = vc5_dbl_set_rate, 338 }; 339 340 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, 341 unsigned long parent_rate) 342 { 343 struct vc5_driver_data *vc5 = 344 container_of(hw, struct vc5_driver_data, clk_pfd); 345 unsigned int prediv, div; 346 int ret; 347 348 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); 349 if (ret) 350 return 0; 351 352 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 353 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) 354 return parent_rate; 355 356 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); 357 if (ret) 358 return 0; 359 360 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ 361 if (div & VC5_REF_DIVIDER_SEL_PREDIV2) 362 return parent_rate / 2; 363 else 364 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); 365 } 366 367 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, 368 unsigned long *parent_rate) 369 { 370 unsigned long idiv; 371 372 /* PLL cannot operate with input clock above 50 MHz. */ 373 if (rate > 50000000) 374 return -EINVAL; 375 376 /* CLKIN within range of PLL input, feed directly to PLL. */ 377 if (*parent_rate <= 50000000) 378 return *parent_rate; 379 380 idiv = DIV_ROUND_UP(*parent_rate, rate); 381 if (idiv > 127) 382 return -EINVAL; 383 384 return *parent_rate / idiv; 385 } 386 387 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 388 unsigned long parent_rate) 389 { 390 struct vc5_driver_data *vc5 = 391 container_of(hw, struct vc5_driver_data, clk_pfd); 392 unsigned long idiv; 393 int ret; 394 u8 div; 395 396 /* CLKIN within range of PLL input, feed directly to PLL. */ 397 if (parent_rate <= 50000000) { 398 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 399 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 400 if (ret) 401 return ret; 402 403 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); 404 } 405 406 idiv = DIV_ROUND_UP(parent_rate, rate); 407 408 /* We have dedicated div-2 predivider. */ 409 if (idiv == 2) 410 div = VC5_REF_DIVIDER_SEL_PREDIV2; 411 else 412 div = VC5_REF_DIVIDER_REF_DIV(idiv); 413 414 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); 415 if (ret) 416 return ret; 417 418 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 419 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 420 } 421 422 static const struct clk_ops vc5_pfd_ops = { 423 .recalc_rate = vc5_pfd_recalc_rate, 424 .round_rate = vc5_pfd_round_rate, 425 .set_rate = vc5_pfd_set_rate, 426 }; 427 428 /* 429 * VersaClock5 PLL/VCO 430 */ 431 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, 432 unsigned long parent_rate) 433 { 434 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 435 struct vc5_driver_data *vc5 = hwdata->vc5; 436 u32 div_int, div_frc; 437 u8 fb[5]; 438 439 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 440 441 div_int = (fb[0] << 4) | (fb[1] >> 4); 442 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; 443 444 /* The PLL divider has 12 integer bits and 24 fractional bits */ 445 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); 446 } 447 448 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 449 unsigned long *parent_rate) 450 { 451 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 452 struct vc5_driver_data *vc5 = hwdata->vc5; 453 u32 div_int; 454 u64 div_frc; 455 456 rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); 457 458 /* Determine integer part, which is 12 bit wide */ 459 div_int = rate / *parent_rate; 460 if (div_int > 0xfff) 461 rate = *parent_rate * 0xfff; 462 463 /* Determine best fractional part, which is 24 bit wide */ 464 div_frc = rate % *parent_rate; 465 div_frc *= BIT(24) - 1; 466 do_div(div_frc, *parent_rate); 467 468 hwdata->div_int = div_int; 469 hwdata->div_frc = (u32)div_frc; 470 471 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); 472 } 473 474 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, 475 unsigned long parent_rate) 476 { 477 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 478 struct vc5_driver_data *vc5 = hwdata->vc5; 479 u8 fb[5]; 480 481 fb[0] = hwdata->div_int >> 4; 482 fb[1] = hwdata->div_int << 4; 483 fb[2] = hwdata->div_frc >> 16; 484 fb[3] = hwdata->div_frc >> 8; 485 fb[4] = hwdata->div_frc; 486 487 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 488 } 489 490 static const struct clk_ops vc5_pll_ops = { 491 .recalc_rate = vc5_pll_recalc_rate, 492 .round_rate = vc5_pll_round_rate, 493 .set_rate = vc5_pll_set_rate, 494 }; 495 496 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, 497 unsigned long parent_rate) 498 { 499 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 500 struct vc5_driver_data *vc5 = hwdata->vc5; 501 /* VCO frequency is divided by two before entering FOD */ 502 u32 f_in = parent_rate / 2; 503 u32 div_int, div_frc; 504 u8 od_int[2]; 505 u8 od_frc[4]; 506 507 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), 508 od_int, 2); 509 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 510 od_frc, 4); 511 512 div_int = (od_int[0] << 4) | (od_int[1] >> 4); 513 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | 514 (od_frc[2] << 6) | (od_frc[3] >> 2); 515 516 /* Avoid division by zero if the output is not configured. */ 517 if (div_int == 0 && div_frc == 0) 518 return 0; 519 520 /* The PLL divider has 12 integer bits and 30 fractional bits */ 521 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 522 } 523 524 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, 525 unsigned long *parent_rate) 526 { 527 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 528 /* VCO frequency is divided by two before entering FOD */ 529 u32 f_in = *parent_rate / 2; 530 u32 div_int; 531 u64 div_frc; 532 533 /* Determine integer part, which is 12 bit wide */ 534 div_int = f_in / rate; 535 /* 536 * WARNING: The clock chip does not output signal if the integer part 537 * of the divider is 0xfff and fractional part is non-zero. 538 * Clamp the divider at 0xffe to keep the code simple. 539 */ 540 if (div_int > 0xffe) { 541 div_int = 0xffe; 542 rate = f_in / div_int; 543 } 544 545 /* Determine best fractional part, which is 30 bit wide */ 546 div_frc = f_in % rate; 547 div_frc <<= 24; 548 do_div(div_frc, rate); 549 550 hwdata->div_int = div_int; 551 hwdata->div_frc = (u32)div_frc; 552 553 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 554 } 555 556 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, 557 unsigned long parent_rate) 558 { 559 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 560 struct vc5_driver_data *vc5 = hwdata->vc5; 561 u8 data[14] = { 562 hwdata->div_frc >> 22, hwdata->div_frc >> 14, 563 hwdata->div_frc >> 6, hwdata->div_frc << 2, 564 0, 0, 0, 0, 0, 565 0, 0, 566 hwdata->div_int >> 4, hwdata->div_int << 4, 567 0 568 }; 569 int ret; 570 571 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 572 data, 14); 573 if (ret) 574 return ret; 575 576 /* 577 * Toggle magic bit in undocumented register for unknown reason. 578 * This is what the IDT timing commander tool does and the chip 579 * datasheet somewhat implies this is needed, but the register 580 * and the bit is not documented. 581 */ 582 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 583 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 584 if (ret) 585 return ret; 586 587 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 588 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 589 } 590 591 static const struct clk_ops vc5_fod_ops = { 592 .recalc_rate = vc5_fod_recalc_rate, 593 .round_rate = vc5_fod_round_rate, 594 .set_rate = vc5_fod_set_rate, 595 }; 596 597 static int vc5_clk_out_prepare(struct clk_hw *hw) 598 { 599 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 600 struct vc5_driver_data *vc5 = hwdata->vc5; 601 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 602 VC5_OUT_DIV_CONTROL_SEL_EXT | 603 VC5_OUT_DIV_CONTROL_EN_FOD; 604 unsigned int src; 605 int ret; 606 607 /* 608 * When enabling a FOD, all currently enabled FODs are briefly 609 * stopped in order to synchronize all of them. This causes a clock 610 * disruption to any unrelated chips that might be already using 611 * other clock outputs. Bypass the sync feature to avoid the issue, 612 * which is possible on the VersaClock 6E family via reserved 613 * registers. 614 */ 615 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { 616 ret = regmap_set_bits(vc5->regmap, 617 VC5_RESERVED_X0(hwdata->num), 618 VC5_RESERVED_X0_BYPASS_SYNC); 619 if (ret) 620 return ret; 621 } 622 623 /* 624 * If the input mux is disabled, enable it first and 625 * select source from matching FOD. 626 */ 627 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 628 if (ret) 629 return ret; 630 631 if ((src & mask) == 0) { 632 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD; 633 ret = regmap_update_bits(vc5->regmap, 634 VC5_OUT_DIV_CONTROL(hwdata->num), 635 mask | VC5_OUT_DIV_CONTROL_RESET, src); 636 if (ret) 637 return ret; 638 } 639 640 /* Enable the clock buffer */ 641 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 642 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 643 if (ret) 644 return ret; 645 646 if (hwdata->clk_output_cfg0_mask) { 647 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n", 648 hwdata->num, hwdata->clk_output_cfg0_mask, 649 hwdata->clk_output_cfg0); 650 651 ret = regmap_update_bits(vc5->regmap, 652 VC5_CLK_OUTPUT_CFG(hwdata->num, 0), 653 hwdata->clk_output_cfg0_mask, 654 hwdata->clk_output_cfg0); 655 if (ret) 656 return ret; 657 } 658 659 return 0; 660 } 661 662 static void vc5_clk_out_unprepare(struct clk_hw *hw) 663 { 664 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 665 struct vc5_driver_data *vc5 = hwdata->vc5; 666 667 /* Disable the clock buffer */ 668 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 669 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 670 } 671 672 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) 673 { 674 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 675 struct vc5_driver_data *vc5 = hwdata->vc5; 676 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 677 VC5_OUT_DIV_CONTROL_SEL_EXT | 678 VC5_OUT_DIV_CONTROL_EN_FOD; 679 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | 680 VC5_OUT_DIV_CONTROL_EN_FOD; 681 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 682 VC5_OUT_DIV_CONTROL_SEL_EXT; 683 unsigned int src; 684 int ret; 685 686 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 687 if (ret) 688 return 0; 689 690 src &= mask; 691 692 if (src == 0) /* Input mux set to DISABLED */ 693 return 0; 694 695 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) 696 return 0; 697 698 if (src == extclk) 699 return 1; 700 701 dev_warn(&vc5->client->dev, 702 "Invalid clock output configuration (%02x)\n", src); 703 return 0; 704 } 705 706 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) 707 { 708 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 709 struct vc5_driver_data *vc5 = hwdata->vc5; 710 const u8 mask = VC5_OUT_DIV_CONTROL_RESET | 711 VC5_OUT_DIV_CONTROL_SELB_NORM | 712 VC5_OUT_DIV_CONTROL_SEL_EXT | 713 VC5_OUT_DIV_CONTROL_EN_FOD; 714 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 715 VC5_OUT_DIV_CONTROL_SEL_EXT; 716 u8 src = VC5_OUT_DIV_CONTROL_RESET; 717 718 if (index == 0) 719 src |= VC5_OUT_DIV_CONTROL_EN_FOD; 720 else 721 src |= extclk; 722 723 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), 724 mask, src); 725 } 726 727 static const struct clk_ops vc5_clk_out_ops = { 728 .prepare = vc5_clk_out_prepare, 729 .unprepare = vc5_clk_out_unprepare, 730 .determine_rate = clk_hw_determine_rate_no_reparent, 731 .set_parent = vc5_clk_out_set_parent, 732 .get_parent = vc5_clk_out_get_parent, 733 }; 734 735 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, 736 void *data) 737 { 738 struct vc5_driver_data *vc5 = data; 739 unsigned int idx = clkspec->args[0]; 740 741 if (idx >= vc5->chip_info->clk_out_cnt) 742 return ERR_PTR(-EINVAL); 743 744 return &vc5->clk_out[idx].hw; 745 } 746 747 static int vc5_map_index_to_output(const enum vc5_model model, 748 const unsigned int n) 749 { 750 switch (model) { 751 case IDT_VC5_5P49V5933: 752 return (n == 0) ? 0 : 3; 753 case IDT_VC5_5P49V5923: 754 case IDT_VC5_5P49V5925: 755 case IDT_VC5_5P49V5935: 756 case IDT_VC6_5P49V6901: 757 case IDT_VC6_5P49V6965: 758 case IDT_VC6_5P49V6975: 759 default: 760 return n; 761 } 762 } 763 764 static int vc5_update_mode(struct device_node *np_output, 765 struct vc5_out_data *clk_out) 766 { 767 u32 value; 768 769 if (!of_property_read_u32(np_output, "idt,mode", &value)) { 770 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK; 771 switch (value) { 772 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL: 773 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS: 774 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33: 775 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS: 776 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2: 777 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD: 778 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25: 779 clk_out->clk_output_cfg0 |= 780 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT; 781 break; 782 default: 783 return -EINVAL; 784 } 785 } 786 return 0; 787 } 788 789 static int vc5_update_power(struct device_node *np_output, 790 struct vc5_out_data *clk_out) 791 { 792 u32 value; 793 794 if (!of_property_read_u32(np_output, "idt,voltage-microvolt", 795 &value)) { 796 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK; 797 switch (value) { 798 case 1800000: 799 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18; 800 break; 801 case 2500000: 802 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25; 803 break; 804 case 3300000: 805 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33; 806 break; 807 default: 808 return -EINVAL; 809 } 810 } 811 return 0; 812 } 813 814 static int vc5_map_cap_value(u32 femtofarads) 815 { 816 int mapped_value; 817 818 /* 819 * The datasheet explicitly states 9000 - 25000 with 0.5pF 820 * steps, but the Programmer's guide shows the steps are 0.430pF. 821 * After getting feedback from Renesas, the .5pF steps were the 822 * goal, but 430nF was the actual values. 823 * Because of this, the actual range goes to 22760 instead of 25000 824 */ 825 if (femtofarads < 9000 || femtofarads > 22760) 826 return -EINVAL; 827 828 /* 829 * The Programmer's guide shows XTAL[5:0] but in reality, 830 * XTAL[0] and XTAL[1] are both LSB which makes the math 831 * strange. With clarfication from Renesas, setting the 832 * values should be simpler by ignoring XTAL[0] 833 */ 834 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430); 835 836 /* 837 * Since the calculation ignores XTAL[0], there is one 838 * special case where mapped_value = 32. In reality, this means 839 * the real mapped value should be 111111b. In other cases, 840 * the mapped_value needs to be shifted 1 to the left. 841 */ 842 if (mapped_value > 31) 843 mapped_value = 0x3f; 844 else 845 mapped_value <<= 1; 846 847 return mapped_value; 848 } 849 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5) 850 { 851 u32 value; 852 int mapped_value; 853 int ret; 854 855 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value)) 856 return 0; 857 858 mapped_value = vc5_map_cap_value(value); 859 if (mapped_value < 0) 860 return mapped_value; 861 862 /* 863 * The mapped_value is really the high 6 bits of 864 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so 865 * shift the value 2 places. 866 */ 867 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, 868 mapped_value << 2); 869 if (ret) 870 return ret; 871 872 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, 873 mapped_value << 2); 874 } 875 876 static int vc5_update_slew(struct device_node *np_output, 877 struct vc5_out_data *clk_out) 878 { 879 u32 value; 880 881 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) { 882 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK; 883 switch (value) { 884 case 80: 885 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80; 886 break; 887 case 85: 888 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85; 889 break; 890 case 90: 891 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90; 892 break; 893 case 100: 894 clk_out->clk_output_cfg0 |= 895 VC5_CLK_OUTPUT_CFG0_SLEW_100; 896 break; 897 default: 898 return -EINVAL; 899 } 900 } 901 return 0; 902 } 903 904 static int vc5_get_output_config(struct i2c_client *client, 905 struct vc5_out_data *clk_out) 906 { 907 struct device_node *np_output; 908 char *child_name; 909 int ret = 0; 910 911 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1); 912 if (!child_name) 913 return -ENOMEM; 914 915 np_output = of_get_child_by_name(client->dev.of_node, child_name); 916 kfree(child_name); 917 if (!np_output) 918 return 0; 919 920 ret = vc5_update_mode(np_output, clk_out); 921 if (ret) 922 goto output_error; 923 924 ret = vc5_update_power(np_output, clk_out); 925 if (ret) 926 goto output_error; 927 928 ret = vc5_update_slew(np_output, clk_out); 929 930 output_error: 931 if (ret) { 932 dev_err(&client->dev, 933 "Invalid clock output configuration OUT%d\n", 934 clk_out->num + 1); 935 } 936 937 of_node_put(np_output); 938 939 return ret; 940 } 941 942 static const struct of_device_id clk_vc5_of_match[]; 943 944 static int vc5_probe(struct i2c_client *client) 945 { 946 unsigned int oe, sd, src_mask = 0, src_val = 0; 947 struct vc5_driver_data *vc5; 948 struct clk_init_data init; 949 const char *parent_names[2]; 950 unsigned int n, idx = 0; 951 int ret; 952 953 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); 954 if (!vc5) 955 return -ENOMEM; 956 957 i2c_set_clientdata(client, vc5); 958 vc5->client = client; 959 vc5->chip_info = device_get_match_data(&client->dev); 960 961 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); 962 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) 963 return -EPROBE_DEFER; 964 965 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); 966 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) 967 return -EPROBE_DEFER; 968 969 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); 970 if (IS_ERR(vc5->regmap)) 971 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap), 972 "failed to allocate register map\n"); 973 974 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd); 975 if (!ret) { 976 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; 977 if (sd) 978 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; 979 } else if (ret != -EINVAL) { 980 return dev_err_probe(&client->dev, ret, 981 "could not read idt,shutdown\n"); 982 } 983 984 ret = of_property_read_u32(client->dev.of_node, 985 "idt,output-enable-active", &oe); 986 if (!ret) { 987 src_mask |= VC5_PRIM_SRC_SHDN_SP; 988 if (oe) 989 src_val |= VC5_PRIM_SRC_SHDN_SP; 990 } else if (ret != -EINVAL) { 991 return dev_err_probe(&client->dev, ret, 992 "could not read idt,output-enable-active\n"); 993 } 994 995 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, 996 src_val); 997 if (ret) 998 return ret; 999 1000 /* Register clock input mux */ 1001 memset(&init, 0, sizeof(init)); 1002 1003 if (!IS_ERR(vc5->pin_xin)) { 1004 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 1005 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 1006 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { 1007 vc5->pin_xin = clk_register_fixed_rate(&client->dev, 1008 "internal-xtal", NULL, 1009 0, 25000000); 1010 if (IS_ERR(vc5->pin_xin)) 1011 return PTR_ERR(vc5->pin_xin); 1012 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 1013 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 1014 } 1015 1016 if (!IS_ERR(vc5->pin_clkin)) { 1017 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; 1018 parent_names[init.num_parents++] = 1019 __clk_get_name(vc5->pin_clkin); 1020 } 1021 1022 if (!init.num_parents) 1023 return dev_err_probe(&client->dev, -EINVAL, 1024 "no input clock specified!\n"); 1025 1026 /* Configure Optional Loading Capacitance for external XTAL */ 1027 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) { 1028 ret = vc5_update_cap_load(client->dev.of_node, vc5); 1029 if (ret) 1030 goto err_clk_register; 1031 } 1032 1033 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node); 1034 if (!init.name) { 1035 ret = -ENOMEM; 1036 goto err_clk; 1037 } 1038 1039 init.ops = &vc5_mux_ops; 1040 init.flags = 0; 1041 init.parent_names = parent_names; 1042 vc5->clk_mux.init = &init; 1043 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); 1044 if (ret) 1045 goto err_clk_register; 1046 kfree(init.name); /* clock framework made a copy of the name */ 1047 1048 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { 1049 /* Register frequency doubler */ 1050 memset(&init, 0, sizeof(init)); 1051 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl", 1052 client->dev.of_node); 1053 if (!init.name) { 1054 ret = -ENOMEM; 1055 goto err_clk; 1056 } 1057 init.ops = &vc5_dbl_ops; 1058 init.flags = CLK_SET_RATE_PARENT; 1059 init.parent_names = parent_names; 1060 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1061 init.num_parents = 1; 1062 vc5->clk_mul.init = &init; 1063 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); 1064 if (ret) 1065 goto err_clk_register; 1066 kfree(init.name); /* clock framework made a copy of the name */ 1067 } 1068 1069 /* Register PFD */ 1070 memset(&init, 0, sizeof(init)); 1071 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node); 1072 if (!init.name) { 1073 ret = -ENOMEM; 1074 goto err_clk; 1075 } 1076 init.ops = &vc5_pfd_ops; 1077 init.flags = CLK_SET_RATE_PARENT; 1078 init.parent_names = parent_names; 1079 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) 1080 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); 1081 else 1082 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1083 init.num_parents = 1; 1084 vc5->clk_pfd.init = &init; 1085 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd); 1086 if (ret) 1087 goto err_clk_register; 1088 kfree(init.name); /* clock framework made a copy of the name */ 1089 1090 /* Register PLL */ 1091 memset(&init, 0, sizeof(init)); 1092 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node); 1093 if (!init.name) { 1094 ret = -ENOMEM; 1095 goto err_clk; 1096 } 1097 init.ops = &vc5_pll_ops; 1098 init.flags = CLK_SET_RATE_PARENT; 1099 init.parent_names = parent_names; 1100 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); 1101 init.num_parents = 1; 1102 vc5->clk_pll.num = 0; 1103 vc5->clk_pll.vc5 = vc5; 1104 vc5->clk_pll.hw.init = &init; 1105 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); 1106 if (ret) 1107 goto err_clk_register; 1108 kfree(init.name); /* clock framework made a copy of the name */ 1109 1110 /* Register FODs */ 1111 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { 1112 idx = vc5_map_index_to_output(vc5->chip_info->model, n); 1113 memset(&init, 0, sizeof(init)); 1114 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d", 1115 client->dev.of_node, idx); 1116 if (!init.name) { 1117 ret = -ENOMEM; 1118 goto err_clk; 1119 } 1120 init.ops = &vc5_fod_ops; 1121 init.flags = CLK_SET_RATE_PARENT; 1122 init.parent_names = parent_names; 1123 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); 1124 init.num_parents = 1; 1125 vc5->clk_fod[n].num = idx; 1126 vc5->clk_fod[n].vc5 = vc5; 1127 vc5->clk_fod[n].hw.init = &init; 1128 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); 1129 if (ret) 1130 goto err_clk_register; 1131 kfree(init.name); /* clock framework made a copy of the name */ 1132 } 1133 1134 /* Register MUX-connected OUT0_I2C_SELB output */ 1135 memset(&init, 0, sizeof(init)); 1136 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb", 1137 client->dev.of_node); 1138 if (!init.name) { 1139 ret = -ENOMEM; 1140 goto err_clk; 1141 } 1142 init.ops = &vc5_clk_out_ops; 1143 init.flags = CLK_SET_RATE_PARENT; 1144 init.parent_names = parent_names; 1145 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1146 init.num_parents = 1; 1147 vc5->clk_out[0].num = idx; 1148 vc5->clk_out[0].vc5 = vc5; 1149 vc5->clk_out[0].hw.init = &init; 1150 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); 1151 if (ret) 1152 goto err_clk_register; 1153 kfree(init.name); /* clock framework made a copy of the name */ 1154 1155 /* Register FOD-connected OUTx outputs */ 1156 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { 1157 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1); 1158 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); 1159 if (n == 1) 1160 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); 1161 else 1162 parent_names[1] = 1163 clk_hw_get_name(&vc5->clk_out[n - 1].hw); 1164 1165 memset(&init, 0, sizeof(init)); 1166 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d", 1167 client->dev.of_node, idx + 1); 1168 if (!init.name) { 1169 ret = -ENOMEM; 1170 goto err_clk; 1171 } 1172 init.ops = &vc5_clk_out_ops; 1173 init.flags = CLK_SET_RATE_PARENT; 1174 init.parent_names = parent_names; 1175 init.num_parents = 2; 1176 vc5->clk_out[n].num = idx; 1177 vc5->clk_out[n].vc5 = vc5; 1178 vc5->clk_out[n].hw.init = &init; 1179 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw); 1180 if (ret) 1181 goto err_clk_register; 1182 kfree(init.name); /* clock framework made a copy of the name */ 1183 1184 /* Fetch Clock Output configuration from DT (if specified) */ 1185 ret = vc5_get_output_config(client, &vc5->clk_out[n]); 1186 if (ret) 1187 goto err_clk; 1188 } 1189 1190 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); 1191 if (ret) { 1192 dev_err_probe(&client->dev, ret, 1193 "unable to add clk provider\n"); 1194 goto err_clk; 1195 } 1196 1197 return 0; 1198 1199 err_clk_register: 1200 dev_err_probe(&client->dev, ret, 1201 "unable to register %s\n", init.name); 1202 kfree(init.name); /* clock framework made a copy of the name */ 1203 err_clk: 1204 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 1205 clk_unregister_fixed_rate(vc5->pin_xin); 1206 return ret; 1207 } 1208 1209 static void vc5_remove(struct i2c_client *client) 1210 { 1211 struct vc5_driver_data *vc5 = i2c_get_clientdata(client); 1212 1213 of_clk_del_provider(client->dev.of_node); 1214 1215 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 1216 clk_unregister_fixed_rate(vc5->pin_xin); 1217 } 1218 1219 static int __maybe_unused vc5_suspend(struct device *dev) 1220 { 1221 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); 1222 1223 regcache_cache_only(vc5->regmap, true); 1224 regcache_mark_dirty(vc5->regmap); 1225 1226 return 0; 1227 } 1228 1229 static int __maybe_unused vc5_resume(struct device *dev) 1230 { 1231 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); 1232 int ret; 1233 1234 regcache_cache_only(vc5->regmap, false); 1235 ret = regcache_sync(vc5->regmap); 1236 if (ret) 1237 dev_err(dev, "Failed to restore register map: %d\n", ret); 1238 return ret; 1239 } 1240 1241 static const struct vc5_chip_info idt_5p49v5923_info = { 1242 .model = IDT_VC5_5P49V5923, 1243 .clk_fod_cnt = 2, 1244 .clk_out_cnt = 3, 1245 .flags = 0, 1246 .vco_max = 3000000000UL, 1247 }; 1248 1249 static const struct vc5_chip_info idt_5p49v5925_info = { 1250 .model = IDT_VC5_5P49V5925, 1251 .clk_fod_cnt = 4, 1252 .clk_out_cnt = 5, 1253 .flags = 0, 1254 .vco_max = 3000000000UL, 1255 }; 1256 1257 static const struct vc5_chip_info idt_5p49v5933_info = { 1258 .model = IDT_VC5_5P49V5933, 1259 .clk_fod_cnt = 2, 1260 .clk_out_cnt = 3, 1261 .flags = VC5_HAS_INTERNAL_XTAL, 1262 .vco_max = 3000000000UL, 1263 }; 1264 1265 static const struct vc5_chip_info idt_5p49v5935_info = { 1266 .model = IDT_VC5_5P49V5935, 1267 .clk_fod_cnt = 4, 1268 .clk_out_cnt = 5, 1269 .flags = VC5_HAS_INTERNAL_XTAL, 1270 .vco_max = 3000000000UL, 1271 }; 1272 1273 static const struct vc5_chip_info idt_5p49v60_info = { 1274 .model = IDT_VC6_5P49V60, 1275 .clk_fod_cnt = 4, 1276 .clk_out_cnt = 5, 1277 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, 1278 .vco_max = 2700000000UL, 1279 }; 1280 1281 static const struct vc5_chip_info idt_5p49v6901_info = { 1282 .model = IDT_VC6_5P49V6901, 1283 .clk_fod_cnt = 4, 1284 .clk_out_cnt = 5, 1285 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, 1286 .vco_max = 3000000000UL, 1287 }; 1288 1289 static const struct vc5_chip_info idt_5p49v6965_info = { 1290 .model = IDT_VC6_5P49V6965, 1291 .clk_fod_cnt = 4, 1292 .clk_out_cnt = 5, 1293 .flags = VC5_HAS_BYPASS_SYNC_BIT, 1294 .vco_max = 3000000000UL, 1295 }; 1296 1297 static const struct vc5_chip_info idt_5p49v6975_info = { 1298 .model = IDT_VC6_5P49V6975, 1299 .clk_fod_cnt = 4, 1300 .clk_out_cnt = 5, 1301 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL, 1302 .vco_max = 3000000000UL, 1303 }; 1304 1305 static const struct i2c_device_id vc5_id[] = { 1306 { "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info }, 1307 { "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info }, 1308 { "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info }, 1309 { "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info }, 1310 { "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info }, 1311 { "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info }, 1312 { "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info }, 1313 { "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info }, 1314 { } 1315 }; 1316 MODULE_DEVICE_TABLE(i2c, vc5_id); 1317 1318 static const struct of_device_id clk_vc5_of_match[] = { 1319 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info }, 1320 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info }, 1321 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, 1322 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, 1323 { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info }, 1324 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info }, 1325 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info }, 1326 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info }, 1327 { }, 1328 }; 1329 MODULE_DEVICE_TABLE(of, clk_vc5_of_match); 1330 1331 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume); 1332 1333 static struct i2c_driver vc5_driver = { 1334 .driver = { 1335 .name = "vc5", 1336 .pm = &vc5_pm_ops, 1337 .of_match_table = clk_vc5_of_match, 1338 }, 1339 .probe = vc5_probe, 1340 .remove = vc5_remove, 1341 .id_table = vc5_id, 1342 }; 1343 module_i2c_driver(vc5_driver); 1344 1345 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); 1346 MODULE_DESCRIPTION("IDT VersaClock 5 driver"); 1347 MODULE_LICENSE("GPL"); 1348