1 /* 2 * Driver for IDT Versaclock 5 3 * 4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * Possible optimizations: 19 * - Use spread spectrum 20 * - Use integer divider in FOD if applicable 21 */ 22 23 #include <linux/clk.h> 24 #include <linux/clk-provider.h> 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/interrupt.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_platform.h> 32 #include <linux/rational.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 /* VersaClock5 registers */ 37 #define VC5_OTP_CONTROL 0x00 38 39 /* Factory-reserved register block */ 40 #define VC5_RSVD_DEVICE_ID 0x01 41 #define VC5_RSVD_ADC_GAIN_7_0 0x02 42 #define VC5_RSVD_ADC_GAIN_15_8 0x03 43 #define VC5_RSVD_ADC_OFFSET_7_0 0x04 44 #define VC5_RSVD_ADC_OFFSET_15_8 0x05 45 #define VC5_RSVD_TEMPY 0x06 46 #define VC5_RSVD_OFFSET_TBIN 0x07 47 #define VC5_RSVD_GAIN 0x08 48 #define VC5_RSVD_TEST_NP 0x09 49 #define VC5_RSVD_UNUSED 0x0a 50 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b 51 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c 52 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d 53 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e 54 #define VC5_RSVD_CLK_AMP_123 0x0f 55 56 /* Configuration register block */ 57 #define VC5_PRIM_SRC_SHDN 0x10 58 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) 59 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) 60 #define VC5_PRIM_SRC_SHDN_SP BIT(1) 61 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) 62 63 #define VC5_VCO_BAND 0x11 64 #define VC5_XTAL_X1_LOAD_CAP 0x12 65 #define VC5_XTAL_X2_LOAD_CAP 0x13 66 #define VC5_REF_DIVIDER 0x15 67 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) 68 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) 69 70 #define VC5_VCO_CTRL_AND_PREDIV 0x16 71 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) 72 73 #define VC5_FEEDBACK_INT_DIV 0x17 74 #define VC5_FEEDBACK_INT_DIV_BITS 0x18 75 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) 76 #define VC5_RC_CONTROL0 0x1e 77 #define VC5_RC_CONTROL1 0x1f 78 /* Register 0x20 is factory reserved */ 79 80 /* Output divider control for divider 1,2,3,4 */ 81 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) 82 #define VC5_OUT_DIV_CONTROL_RESET BIT(7) 83 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) 84 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) 85 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) 86 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) 87 88 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) 89 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) 90 91 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) 92 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) 93 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) 94 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) 95 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) 96 /* Registers 0x30, 0x40, 0x50 are factory reserved */ 97 98 /* Clock control register for clock 1,2 */ 99 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) 100 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) 101 102 #define VC5_CLK_OE_SHDN 0x68 103 #define VC5_CLK_OS_SHDN 0x69 104 105 #define VC5_GLOBAL_REGISTER 0x76 106 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) 107 108 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ 109 #define VC5_PLL_VCO_MIN 2500000000UL 110 #define VC5_PLL_VCO_MAX 3000000000UL 111 112 /* VC5 Input mux settings */ 113 #define VC5_MUX_IN_XIN BIT(0) 114 #define VC5_MUX_IN_CLKIN BIT(1) 115 116 /* Supported IDT VC5 models. */ 117 enum vc5_model { 118 IDT_VC5_5P49V5923, 119 IDT_VC5_5P49V5933, 120 }; 121 122 struct vc5_driver_data; 123 124 struct vc5_hw_data { 125 struct clk_hw hw; 126 struct vc5_driver_data *vc5; 127 u32 div_int; 128 u32 div_frc; 129 unsigned int num; 130 }; 131 132 struct vc5_driver_data { 133 struct i2c_client *client; 134 struct regmap *regmap; 135 enum vc5_model model; 136 137 struct clk *pin_xin; 138 struct clk *pin_clkin; 139 unsigned char clk_mux_ins; 140 struct clk_hw clk_mux; 141 struct vc5_hw_data clk_pll; 142 struct vc5_hw_data clk_fod[2]; 143 struct vc5_hw_data clk_out[3]; 144 }; 145 146 static const char * const vc5_mux_names[] = { 147 "mux" 148 }; 149 150 static const char * const vc5_pll_names[] = { 151 "pll" 152 }; 153 154 static const char * const vc5_fod_names[] = { 155 "fod0", "fod1", "fod2", "fod3", 156 }; 157 158 static const char * const vc5_clk_out_names[] = { 159 "out0_sel_i2cb", "out1", "out2", "out3", "out4", 160 }; 161 162 /* 163 * VersaClock5 i2c regmap 164 */ 165 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) 166 { 167 /* Factory reserved regs, make them read-only */ 168 if (reg <= 0xf) 169 return false; 170 171 /* Factory reserved regs, make them read-only */ 172 if (reg == 0x14 || reg == 0x1c || reg == 0x1d) 173 return false; 174 175 return true; 176 } 177 178 static const struct regmap_config vc5_regmap_config = { 179 .reg_bits = 8, 180 .val_bits = 8, 181 .cache_type = REGCACHE_RBTREE, 182 .max_register = 0x76, 183 .writeable_reg = vc5_regmap_is_writeable, 184 }; 185 186 /* 187 * VersaClock5 input multiplexer between XTAL and CLKIN divider 188 */ 189 static unsigned char vc5_mux_get_parent(struct clk_hw *hw) 190 { 191 struct vc5_driver_data *vc5 = 192 container_of(hw, struct vc5_driver_data, clk_mux); 193 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 194 unsigned int src; 195 196 regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); 197 src &= mask; 198 199 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) 200 return 0; 201 202 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) 203 return 1; 204 205 dev_warn(&vc5->client->dev, 206 "Invalid clock input configuration (%02x)\n", src); 207 return 0; 208 } 209 210 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) 211 { 212 struct vc5_driver_data *vc5 = 213 container_of(hw, struct vc5_driver_data, clk_mux); 214 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 215 u8 src; 216 217 if ((index > 1) || !vc5->clk_mux_ins) 218 return -EINVAL; 219 220 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { 221 if (index == 0) 222 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 223 if (index == 1) 224 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 225 } else { 226 if (index != 0) 227 return -EINVAL; 228 229 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) 230 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 231 if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) 232 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 233 } 234 235 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); 236 } 237 238 static unsigned long vc5_mux_recalc_rate(struct clk_hw *hw, 239 unsigned long parent_rate) 240 { 241 struct vc5_driver_data *vc5 = 242 container_of(hw, struct vc5_driver_data, clk_mux); 243 unsigned int prediv, div; 244 245 regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); 246 247 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 248 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) 249 return parent_rate; 250 251 regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); 252 253 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ 254 if (div & VC5_REF_DIVIDER_SEL_PREDIV2) 255 return parent_rate / 2; 256 else 257 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); 258 } 259 260 static long vc5_mux_round_rate(struct clk_hw *hw, unsigned long rate, 261 unsigned long *parent_rate) 262 { 263 unsigned long idiv; 264 265 /* PLL cannot operate with input clock above 50 MHz. */ 266 if (rate > 50000000) 267 return -EINVAL; 268 269 /* CLKIN within range of PLL input, feed directly to PLL. */ 270 if (*parent_rate <= 50000000) 271 return *parent_rate; 272 273 idiv = DIV_ROUND_UP(*parent_rate, rate); 274 if (idiv > 127) 275 return -EINVAL; 276 277 return *parent_rate / idiv; 278 } 279 280 static int vc5_mux_set_rate(struct clk_hw *hw, unsigned long rate, 281 unsigned long parent_rate) 282 { 283 struct vc5_driver_data *vc5 = 284 container_of(hw, struct vc5_driver_data, clk_mux); 285 unsigned long idiv; 286 u8 div; 287 288 /* CLKIN within range of PLL input, feed directly to PLL. */ 289 if (parent_rate <= 50000000) { 290 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 291 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 292 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 293 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); 294 return 0; 295 } 296 297 idiv = DIV_ROUND_UP(parent_rate, rate); 298 299 /* We have dedicated div-2 predivider. */ 300 if (idiv == 2) 301 div = VC5_REF_DIVIDER_SEL_PREDIV2; 302 else 303 div = VC5_REF_DIVIDER_REF_DIV(idiv); 304 305 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); 306 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 307 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0); 308 309 return 0; 310 } 311 312 static const struct clk_ops vc5_mux_ops = { 313 .set_parent = vc5_mux_set_parent, 314 .get_parent = vc5_mux_get_parent, 315 .recalc_rate = vc5_mux_recalc_rate, 316 .round_rate = vc5_mux_round_rate, 317 .set_rate = vc5_mux_set_rate, 318 }; 319 320 /* 321 * VersaClock5 PLL/VCO 322 */ 323 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, 324 unsigned long parent_rate) 325 { 326 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 327 struct vc5_driver_data *vc5 = hwdata->vc5; 328 u32 div_int, div_frc; 329 u8 fb[5]; 330 331 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 332 333 div_int = (fb[0] << 4) | (fb[1] >> 4); 334 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; 335 336 /* The PLL divider has 12 integer bits and 24 fractional bits */ 337 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); 338 } 339 340 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 341 unsigned long *parent_rate) 342 { 343 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 344 u32 div_int; 345 u64 div_frc; 346 347 if (rate < VC5_PLL_VCO_MIN) 348 rate = VC5_PLL_VCO_MIN; 349 if (rate > VC5_PLL_VCO_MAX) 350 rate = VC5_PLL_VCO_MAX; 351 352 /* Determine integer part, which is 12 bit wide */ 353 div_int = rate / *parent_rate; 354 if (div_int > 0xfff) 355 rate = *parent_rate * 0xfff; 356 357 /* Determine best fractional part, which is 24 bit wide */ 358 div_frc = rate % *parent_rate; 359 div_frc *= BIT(24) - 1; 360 do_div(div_frc, *parent_rate); 361 362 hwdata->div_int = div_int; 363 hwdata->div_frc = (u32)div_frc; 364 365 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); 366 } 367 368 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, 369 unsigned long parent_rate) 370 { 371 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 372 struct vc5_driver_data *vc5 = hwdata->vc5; 373 u8 fb[5]; 374 375 fb[0] = hwdata->div_int >> 4; 376 fb[1] = hwdata->div_int << 4; 377 fb[2] = hwdata->div_frc >> 16; 378 fb[3] = hwdata->div_frc >> 8; 379 fb[4] = hwdata->div_frc; 380 381 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 382 } 383 384 static const struct clk_ops vc5_pll_ops = { 385 .recalc_rate = vc5_pll_recalc_rate, 386 .round_rate = vc5_pll_round_rate, 387 .set_rate = vc5_pll_set_rate, 388 }; 389 390 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, 391 unsigned long parent_rate) 392 { 393 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 394 struct vc5_driver_data *vc5 = hwdata->vc5; 395 /* VCO frequency is divided by two before entering FOD */ 396 u32 f_in = parent_rate / 2; 397 u32 div_int, div_frc; 398 u8 od_int[2]; 399 u8 od_frc[4]; 400 401 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), 402 od_int, 2); 403 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 404 od_frc, 4); 405 406 div_int = (od_int[0] << 4) | (od_int[1] >> 4); 407 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | 408 (od_frc[2] << 6) | (od_frc[3] >> 2); 409 410 /* The PLL divider has 12 integer bits and 30 fractional bits */ 411 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 412 } 413 414 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, 415 unsigned long *parent_rate) 416 { 417 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 418 /* VCO frequency is divided by two before entering FOD */ 419 u32 f_in = *parent_rate / 2; 420 u32 div_int; 421 u64 div_frc; 422 423 /* Determine integer part, which is 12 bit wide */ 424 div_int = f_in / rate; 425 /* 426 * WARNING: The clock chip does not output signal if the integer part 427 * of the divider is 0xfff and fractional part is non-zero. 428 * Clamp the divider at 0xffe to keep the code simple. 429 */ 430 if (div_int > 0xffe) { 431 div_int = 0xffe; 432 rate = f_in / div_int; 433 } 434 435 /* Determine best fractional part, which is 30 bit wide */ 436 div_frc = f_in % rate; 437 div_frc <<= 24; 438 do_div(div_frc, rate); 439 440 hwdata->div_int = div_int; 441 hwdata->div_frc = (u32)div_frc; 442 443 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 444 } 445 446 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, 447 unsigned long parent_rate) 448 { 449 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 450 struct vc5_driver_data *vc5 = hwdata->vc5; 451 u8 data[14] = { 452 hwdata->div_frc >> 22, hwdata->div_frc >> 14, 453 hwdata->div_frc >> 6, hwdata->div_frc << 2, 454 0, 0, 0, 0, 0, 455 0, 0, 456 hwdata->div_int >> 4, hwdata->div_int << 4, 457 0 458 }; 459 460 regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 461 data, 14); 462 463 /* 464 * Toggle magic bit in undocumented register for unknown reason. 465 * This is what the IDT timing commander tool does and the chip 466 * datasheet somewhat implies this is needed, but the register 467 * and the bit is not documented. 468 */ 469 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 470 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0); 471 regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 472 VC5_GLOBAL_REGISTER_GLOBAL_RESET, 473 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 474 return 0; 475 } 476 477 static const struct clk_ops vc5_fod_ops = { 478 .recalc_rate = vc5_fod_recalc_rate, 479 .round_rate = vc5_fod_round_rate, 480 .set_rate = vc5_fod_set_rate, 481 }; 482 483 static int vc5_clk_out_prepare(struct clk_hw *hw) 484 { 485 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 486 struct vc5_driver_data *vc5 = hwdata->vc5; 487 488 /* Enable the clock buffer */ 489 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 490 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 491 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 492 return 0; 493 } 494 495 static void vc5_clk_out_unprepare(struct clk_hw *hw) 496 { 497 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 498 struct vc5_driver_data *vc5 = hwdata->vc5; 499 500 /* Enable the clock buffer */ 501 regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 502 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0); 503 } 504 505 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) 506 { 507 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 508 struct vc5_driver_data *vc5 = hwdata->vc5; 509 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 510 VC5_OUT_DIV_CONTROL_SEL_EXT | 511 VC5_OUT_DIV_CONTROL_EN_FOD; 512 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | 513 VC5_OUT_DIV_CONTROL_EN_FOD; 514 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 515 VC5_OUT_DIV_CONTROL_SEL_EXT; 516 unsigned int src; 517 518 regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 519 src &= mask; 520 521 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) 522 return 0; 523 524 if (src == extclk) 525 return 1; 526 527 dev_warn(&vc5->client->dev, 528 "Invalid clock output configuration (%02x)\n", src); 529 return 0; 530 } 531 532 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) 533 { 534 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 535 struct vc5_driver_data *vc5 = hwdata->vc5; 536 const u8 mask = VC5_OUT_DIV_CONTROL_RESET | 537 VC5_OUT_DIV_CONTROL_SELB_NORM | 538 VC5_OUT_DIV_CONTROL_SEL_EXT | 539 VC5_OUT_DIV_CONTROL_EN_FOD; 540 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 541 VC5_OUT_DIV_CONTROL_SEL_EXT; 542 u8 src = VC5_OUT_DIV_CONTROL_RESET; 543 544 if (index == 0) 545 src |= VC5_OUT_DIV_CONTROL_EN_FOD; 546 else 547 src |= extclk; 548 549 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), 550 mask, src); 551 } 552 553 static const struct clk_ops vc5_clk_out_ops = { 554 .prepare = vc5_clk_out_prepare, 555 .unprepare = vc5_clk_out_unprepare, 556 .set_parent = vc5_clk_out_set_parent, 557 .get_parent = vc5_clk_out_get_parent, 558 }; 559 560 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, 561 void *data) 562 { 563 struct vc5_driver_data *vc5 = data; 564 unsigned int idx = clkspec->args[0]; 565 566 if (idx > 2) 567 return ERR_PTR(-EINVAL); 568 569 return &vc5->clk_out[idx].hw; 570 } 571 572 static int vc5_map_index_to_output(const enum vc5_model model, 573 const unsigned int n) 574 { 575 switch (model) { 576 case IDT_VC5_5P49V5933: 577 return (n == 0) ? 0 : 3; 578 case IDT_VC5_5P49V5923: 579 default: 580 return n; 581 } 582 } 583 584 static const struct of_device_id clk_vc5_of_match[]; 585 586 static int vc5_probe(struct i2c_client *client, 587 const struct i2c_device_id *id) 588 { 589 const struct of_device_id *of_id = 590 of_match_device(clk_vc5_of_match, &client->dev); 591 struct vc5_driver_data *vc5; 592 struct clk_init_data init; 593 const char *parent_names[2]; 594 unsigned int n, idx; 595 int ret; 596 597 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); 598 if (vc5 == NULL) 599 return -ENOMEM; 600 601 i2c_set_clientdata(client, vc5); 602 vc5->client = client; 603 vc5->model = (enum vc5_model)of_id->data; 604 605 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); 606 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) 607 return -EPROBE_DEFER; 608 609 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); 610 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) 611 return -EPROBE_DEFER; 612 613 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); 614 if (IS_ERR(vc5->regmap)) { 615 dev_err(&client->dev, "failed to allocate register map\n"); 616 return PTR_ERR(vc5->regmap); 617 } 618 619 /* Register clock input mux */ 620 memset(&init, 0, sizeof(init)); 621 622 if (!IS_ERR(vc5->pin_xin)) { 623 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 624 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 625 } else if (vc5->model == IDT_VC5_5P49V5933) { 626 /* IDT VC5 5P49V5933 has built-in oscilator. */ 627 vc5->pin_xin = clk_register_fixed_rate(&client->dev, 628 "internal-xtal", NULL, 629 0, 25000000); 630 if (IS_ERR(vc5->pin_xin)) 631 return PTR_ERR(vc5->pin_xin); 632 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 633 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 634 } 635 636 if (!IS_ERR(vc5->pin_clkin)) { 637 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; 638 parent_names[init.num_parents++] = 639 __clk_get_name(vc5->pin_clkin); 640 } 641 642 if (!init.num_parents) { 643 dev_err(&client->dev, "no input clock specified!\n"); 644 return -EINVAL; 645 } 646 647 init.name = vc5_mux_names[0]; 648 init.ops = &vc5_mux_ops; 649 init.flags = 0; 650 init.parent_names = parent_names; 651 vc5->clk_mux.init = &init; 652 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); 653 if (ret) { 654 dev_err(&client->dev, "unable to register %s\n", init.name); 655 goto err_clk; 656 } 657 658 /* Register PLL */ 659 memset(&init, 0, sizeof(init)); 660 init.name = vc5_pll_names[0]; 661 init.ops = &vc5_pll_ops; 662 init.flags = CLK_SET_RATE_PARENT; 663 init.parent_names = vc5_mux_names; 664 init.num_parents = 1; 665 vc5->clk_pll.num = 0; 666 vc5->clk_pll.vc5 = vc5; 667 vc5->clk_pll.hw.init = &init; 668 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); 669 if (ret) { 670 dev_err(&client->dev, "unable to register %s\n", init.name); 671 goto err_clk; 672 } 673 674 /* Register FODs */ 675 for (n = 0; n < 2; n++) { 676 idx = vc5_map_index_to_output(vc5->model, n); 677 memset(&init, 0, sizeof(init)); 678 init.name = vc5_fod_names[idx]; 679 init.ops = &vc5_fod_ops; 680 init.flags = CLK_SET_RATE_PARENT; 681 init.parent_names = vc5_pll_names; 682 init.num_parents = 1; 683 vc5->clk_fod[n].num = idx; 684 vc5->clk_fod[n].vc5 = vc5; 685 vc5->clk_fod[n].hw.init = &init; 686 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); 687 if (ret) { 688 dev_err(&client->dev, "unable to register %s\n", 689 init.name); 690 goto err_clk; 691 } 692 } 693 694 /* Register MUX-connected OUT0_I2C_SELB output */ 695 memset(&init, 0, sizeof(init)); 696 init.name = vc5_clk_out_names[0]; 697 init.ops = &vc5_clk_out_ops; 698 init.flags = CLK_SET_RATE_PARENT; 699 init.parent_names = vc5_mux_names; 700 init.num_parents = 1; 701 vc5->clk_out[0].num = idx; 702 vc5->clk_out[0].vc5 = vc5; 703 vc5->clk_out[0].hw.init = &init; 704 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); 705 if (ret) { 706 dev_err(&client->dev, "unable to register %s\n", 707 init.name); 708 goto err_clk; 709 } 710 711 /* Register FOD-connected OUTx outputs */ 712 for (n = 1; n < 3; n++) { 713 idx = vc5_map_index_to_output(vc5->model, n - 1); 714 parent_names[0] = vc5_fod_names[idx]; 715 if (n == 1) 716 parent_names[1] = vc5_mux_names[0]; 717 else 718 parent_names[1] = vc5_clk_out_names[n - 1]; 719 720 memset(&init, 0, sizeof(init)); 721 init.name = vc5_clk_out_names[idx + 1]; 722 init.ops = &vc5_clk_out_ops; 723 init.flags = CLK_SET_RATE_PARENT; 724 init.parent_names = parent_names; 725 init.num_parents = 2; 726 vc5->clk_out[n].num = idx; 727 vc5->clk_out[n].vc5 = vc5; 728 vc5->clk_out[n].hw.init = &init; 729 ret = devm_clk_hw_register(&client->dev, 730 &vc5->clk_out[n].hw); 731 if (ret) { 732 dev_err(&client->dev, "unable to register %s\n", 733 init.name); 734 goto err_clk; 735 } 736 } 737 738 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); 739 if (ret) { 740 dev_err(&client->dev, "unable to add clk provider\n"); 741 goto err_clk; 742 } 743 744 return 0; 745 746 err_clk: 747 if (vc5->model == IDT_VC5_5P49V5933) 748 clk_unregister_fixed_rate(vc5->pin_xin); 749 return ret; 750 } 751 752 static int vc5_remove(struct i2c_client *client) 753 { 754 struct vc5_driver_data *vc5 = i2c_get_clientdata(client); 755 756 of_clk_del_provider(client->dev.of_node); 757 758 if (vc5->model == IDT_VC5_5P49V5933) 759 clk_unregister_fixed_rate(vc5->pin_xin); 760 761 return 0; 762 } 763 764 static const struct i2c_device_id vc5_id[] = { 765 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 }, 766 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, 767 { } 768 }; 769 MODULE_DEVICE_TABLE(i2c, vc5_id); 770 771 static const struct of_device_id clk_vc5_of_match[] = { 772 { .compatible = "idt,5p49v5923", .data = (void *)IDT_VC5_5P49V5923 }, 773 { .compatible = "idt,5p49v5933", .data = (void *)IDT_VC5_5P49V5933 }, 774 { }, 775 }; 776 MODULE_DEVICE_TABLE(of, clk_vc5_of_match); 777 778 static struct i2c_driver vc5_driver = { 779 .driver = { 780 .name = "vc5", 781 .of_match_table = clk_vc5_of_match, 782 }, 783 .probe = vc5_probe, 784 .remove = vc5_remove, 785 .id_table = vc5_id, 786 }; 787 module_i2c_driver(vc5_driver); 788 789 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); 790 MODULE_DESCRIPTION("IDT VersaClock 5 driver"); 791 MODULE_LICENSE("GPL"); 792