1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for IDT Versaclock 5 4 * 5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 /* 9 * Possible optimizations: 10 * - Use spread spectrum 11 * - Use integer divider in FOD if applicable 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/rational.h> 24 #include <linux/regmap.h> 25 #include <linux/slab.h> 26 27 #include <dt-bindings/clock/versaclock.h> 28 29 /* VersaClock5 registers */ 30 #define VC5_OTP_CONTROL 0x00 31 32 /* Factory-reserved register block */ 33 #define VC5_RSVD_DEVICE_ID 0x01 34 #define VC5_RSVD_ADC_GAIN_7_0 0x02 35 #define VC5_RSVD_ADC_GAIN_15_8 0x03 36 #define VC5_RSVD_ADC_OFFSET_7_0 0x04 37 #define VC5_RSVD_ADC_OFFSET_15_8 0x05 38 #define VC5_RSVD_TEMPY 0x06 39 #define VC5_RSVD_OFFSET_TBIN 0x07 40 #define VC5_RSVD_GAIN 0x08 41 #define VC5_RSVD_TEST_NP 0x09 42 #define VC5_RSVD_UNUSED 0x0a 43 #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b 44 #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c 45 #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d 46 #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e 47 #define VC5_RSVD_CLK_AMP_123 0x0f 48 49 /* Configuration register block */ 50 #define VC5_PRIM_SRC_SHDN 0x10 51 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) 52 #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) 53 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) 54 #define VC5_PRIM_SRC_SHDN_SP BIT(1) 55 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) 56 57 #define VC5_VCO_BAND 0x11 58 #define VC5_XTAL_X1_LOAD_CAP 0x12 59 #define VC5_XTAL_X2_LOAD_CAP 0x13 60 #define VC5_REF_DIVIDER 0x15 61 #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) 62 #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) 63 64 #define VC5_VCO_CTRL_AND_PREDIV 0x16 65 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) 66 67 #define VC5_FEEDBACK_INT_DIV 0x17 68 #define VC5_FEEDBACK_INT_DIV_BITS 0x18 69 #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) 70 #define VC5_RC_CONTROL0 0x1e 71 #define VC5_RC_CONTROL1 0x1f 72 73 /* These registers are named "Unused Factory Reserved Registers" */ 74 #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10)) 75 #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */ 76 77 /* Output divider control for divider 1,2,3,4 */ 78 #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) 79 #define VC5_OUT_DIV_CONTROL_RESET BIT(7) 80 #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) 81 #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) 82 #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) 83 #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) 84 85 #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) 86 #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) 87 88 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) 89 #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) 90 #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) 91 #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) 92 #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) 93 94 /* Clock control register for clock 1,2 */ 95 #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) 96 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 97 #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) 98 99 #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL) 100 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) 101 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33) 102 #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) 103 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) 104 #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) 105 #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25) 106 107 #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 108 #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 109 #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 110 #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 111 #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) 112 #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0 113 #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 114 #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 115 #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 116 #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 117 #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) 118 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) 119 120 #define VC5_CLK_OE_SHDN 0x68 121 #define VC5_CLK_OS_SHDN 0x69 122 123 #define VC5_GLOBAL_REGISTER 0x76 124 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) 125 126 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */ 127 #define VC5_PLL_VCO_MIN 2500000000UL 128 #define VC5_PLL_VCO_MAX 3000000000UL 129 130 /* VC5 Input mux settings */ 131 #define VC5_MUX_IN_XIN BIT(0) 132 #define VC5_MUX_IN_CLKIN BIT(1) 133 134 /* Maximum number of clk_out supported by this driver */ 135 #define VC5_MAX_CLK_OUT_NUM 5 136 137 /* Maximum number of FODs supported by this driver */ 138 #define VC5_MAX_FOD_NUM 4 139 140 /* flags to describe chip features */ 141 /* chip has built-in oscilator */ 142 #define VC5_HAS_INTERNAL_XTAL BIT(0) 143 /* chip has PFD requency doubler */ 144 #define VC5_HAS_PFD_FREQ_DBL BIT(1) 145 /* chip has bits to disable FOD sync */ 146 #define VC5_HAS_BYPASS_SYNC_BIT BIT(2) 147 148 /* Supported IDT VC5 models. */ 149 enum vc5_model { 150 IDT_VC5_5P49V5923, 151 IDT_VC5_5P49V5925, 152 IDT_VC5_5P49V5933, 153 IDT_VC5_5P49V5935, 154 IDT_VC6_5P49V6901, 155 IDT_VC6_5P49V6965, 156 IDT_VC6_5P49V6975, 157 }; 158 159 /* Structure to describe features of a particular VC5 model */ 160 struct vc5_chip_info { 161 const enum vc5_model model; 162 const unsigned int clk_fod_cnt; 163 const unsigned int clk_out_cnt; 164 const u32 flags; 165 }; 166 167 struct vc5_driver_data; 168 169 struct vc5_hw_data { 170 struct clk_hw hw; 171 struct vc5_driver_data *vc5; 172 u32 div_int; 173 u32 div_frc; 174 unsigned int num; 175 }; 176 177 struct vc5_out_data { 178 struct clk_hw hw; 179 struct vc5_driver_data *vc5; 180 unsigned int num; 181 unsigned int clk_output_cfg0; 182 unsigned int clk_output_cfg0_mask; 183 }; 184 185 struct vc5_driver_data { 186 struct i2c_client *client; 187 struct regmap *regmap; 188 const struct vc5_chip_info *chip_info; 189 190 struct clk *pin_xin; 191 struct clk *pin_clkin; 192 unsigned char clk_mux_ins; 193 struct clk_hw clk_mux; 194 struct clk_hw clk_mul; 195 struct clk_hw clk_pfd; 196 struct vc5_hw_data clk_pll; 197 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; 198 struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM]; 199 }; 200 201 /* 202 * VersaClock5 i2c regmap 203 */ 204 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) 205 { 206 /* Factory reserved regs, make them read-only */ 207 if (reg <= 0xf) 208 return false; 209 210 /* Factory reserved regs, make them read-only */ 211 if (reg == 0x14 || reg == 0x1c || reg == 0x1d) 212 return false; 213 214 return true; 215 } 216 217 static const struct regmap_config vc5_regmap_config = { 218 .reg_bits = 8, 219 .val_bits = 8, 220 .cache_type = REGCACHE_RBTREE, 221 .max_register = 0x76, 222 .writeable_reg = vc5_regmap_is_writeable, 223 }; 224 225 /* 226 * VersaClock5 input multiplexer between XTAL and CLKIN divider 227 */ 228 static unsigned char vc5_mux_get_parent(struct clk_hw *hw) 229 { 230 struct vc5_driver_data *vc5 = 231 container_of(hw, struct vc5_driver_data, clk_mux); 232 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 233 unsigned int src; 234 int ret; 235 236 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src); 237 if (ret) 238 return 0; 239 240 src &= mask; 241 242 if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) 243 return 0; 244 245 if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) 246 return 1; 247 248 dev_warn(&vc5->client->dev, 249 "Invalid clock input configuration (%02x)\n", src); 250 return 0; 251 } 252 253 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) 254 { 255 struct vc5_driver_data *vc5 = 256 container_of(hw, struct vc5_driver_data, clk_mux); 257 const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; 258 u8 src; 259 260 if ((index > 1) || !vc5->clk_mux_ins) 261 return -EINVAL; 262 263 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { 264 if (index == 0) 265 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 266 if (index == 1) 267 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 268 } else { 269 if (index != 0) 270 return -EINVAL; 271 272 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) 273 src = VC5_PRIM_SRC_SHDN_EN_XTAL; 274 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) 275 src = VC5_PRIM_SRC_SHDN_EN_CLKIN; 276 else /* Invalid; should have been caught by vc5_probe() */ 277 return -EINVAL; 278 } 279 280 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); 281 } 282 283 static const struct clk_ops vc5_mux_ops = { 284 .set_parent = vc5_mux_set_parent, 285 .get_parent = vc5_mux_get_parent, 286 }; 287 288 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, 289 unsigned long parent_rate) 290 { 291 struct vc5_driver_data *vc5 = 292 container_of(hw, struct vc5_driver_data, clk_mul); 293 unsigned int premul; 294 int ret; 295 296 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); 297 if (ret) 298 return 0; 299 300 if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) 301 parent_rate *= 2; 302 303 return parent_rate; 304 } 305 306 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, 307 unsigned long *parent_rate) 308 { 309 if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) 310 return rate; 311 else 312 return -EINVAL; 313 } 314 315 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, 316 unsigned long parent_rate) 317 { 318 struct vc5_driver_data *vc5 = 319 container_of(hw, struct vc5_driver_data, clk_mul); 320 u32 mask; 321 322 if ((parent_rate * 2) == rate) 323 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; 324 else 325 mask = 0; 326 327 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, 328 VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, 329 mask); 330 } 331 332 static const struct clk_ops vc5_dbl_ops = { 333 .recalc_rate = vc5_dbl_recalc_rate, 334 .round_rate = vc5_dbl_round_rate, 335 .set_rate = vc5_dbl_set_rate, 336 }; 337 338 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, 339 unsigned long parent_rate) 340 { 341 struct vc5_driver_data *vc5 = 342 container_of(hw, struct vc5_driver_data, clk_pfd); 343 unsigned int prediv, div; 344 int ret; 345 346 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); 347 if (ret) 348 return 0; 349 350 /* The bypass_prediv is set, PLL fed from Ref_in directly. */ 351 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) 352 return parent_rate; 353 354 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div); 355 if (ret) 356 return 0; 357 358 /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ 359 if (div & VC5_REF_DIVIDER_SEL_PREDIV2) 360 return parent_rate / 2; 361 else 362 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); 363 } 364 365 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, 366 unsigned long *parent_rate) 367 { 368 unsigned long idiv; 369 370 /* PLL cannot operate with input clock above 50 MHz. */ 371 if (rate > 50000000) 372 return -EINVAL; 373 374 /* CLKIN within range of PLL input, feed directly to PLL. */ 375 if (*parent_rate <= 50000000) 376 return *parent_rate; 377 378 idiv = DIV_ROUND_UP(*parent_rate, rate); 379 if (idiv > 127) 380 return -EINVAL; 381 382 return *parent_rate / idiv; 383 } 384 385 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, 386 unsigned long parent_rate) 387 { 388 struct vc5_driver_data *vc5 = 389 container_of(hw, struct vc5_driver_data, clk_pfd); 390 unsigned long idiv; 391 int ret; 392 u8 div; 393 394 /* CLKIN within range of PLL input, feed directly to PLL. */ 395 if (parent_rate <= 50000000) { 396 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 397 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 398 if (ret) 399 return ret; 400 401 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00); 402 } 403 404 idiv = DIV_ROUND_UP(parent_rate, rate); 405 406 /* We have dedicated div-2 predivider. */ 407 if (idiv == 2) 408 div = VC5_REF_DIVIDER_SEL_PREDIV2; 409 else 410 div = VC5_REF_DIVIDER_REF_DIV(idiv); 411 412 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div); 413 if (ret) 414 return ret; 415 416 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, 417 VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); 418 } 419 420 static const struct clk_ops vc5_pfd_ops = { 421 .recalc_rate = vc5_pfd_recalc_rate, 422 .round_rate = vc5_pfd_round_rate, 423 .set_rate = vc5_pfd_set_rate, 424 }; 425 426 /* 427 * VersaClock5 PLL/VCO 428 */ 429 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, 430 unsigned long parent_rate) 431 { 432 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 433 struct vc5_driver_data *vc5 = hwdata->vc5; 434 u32 div_int, div_frc; 435 u8 fb[5]; 436 437 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 438 439 div_int = (fb[0] << 4) | (fb[1] >> 4); 440 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; 441 442 /* The PLL divider has 12 integer bits and 24 fractional bits */ 443 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); 444 } 445 446 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, 447 unsigned long *parent_rate) 448 { 449 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 450 u32 div_int; 451 u64 div_frc; 452 453 if (rate < VC5_PLL_VCO_MIN) 454 rate = VC5_PLL_VCO_MIN; 455 if (rate > VC5_PLL_VCO_MAX) 456 rate = VC5_PLL_VCO_MAX; 457 458 /* Determine integer part, which is 12 bit wide */ 459 div_int = rate / *parent_rate; 460 if (div_int > 0xfff) 461 rate = *parent_rate * 0xfff; 462 463 /* Determine best fractional part, which is 24 bit wide */ 464 div_frc = rate % *parent_rate; 465 div_frc *= BIT(24) - 1; 466 do_div(div_frc, *parent_rate); 467 468 hwdata->div_int = div_int; 469 hwdata->div_frc = (u32)div_frc; 470 471 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); 472 } 473 474 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, 475 unsigned long parent_rate) 476 { 477 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 478 struct vc5_driver_data *vc5 = hwdata->vc5; 479 u8 fb[5]; 480 481 fb[0] = hwdata->div_int >> 4; 482 fb[1] = hwdata->div_int << 4; 483 fb[2] = hwdata->div_frc >> 16; 484 fb[3] = hwdata->div_frc >> 8; 485 fb[4] = hwdata->div_frc; 486 487 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); 488 } 489 490 static const struct clk_ops vc5_pll_ops = { 491 .recalc_rate = vc5_pll_recalc_rate, 492 .round_rate = vc5_pll_round_rate, 493 .set_rate = vc5_pll_set_rate, 494 }; 495 496 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, 497 unsigned long parent_rate) 498 { 499 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 500 struct vc5_driver_data *vc5 = hwdata->vc5; 501 /* VCO frequency is divided by two before entering FOD */ 502 u32 f_in = parent_rate / 2; 503 u32 div_int, div_frc; 504 u8 od_int[2]; 505 u8 od_frc[4]; 506 507 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), 508 od_int, 2); 509 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 510 od_frc, 4); 511 512 div_int = (od_int[0] << 4) | (od_int[1] >> 4); 513 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | 514 (od_frc[2] << 6) | (od_frc[3] >> 2); 515 516 /* Avoid division by zero if the output is not configured. */ 517 if (div_int == 0 && div_frc == 0) 518 return 0; 519 520 /* The PLL divider has 12 integer bits and 30 fractional bits */ 521 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 522 } 523 524 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, 525 unsigned long *parent_rate) 526 { 527 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 528 /* VCO frequency is divided by two before entering FOD */ 529 u32 f_in = *parent_rate / 2; 530 u32 div_int; 531 u64 div_frc; 532 533 /* Determine integer part, which is 12 bit wide */ 534 div_int = f_in / rate; 535 /* 536 * WARNING: The clock chip does not output signal if the integer part 537 * of the divider is 0xfff and fractional part is non-zero. 538 * Clamp the divider at 0xffe to keep the code simple. 539 */ 540 if (div_int > 0xffe) { 541 div_int = 0xffe; 542 rate = f_in / div_int; 543 } 544 545 /* Determine best fractional part, which is 30 bit wide */ 546 div_frc = f_in % rate; 547 div_frc <<= 24; 548 do_div(div_frc, rate); 549 550 hwdata->div_int = div_int; 551 hwdata->div_frc = (u32)div_frc; 552 553 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); 554 } 555 556 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, 557 unsigned long parent_rate) 558 { 559 struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); 560 struct vc5_driver_data *vc5 = hwdata->vc5; 561 u8 data[14] = { 562 hwdata->div_frc >> 22, hwdata->div_frc >> 14, 563 hwdata->div_frc >> 6, hwdata->div_frc << 2, 564 0, 0, 0, 0, 0, 565 0, 0, 566 hwdata->div_int >> 4, hwdata->div_int << 4, 567 0 568 }; 569 int ret; 570 571 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), 572 data, 14); 573 if (ret) 574 return ret; 575 576 /* 577 * Toggle magic bit in undocumented register for unknown reason. 578 * This is what the IDT timing commander tool does and the chip 579 * datasheet somewhat implies this is needed, but the register 580 * and the bit is not documented. 581 */ 582 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 583 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 584 if (ret) 585 return ret; 586 587 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER, 588 VC5_GLOBAL_REGISTER_GLOBAL_RESET); 589 } 590 591 static const struct clk_ops vc5_fod_ops = { 592 .recalc_rate = vc5_fod_recalc_rate, 593 .round_rate = vc5_fod_round_rate, 594 .set_rate = vc5_fod_set_rate, 595 }; 596 597 static int vc5_clk_out_prepare(struct clk_hw *hw) 598 { 599 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 600 struct vc5_driver_data *vc5 = hwdata->vc5; 601 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 602 VC5_OUT_DIV_CONTROL_SEL_EXT | 603 VC5_OUT_DIV_CONTROL_EN_FOD; 604 unsigned int src; 605 int ret; 606 607 /* 608 * When enabling a FOD, all currently enabled FODs are briefly 609 * stopped in order to synchronize all of them. This causes a clock 610 * disruption to any unrelated chips that might be already using 611 * other clock outputs. Bypass the sync feature to avoid the issue, 612 * which is possible on the VersaClock 6E family via reserved 613 * registers. 614 */ 615 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { 616 ret = regmap_set_bits(vc5->regmap, 617 VC5_RESERVED_X0(hwdata->num), 618 VC5_RESERVED_X0_BYPASS_SYNC); 619 if (ret) 620 return ret; 621 } 622 623 /* 624 * If the input mux is disabled, enable it first and 625 * select source from matching FOD. 626 */ 627 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 628 if (ret) 629 return ret; 630 631 if ((src & mask) == 0) { 632 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD; 633 ret = regmap_update_bits(vc5->regmap, 634 VC5_OUT_DIV_CONTROL(hwdata->num), 635 mask | VC5_OUT_DIV_CONTROL_RESET, src); 636 if (ret) 637 return ret; 638 } 639 640 /* Enable the clock buffer */ 641 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 642 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 643 if (ret) 644 return ret; 645 646 if (hwdata->clk_output_cfg0_mask) { 647 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n", 648 hwdata->num, hwdata->clk_output_cfg0_mask, 649 hwdata->clk_output_cfg0); 650 651 ret = regmap_update_bits(vc5->regmap, 652 VC5_CLK_OUTPUT_CFG(hwdata->num, 0), 653 hwdata->clk_output_cfg0_mask, 654 hwdata->clk_output_cfg0); 655 if (ret) 656 return ret; 657 } 658 659 return 0; 660 } 661 662 static void vc5_clk_out_unprepare(struct clk_hw *hw) 663 { 664 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 665 struct vc5_driver_data *vc5 = hwdata->vc5; 666 667 /* Disable the clock buffer */ 668 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), 669 VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); 670 } 671 672 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) 673 { 674 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 675 struct vc5_driver_data *vc5 = hwdata->vc5; 676 const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | 677 VC5_OUT_DIV_CONTROL_SEL_EXT | 678 VC5_OUT_DIV_CONTROL_EN_FOD; 679 const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | 680 VC5_OUT_DIV_CONTROL_EN_FOD; 681 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 682 VC5_OUT_DIV_CONTROL_SEL_EXT; 683 unsigned int src; 684 int ret; 685 686 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src); 687 if (ret) 688 return 0; 689 690 src &= mask; 691 692 if (src == 0) /* Input mux set to DISABLED */ 693 return 0; 694 695 if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) 696 return 0; 697 698 if (src == extclk) 699 return 1; 700 701 dev_warn(&vc5->client->dev, 702 "Invalid clock output configuration (%02x)\n", src); 703 return 0; 704 } 705 706 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) 707 { 708 struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); 709 struct vc5_driver_data *vc5 = hwdata->vc5; 710 const u8 mask = VC5_OUT_DIV_CONTROL_RESET | 711 VC5_OUT_DIV_CONTROL_SELB_NORM | 712 VC5_OUT_DIV_CONTROL_SEL_EXT | 713 VC5_OUT_DIV_CONTROL_EN_FOD; 714 const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | 715 VC5_OUT_DIV_CONTROL_SEL_EXT; 716 u8 src = VC5_OUT_DIV_CONTROL_RESET; 717 718 if (index == 0) 719 src |= VC5_OUT_DIV_CONTROL_EN_FOD; 720 else 721 src |= extclk; 722 723 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), 724 mask, src); 725 } 726 727 static const struct clk_ops vc5_clk_out_ops = { 728 .prepare = vc5_clk_out_prepare, 729 .unprepare = vc5_clk_out_unprepare, 730 .set_parent = vc5_clk_out_set_parent, 731 .get_parent = vc5_clk_out_get_parent, 732 }; 733 734 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, 735 void *data) 736 { 737 struct vc5_driver_data *vc5 = data; 738 unsigned int idx = clkspec->args[0]; 739 740 if (idx >= vc5->chip_info->clk_out_cnt) 741 return ERR_PTR(-EINVAL); 742 743 return &vc5->clk_out[idx].hw; 744 } 745 746 static int vc5_map_index_to_output(const enum vc5_model model, 747 const unsigned int n) 748 { 749 switch (model) { 750 case IDT_VC5_5P49V5933: 751 return (n == 0) ? 0 : 3; 752 case IDT_VC5_5P49V5923: 753 case IDT_VC5_5P49V5925: 754 case IDT_VC5_5P49V5935: 755 case IDT_VC6_5P49V6901: 756 case IDT_VC6_5P49V6965: 757 case IDT_VC6_5P49V6975: 758 default: 759 return n; 760 } 761 } 762 763 static int vc5_update_mode(struct device_node *np_output, 764 struct vc5_out_data *clk_out) 765 { 766 u32 value; 767 768 if (!of_property_read_u32(np_output, "idt,mode", &value)) { 769 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK; 770 switch (value) { 771 case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL: 772 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS: 773 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33: 774 case VC5_CLK_OUTPUT_CFG0_CFG_LVDS: 775 case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2: 776 case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD: 777 case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25: 778 clk_out->clk_output_cfg0 |= 779 value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT; 780 break; 781 default: 782 return -EINVAL; 783 } 784 } 785 return 0; 786 } 787 788 static int vc5_update_power(struct device_node *np_output, 789 struct vc5_out_data *clk_out) 790 { 791 u32 value; 792 793 if (!of_property_read_u32(np_output, "idt,voltage-microvolt", 794 &value)) { 795 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK; 796 switch (value) { 797 case 1800000: 798 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18; 799 break; 800 case 2500000: 801 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25; 802 break; 803 case 3300000: 804 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33; 805 break; 806 default: 807 return -EINVAL; 808 } 809 } 810 return 0; 811 } 812 813 static int vc5_map_cap_value(u32 femtofarads) 814 { 815 int mapped_value; 816 817 /* 818 * The datasheet explicitly states 9000 - 25000 with 0.5pF 819 * steps, but the Programmer's guide shows the steps are 0.430pF. 820 * After getting feedback from Renesas, the .5pF steps were the 821 * goal, but 430nF was the actual values. 822 * Because of this, the actual range goes to 22760 instead of 25000 823 */ 824 if (femtofarads < 9000 || femtofarads > 22760) 825 return -EINVAL; 826 827 /* 828 * The Programmer's guide shows XTAL[5:0] but in reality, 829 * XTAL[0] and XTAL[1] are both LSB which makes the math 830 * strange. With clarfication from Renesas, setting the 831 * values should be simpler by ignoring XTAL[0] 832 */ 833 mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430); 834 835 /* 836 * Since the calculation ignores XTAL[0], there is one 837 * special case where mapped_value = 32. In reality, this means 838 * the real mapped value should be 111111b. In other cases, 839 * the mapped_value needs to be shifted 1 to the left. 840 */ 841 if (mapped_value > 31) 842 mapped_value = 0x3f; 843 else 844 mapped_value <<= 1; 845 846 return mapped_value; 847 } 848 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5) 849 { 850 u32 value; 851 int mapped_value; 852 int ret; 853 854 if (of_property_read_u32(node, "idt,xtal-load-femtofarads", &value)) 855 return 0; 856 857 mapped_value = vc5_map_cap_value(value); 858 if (mapped_value < 0) 859 return mapped_value; 860 861 /* 862 * The mapped_value is really the high 6 bits of 863 * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so 864 * shift the value 2 places. 865 */ 866 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03, 867 mapped_value << 2); 868 if (ret) 869 return ret; 870 871 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03, 872 mapped_value << 2); 873 } 874 875 static int vc5_update_slew(struct device_node *np_output, 876 struct vc5_out_data *clk_out) 877 { 878 u32 value; 879 880 if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) { 881 clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK; 882 switch (value) { 883 case 80: 884 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80; 885 break; 886 case 85: 887 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85; 888 break; 889 case 90: 890 clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90; 891 break; 892 case 100: 893 clk_out->clk_output_cfg0 |= 894 VC5_CLK_OUTPUT_CFG0_SLEW_100; 895 break; 896 default: 897 return -EINVAL; 898 } 899 } 900 return 0; 901 } 902 903 static int vc5_get_output_config(struct i2c_client *client, 904 struct vc5_out_data *clk_out) 905 { 906 struct device_node *np_output; 907 char *child_name; 908 int ret = 0; 909 910 child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1); 911 if (!child_name) 912 return -ENOMEM; 913 914 np_output = of_get_child_by_name(client->dev.of_node, child_name); 915 kfree(child_name); 916 if (!np_output) 917 return 0; 918 919 ret = vc5_update_mode(np_output, clk_out); 920 if (ret) 921 goto output_error; 922 923 ret = vc5_update_power(np_output, clk_out); 924 if (ret) 925 goto output_error; 926 927 ret = vc5_update_slew(np_output, clk_out); 928 929 output_error: 930 if (ret) { 931 dev_err(&client->dev, 932 "Invalid clock output configuration OUT%d\n", 933 clk_out->num + 1); 934 } 935 936 of_node_put(np_output); 937 938 return ret; 939 } 940 941 static const struct of_device_id clk_vc5_of_match[]; 942 943 static int vc5_probe(struct i2c_client *client) 944 { 945 unsigned int oe, sd, src_mask = 0, src_val = 0; 946 struct vc5_driver_data *vc5; 947 struct clk_init_data init; 948 const char *parent_names[2]; 949 unsigned int n, idx = 0; 950 int ret; 951 952 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); 953 if (!vc5) 954 return -ENOMEM; 955 956 i2c_set_clientdata(client, vc5); 957 vc5->client = client; 958 vc5->chip_info = of_device_get_match_data(&client->dev); 959 960 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); 961 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) 962 return -EPROBE_DEFER; 963 964 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin"); 965 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER) 966 return -EPROBE_DEFER; 967 968 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); 969 if (IS_ERR(vc5->regmap)) 970 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap), 971 "failed to allocate register map\n"); 972 973 ret = of_property_read_u32(client->dev.of_node, "idt,shutdown", &sd); 974 if (!ret) { 975 src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; 976 if (sd) 977 src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; 978 } else if (ret != -EINVAL) { 979 return dev_err_probe(&client->dev, ret, 980 "could not read idt,shutdown\n"); 981 } 982 983 ret = of_property_read_u32(client->dev.of_node, 984 "idt,output-enable-active", &oe); 985 if (!ret) { 986 src_mask |= VC5_PRIM_SRC_SHDN_SP; 987 if (oe) 988 src_val |= VC5_PRIM_SRC_SHDN_SP; 989 } else if (ret != -EINVAL) { 990 return dev_err_probe(&client->dev, ret, 991 "could not read idt,output-enable-active\n"); 992 } 993 994 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask, 995 src_val); 996 if (ret) 997 return ret; 998 999 /* Register clock input mux */ 1000 memset(&init, 0, sizeof(init)); 1001 1002 if (!IS_ERR(vc5->pin_xin)) { 1003 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 1004 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 1005 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { 1006 vc5->pin_xin = clk_register_fixed_rate(&client->dev, 1007 "internal-xtal", NULL, 1008 0, 25000000); 1009 if (IS_ERR(vc5->pin_xin)) 1010 return PTR_ERR(vc5->pin_xin); 1011 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 1012 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 1013 } 1014 1015 if (!IS_ERR(vc5->pin_clkin)) { 1016 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; 1017 parent_names[init.num_parents++] = 1018 __clk_get_name(vc5->pin_clkin); 1019 } 1020 1021 if (!init.num_parents) 1022 return dev_err_probe(&client->dev, -EINVAL, 1023 "no input clock specified!\n"); 1024 1025 /* Configure Optional Loading Capacitance for external XTAL */ 1026 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) { 1027 ret = vc5_update_cap_load(client->dev.of_node, vc5); 1028 if (ret) 1029 goto err_clk_register; 1030 } 1031 1032 init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node); 1033 init.ops = &vc5_mux_ops; 1034 init.flags = 0; 1035 init.parent_names = parent_names; 1036 vc5->clk_mux.init = &init; 1037 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux); 1038 if (ret) 1039 goto err_clk_register; 1040 kfree(init.name); /* clock framework made a copy of the name */ 1041 1042 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { 1043 /* Register frequency doubler */ 1044 memset(&init, 0, sizeof(init)); 1045 init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl", 1046 client->dev.of_node); 1047 init.ops = &vc5_dbl_ops; 1048 init.flags = CLK_SET_RATE_PARENT; 1049 init.parent_names = parent_names; 1050 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1051 init.num_parents = 1; 1052 vc5->clk_mul.init = &init; 1053 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); 1054 if (ret) 1055 goto err_clk_register; 1056 kfree(init.name); /* clock framework made a copy of the name */ 1057 } 1058 1059 /* Register PFD */ 1060 memset(&init, 0, sizeof(init)); 1061 init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node); 1062 init.ops = &vc5_pfd_ops; 1063 init.flags = CLK_SET_RATE_PARENT; 1064 init.parent_names = parent_names; 1065 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) 1066 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); 1067 else 1068 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1069 init.num_parents = 1; 1070 vc5->clk_pfd.init = &init; 1071 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd); 1072 if (ret) 1073 goto err_clk_register; 1074 kfree(init.name); /* clock framework made a copy of the name */ 1075 1076 /* Register PLL */ 1077 memset(&init, 0, sizeof(init)); 1078 init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node); 1079 init.ops = &vc5_pll_ops; 1080 init.flags = CLK_SET_RATE_PARENT; 1081 init.parent_names = parent_names; 1082 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); 1083 init.num_parents = 1; 1084 vc5->clk_pll.num = 0; 1085 vc5->clk_pll.vc5 = vc5; 1086 vc5->clk_pll.hw.init = &init; 1087 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw); 1088 if (ret) 1089 goto err_clk_register; 1090 kfree(init.name); /* clock framework made a copy of the name */ 1091 1092 /* Register FODs */ 1093 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { 1094 idx = vc5_map_index_to_output(vc5->chip_info->model, n); 1095 memset(&init, 0, sizeof(init)); 1096 init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d", 1097 client->dev.of_node, idx); 1098 init.ops = &vc5_fod_ops; 1099 init.flags = CLK_SET_RATE_PARENT; 1100 init.parent_names = parent_names; 1101 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); 1102 init.num_parents = 1; 1103 vc5->clk_fod[n].num = idx; 1104 vc5->clk_fod[n].vc5 = vc5; 1105 vc5->clk_fod[n].hw.init = &init; 1106 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw); 1107 if (ret) 1108 goto err_clk_register; 1109 kfree(init.name); /* clock framework made a copy of the name */ 1110 } 1111 1112 /* Register MUX-connected OUT0_I2C_SELB output */ 1113 memset(&init, 0, sizeof(init)); 1114 init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb", 1115 client->dev.of_node); 1116 init.ops = &vc5_clk_out_ops; 1117 init.flags = CLK_SET_RATE_PARENT; 1118 init.parent_names = parent_names; 1119 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); 1120 init.num_parents = 1; 1121 vc5->clk_out[0].num = idx; 1122 vc5->clk_out[0].vc5 = vc5; 1123 vc5->clk_out[0].hw.init = &init; 1124 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw); 1125 if (ret) 1126 goto err_clk_register; 1127 kfree(init.name); /* clock framework made a copy of the name */ 1128 1129 /* Register FOD-connected OUTx outputs */ 1130 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { 1131 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1); 1132 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); 1133 if (n == 1) 1134 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); 1135 else 1136 parent_names[1] = 1137 clk_hw_get_name(&vc5->clk_out[n - 1].hw); 1138 1139 memset(&init, 0, sizeof(init)); 1140 init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d", 1141 client->dev.of_node, idx + 1); 1142 init.ops = &vc5_clk_out_ops; 1143 init.flags = CLK_SET_RATE_PARENT; 1144 init.parent_names = parent_names; 1145 init.num_parents = 2; 1146 vc5->clk_out[n].num = idx; 1147 vc5->clk_out[n].vc5 = vc5; 1148 vc5->clk_out[n].hw.init = &init; 1149 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw); 1150 if (ret) 1151 goto err_clk_register; 1152 kfree(init.name); /* clock framework made a copy of the name */ 1153 1154 /* Fetch Clock Output configuration from DT (if specified) */ 1155 ret = vc5_get_output_config(client, &vc5->clk_out[n]); 1156 if (ret) 1157 goto err_clk; 1158 } 1159 1160 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5); 1161 if (ret) { 1162 dev_err_probe(&client->dev, ret, 1163 "unable to add clk provider\n"); 1164 goto err_clk; 1165 } 1166 1167 return 0; 1168 1169 err_clk_register: 1170 dev_err_probe(&client->dev, ret, 1171 "unable to register %s\n", init.name); 1172 kfree(init.name); /* clock framework made a copy of the name */ 1173 err_clk: 1174 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 1175 clk_unregister_fixed_rate(vc5->pin_xin); 1176 return ret; 1177 } 1178 1179 static void vc5_remove(struct i2c_client *client) 1180 { 1181 struct vc5_driver_data *vc5 = i2c_get_clientdata(client); 1182 1183 of_clk_del_provider(client->dev.of_node); 1184 1185 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) 1186 clk_unregister_fixed_rate(vc5->pin_xin); 1187 } 1188 1189 static int __maybe_unused vc5_suspend(struct device *dev) 1190 { 1191 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); 1192 1193 regcache_cache_only(vc5->regmap, true); 1194 regcache_mark_dirty(vc5->regmap); 1195 1196 return 0; 1197 } 1198 1199 static int __maybe_unused vc5_resume(struct device *dev) 1200 { 1201 struct vc5_driver_data *vc5 = dev_get_drvdata(dev); 1202 int ret; 1203 1204 regcache_cache_only(vc5->regmap, false); 1205 ret = regcache_sync(vc5->regmap); 1206 if (ret) 1207 dev_err(dev, "Failed to restore register map: %d\n", ret); 1208 return ret; 1209 } 1210 1211 static const struct vc5_chip_info idt_5p49v5923_info = { 1212 .model = IDT_VC5_5P49V5923, 1213 .clk_fod_cnt = 2, 1214 .clk_out_cnt = 3, 1215 .flags = 0, 1216 }; 1217 1218 static const struct vc5_chip_info idt_5p49v5925_info = { 1219 .model = IDT_VC5_5P49V5925, 1220 .clk_fod_cnt = 4, 1221 .clk_out_cnt = 5, 1222 .flags = 0, 1223 }; 1224 1225 static const struct vc5_chip_info idt_5p49v5933_info = { 1226 .model = IDT_VC5_5P49V5933, 1227 .clk_fod_cnt = 2, 1228 .clk_out_cnt = 3, 1229 .flags = VC5_HAS_INTERNAL_XTAL, 1230 }; 1231 1232 static const struct vc5_chip_info idt_5p49v5935_info = { 1233 .model = IDT_VC5_5P49V5935, 1234 .clk_fod_cnt = 4, 1235 .clk_out_cnt = 5, 1236 .flags = VC5_HAS_INTERNAL_XTAL, 1237 }; 1238 1239 static const struct vc5_chip_info idt_5p49v6901_info = { 1240 .model = IDT_VC6_5P49V6901, 1241 .clk_fod_cnt = 4, 1242 .clk_out_cnt = 5, 1243 .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, 1244 }; 1245 1246 static const struct vc5_chip_info idt_5p49v6965_info = { 1247 .model = IDT_VC6_5P49V6965, 1248 .clk_fod_cnt = 4, 1249 .clk_out_cnt = 5, 1250 .flags = VC5_HAS_BYPASS_SYNC_BIT, 1251 }; 1252 1253 static const struct vc5_chip_info idt_5p49v6975_info = { 1254 .model = IDT_VC6_5P49V6975, 1255 .clk_fod_cnt = 4, 1256 .clk_out_cnt = 5, 1257 .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL, 1258 }; 1259 1260 static const struct i2c_device_id vc5_id[] = { 1261 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 }, 1262 { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 }, 1263 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, 1264 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 }, 1265 { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 }, 1266 { "5p49v6965", .driver_data = IDT_VC6_5P49V6965 }, 1267 { "5p49v6975", .driver_data = IDT_VC6_5P49V6975 }, 1268 { } 1269 }; 1270 MODULE_DEVICE_TABLE(i2c, vc5_id); 1271 1272 static const struct of_device_id clk_vc5_of_match[] = { 1273 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info }, 1274 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info }, 1275 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info }, 1276 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info }, 1277 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info }, 1278 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info }, 1279 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info }, 1280 { }, 1281 }; 1282 MODULE_DEVICE_TABLE(of, clk_vc5_of_match); 1283 1284 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume); 1285 1286 static struct i2c_driver vc5_driver = { 1287 .driver = { 1288 .name = "vc5", 1289 .pm = &vc5_pm_ops, 1290 .of_match_table = clk_vc5_of_match, 1291 }, 1292 .probe_new = vc5_probe, 1293 .remove = vc5_remove, 1294 .id_table = vc5_id, 1295 }; 1296 module_i2c_driver(vc5_driver); 1297 1298 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); 1299 MODULE_DESCRIPTION("IDT VersaClock 5 driver"); 1300 MODULE_LICENSE("GPL"); 1301