xref: /openbmc/linux/drivers/clk/clk-stm32f4.c (revision a36954f5)
1 /*
2  * Author: Daniel Thompson <daniel.thompson@linaro.org>
3  *
4  * Inspired by clk-asm9260.c .
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include <linux/clk-provider.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/regmap.h>
29 #include <linux/mfd/syscon.h>
30 
31 /*
32  * Include list of clocks wich are not derived from system clock (SYSCLOCK)
33  * The index of these clocks is the secondary index of DT bindings
34  *
35  */
36 #include <dt-bindings/clock/stm32fx-clock.h>
37 
38 #define STM32F4_RCC_CR			0x00
39 #define STM32F4_RCC_PLLCFGR		0x04
40 #define STM32F4_RCC_CFGR		0x08
41 #define STM32F4_RCC_AHB1ENR		0x30
42 #define STM32F4_RCC_AHB2ENR		0x34
43 #define STM32F4_RCC_AHB3ENR		0x38
44 #define STM32F4_RCC_APB1ENR		0x40
45 #define STM32F4_RCC_APB2ENR		0x44
46 #define STM32F4_RCC_BDCR		0x70
47 #define STM32F4_RCC_CSR			0x74
48 #define STM32F4_RCC_PLLI2SCFGR		0x84
49 #define STM32F4_RCC_PLLSAICFGR		0x88
50 #define STM32F4_RCC_DCKCFGR		0x8c
51 #define STM32F7_RCC_DCKCFGR2		0x90
52 
53 #define NONE -1
54 #define NO_IDX  NONE
55 #define NO_MUX  NONE
56 #define NO_GATE NONE
57 
58 struct stm32f4_gate_data {
59 	u8	offset;
60 	u8	bit_idx;
61 	const char *name;
62 	const char *parent_name;
63 	unsigned long flags;
64 };
65 
66 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
67 	{ STM32F4_RCC_AHB1ENR,  0,	"gpioa",	"ahb_div" },
68 	{ STM32F4_RCC_AHB1ENR,  1,	"gpiob",	"ahb_div" },
69 	{ STM32F4_RCC_AHB1ENR,  2,	"gpioc",	"ahb_div" },
70 	{ STM32F4_RCC_AHB1ENR,  3,	"gpiod",	"ahb_div" },
71 	{ STM32F4_RCC_AHB1ENR,  4,	"gpioe",	"ahb_div" },
72 	{ STM32F4_RCC_AHB1ENR,  5,	"gpiof",	"ahb_div" },
73 	{ STM32F4_RCC_AHB1ENR,  6,	"gpiog",	"ahb_div" },
74 	{ STM32F4_RCC_AHB1ENR,  7,	"gpioh",	"ahb_div" },
75 	{ STM32F4_RCC_AHB1ENR,  8,	"gpioi",	"ahb_div" },
76 	{ STM32F4_RCC_AHB1ENR,  9,	"gpioj",	"ahb_div" },
77 	{ STM32F4_RCC_AHB1ENR, 10,	"gpiok",	"ahb_div" },
78 	{ STM32F4_RCC_AHB1ENR, 12,	"crc",		"ahb_div" },
79 	{ STM32F4_RCC_AHB1ENR, 18,	"bkpsra",	"ahb_div" },
80 	{ STM32F4_RCC_AHB1ENR, 20,	"ccmdatam",	"ahb_div" },
81 	{ STM32F4_RCC_AHB1ENR, 21,	"dma1",		"ahb_div" },
82 	{ STM32F4_RCC_AHB1ENR, 22,	"dma2",		"ahb_div" },
83 	{ STM32F4_RCC_AHB1ENR, 23,	"dma2d",	"ahb_div" },
84 	{ STM32F4_RCC_AHB1ENR, 25,	"ethmac",	"ahb_div" },
85 	{ STM32F4_RCC_AHB1ENR, 26,	"ethmactx",	"ahb_div" },
86 	{ STM32F4_RCC_AHB1ENR, 27,	"ethmacrx",	"ahb_div" },
87 	{ STM32F4_RCC_AHB1ENR, 28,	"ethmacptp",	"ahb_div" },
88 	{ STM32F4_RCC_AHB1ENR, 29,	"otghs",	"ahb_div" },
89 	{ STM32F4_RCC_AHB1ENR, 30,	"otghsulpi",	"ahb_div" },
90 
91 	{ STM32F4_RCC_AHB2ENR,  0,	"dcmi",		"ahb_div" },
92 	{ STM32F4_RCC_AHB2ENR,  4,	"cryp",		"ahb_div" },
93 	{ STM32F4_RCC_AHB2ENR,  5,	"hash",		"ahb_div" },
94 	{ STM32F4_RCC_AHB2ENR,  6,	"rng",		"pll48" },
95 	{ STM32F4_RCC_AHB2ENR,  7,	"otgfs",	"pll48" },
96 
97 	{ STM32F4_RCC_AHB3ENR,  0,	"fmc",		"ahb_div",
98 		CLK_IGNORE_UNUSED },
99 
100 	{ STM32F4_RCC_APB1ENR,  0,	"tim2",		"apb1_mul" },
101 	{ STM32F4_RCC_APB1ENR,  1,	"tim3",		"apb1_mul" },
102 	{ STM32F4_RCC_APB1ENR,  2,	"tim4",		"apb1_mul" },
103 	{ STM32F4_RCC_APB1ENR,  3,	"tim5",		"apb1_mul" },
104 	{ STM32F4_RCC_APB1ENR,  4,	"tim6",		"apb1_mul" },
105 	{ STM32F4_RCC_APB1ENR,  5,	"tim7",		"apb1_mul" },
106 	{ STM32F4_RCC_APB1ENR,  6,	"tim12",	"apb1_mul" },
107 	{ STM32F4_RCC_APB1ENR,  7,	"tim13",	"apb1_mul" },
108 	{ STM32F4_RCC_APB1ENR,  8,	"tim14",	"apb1_mul" },
109 	{ STM32F4_RCC_APB1ENR, 11,	"wwdg",		"apb1_div" },
110 	{ STM32F4_RCC_APB1ENR, 14,	"spi2",		"apb1_div" },
111 	{ STM32F4_RCC_APB1ENR, 15,	"spi3",		"apb1_div" },
112 	{ STM32F4_RCC_APB1ENR, 17,	"uart2",	"apb1_div" },
113 	{ STM32F4_RCC_APB1ENR, 18,	"uart3",	"apb1_div" },
114 	{ STM32F4_RCC_APB1ENR, 19,	"uart4",	"apb1_div" },
115 	{ STM32F4_RCC_APB1ENR, 20,	"uart5",	"apb1_div" },
116 	{ STM32F4_RCC_APB1ENR, 21,	"i2c1",		"apb1_div" },
117 	{ STM32F4_RCC_APB1ENR, 22,	"i2c2",		"apb1_div" },
118 	{ STM32F4_RCC_APB1ENR, 23,	"i2c3",		"apb1_div" },
119 	{ STM32F4_RCC_APB1ENR, 25,	"can1",		"apb1_div" },
120 	{ STM32F4_RCC_APB1ENR, 26,	"can2",		"apb1_div" },
121 	{ STM32F4_RCC_APB1ENR, 28,	"pwr",		"apb1_div" },
122 	{ STM32F4_RCC_APB1ENR, 29,	"dac",		"apb1_div" },
123 	{ STM32F4_RCC_APB1ENR, 30,	"uart7",	"apb1_div" },
124 	{ STM32F4_RCC_APB1ENR, 31,	"uart8",	"apb1_div" },
125 
126 	{ STM32F4_RCC_APB2ENR,  0,	"tim1",		"apb2_mul" },
127 	{ STM32F4_RCC_APB2ENR,  1,	"tim8",		"apb2_mul" },
128 	{ STM32F4_RCC_APB2ENR,  4,	"usart1",	"apb2_div" },
129 	{ STM32F4_RCC_APB2ENR,  5,	"usart6",	"apb2_div" },
130 	{ STM32F4_RCC_APB2ENR,  8,	"adc1",		"apb2_div" },
131 	{ STM32F4_RCC_APB2ENR,  9,	"adc2",		"apb2_div" },
132 	{ STM32F4_RCC_APB2ENR, 10,	"adc3",		"apb2_div" },
133 	{ STM32F4_RCC_APB2ENR, 11,	"sdio",		"pll48" },
134 	{ STM32F4_RCC_APB2ENR, 12,	"spi1",		"apb2_div" },
135 	{ STM32F4_RCC_APB2ENR, 13,	"spi4",		"apb2_div" },
136 	{ STM32F4_RCC_APB2ENR, 14,	"syscfg",	"apb2_div" },
137 	{ STM32F4_RCC_APB2ENR, 16,	"tim9",		"apb2_mul" },
138 	{ STM32F4_RCC_APB2ENR, 17,	"tim10",	"apb2_mul" },
139 	{ STM32F4_RCC_APB2ENR, 18,	"tim11",	"apb2_mul" },
140 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
141 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
142 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
143 	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
144 };
145 
146 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
147 	{ STM32F4_RCC_AHB1ENR,  0,	"gpioa",	"ahb_div" },
148 	{ STM32F4_RCC_AHB1ENR,  1,	"gpiob",	"ahb_div" },
149 	{ STM32F4_RCC_AHB1ENR,  2,	"gpioc",	"ahb_div" },
150 	{ STM32F4_RCC_AHB1ENR,  3,	"gpiod",	"ahb_div" },
151 	{ STM32F4_RCC_AHB1ENR,  4,	"gpioe",	"ahb_div" },
152 	{ STM32F4_RCC_AHB1ENR,  5,	"gpiof",	"ahb_div" },
153 	{ STM32F4_RCC_AHB1ENR,  6,	"gpiog",	"ahb_div" },
154 	{ STM32F4_RCC_AHB1ENR,  7,	"gpioh",	"ahb_div" },
155 	{ STM32F4_RCC_AHB1ENR,  8,	"gpioi",	"ahb_div" },
156 	{ STM32F4_RCC_AHB1ENR,  9,	"gpioj",	"ahb_div" },
157 	{ STM32F4_RCC_AHB1ENR, 10,	"gpiok",	"ahb_div" },
158 	{ STM32F4_RCC_AHB1ENR, 12,	"crc",		"ahb_div" },
159 	{ STM32F4_RCC_AHB1ENR, 18,	"bkpsra",	"ahb_div" },
160 	{ STM32F4_RCC_AHB1ENR, 20,	"ccmdatam",	"ahb_div" },
161 	{ STM32F4_RCC_AHB1ENR, 21,	"dma1",		"ahb_div" },
162 	{ STM32F4_RCC_AHB1ENR, 22,	"dma2",		"ahb_div" },
163 	{ STM32F4_RCC_AHB1ENR, 23,	"dma2d",	"ahb_div" },
164 	{ STM32F4_RCC_AHB1ENR, 25,	"ethmac",	"ahb_div" },
165 	{ STM32F4_RCC_AHB1ENR, 26,	"ethmactx",	"ahb_div" },
166 	{ STM32F4_RCC_AHB1ENR, 27,	"ethmacrx",	"ahb_div" },
167 	{ STM32F4_RCC_AHB1ENR, 28,	"ethmacptp",	"ahb_div" },
168 	{ STM32F4_RCC_AHB1ENR, 29,	"otghs",	"ahb_div" },
169 	{ STM32F4_RCC_AHB1ENR, 30,	"otghsulpi",	"ahb_div" },
170 
171 	{ STM32F4_RCC_AHB2ENR,  0,	"dcmi",		"ahb_div" },
172 	{ STM32F4_RCC_AHB2ENR,  4,	"cryp",		"ahb_div" },
173 	{ STM32F4_RCC_AHB2ENR,  5,	"hash",		"ahb_div" },
174 	{ STM32F4_RCC_AHB2ENR,  6,	"rng",		"pll48" },
175 	{ STM32F4_RCC_AHB2ENR,  7,	"otgfs",	"pll48" },
176 
177 	{ STM32F4_RCC_AHB3ENR,  0,	"fmc",		"ahb_div",
178 		CLK_IGNORE_UNUSED },
179 	{ STM32F4_RCC_AHB3ENR,  1,	"qspi",		"ahb_div",
180 		CLK_IGNORE_UNUSED },
181 
182 	{ STM32F4_RCC_APB1ENR,  0,	"tim2",		"apb1_mul" },
183 	{ STM32F4_RCC_APB1ENR,  1,	"tim3",		"apb1_mul" },
184 	{ STM32F4_RCC_APB1ENR,  2,	"tim4",		"apb1_mul" },
185 	{ STM32F4_RCC_APB1ENR,  3,	"tim5",		"apb1_mul" },
186 	{ STM32F4_RCC_APB1ENR,  4,	"tim6",		"apb1_mul" },
187 	{ STM32F4_RCC_APB1ENR,  5,	"tim7",		"apb1_mul" },
188 	{ STM32F4_RCC_APB1ENR,  6,	"tim12",	"apb1_mul" },
189 	{ STM32F4_RCC_APB1ENR,  7,	"tim13",	"apb1_mul" },
190 	{ STM32F4_RCC_APB1ENR,  8,	"tim14",	"apb1_mul" },
191 	{ STM32F4_RCC_APB1ENR, 11,	"wwdg",		"apb1_div" },
192 	{ STM32F4_RCC_APB1ENR, 14,	"spi2",		"apb1_div" },
193 	{ STM32F4_RCC_APB1ENR, 15,	"spi3",		"apb1_div" },
194 	{ STM32F4_RCC_APB1ENR, 17,	"uart2",	"apb1_div" },
195 	{ STM32F4_RCC_APB1ENR, 18,	"uart3",	"apb1_div" },
196 	{ STM32F4_RCC_APB1ENR, 19,	"uart4",	"apb1_div" },
197 	{ STM32F4_RCC_APB1ENR, 20,	"uart5",	"apb1_div" },
198 	{ STM32F4_RCC_APB1ENR, 21,	"i2c1",		"apb1_div" },
199 	{ STM32F4_RCC_APB1ENR, 22,	"i2c2",		"apb1_div" },
200 	{ STM32F4_RCC_APB1ENR, 23,	"i2c3",		"apb1_div" },
201 	{ STM32F4_RCC_APB1ENR, 25,	"can1",		"apb1_div" },
202 	{ STM32F4_RCC_APB1ENR, 26,	"can2",		"apb1_div" },
203 	{ STM32F4_RCC_APB1ENR, 28,	"pwr",		"apb1_div" },
204 	{ STM32F4_RCC_APB1ENR, 29,	"dac",		"apb1_div" },
205 	{ STM32F4_RCC_APB1ENR, 30,	"uart7",	"apb1_div" },
206 	{ STM32F4_RCC_APB1ENR, 31,	"uart8",	"apb1_div" },
207 
208 	{ STM32F4_RCC_APB2ENR,  0,	"tim1",		"apb2_mul" },
209 	{ STM32F4_RCC_APB2ENR,  1,	"tim8",		"apb2_mul" },
210 	{ STM32F4_RCC_APB2ENR,  4,	"usart1",	"apb2_div" },
211 	{ STM32F4_RCC_APB2ENR,  5,	"usart6",	"apb2_div" },
212 	{ STM32F4_RCC_APB2ENR,  8,	"adc1",		"apb2_div" },
213 	{ STM32F4_RCC_APB2ENR,  9,	"adc2",		"apb2_div" },
214 	{ STM32F4_RCC_APB2ENR, 10,	"adc3",		"apb2_div" },
215 	{ STM32F4_RCC_APB2ENR, 11,	"sdio",		"sdmux" },
216 	{ STM32F4_RCC_APB2ENR, 12,	"spi1",		"apb2_div" },
217 	{ STM32F4_RCC_APB2ENR, 13,	"spi4",		"apb2_div" },
218 	{ STM32F4_RCC_APB2ENR, 14,	"syscfg",	"apb2_div" },
219 	{ STM32F4_RCC_APB2ENR, 16,	"tim9",		"apb2_mul" },
220 	{ STM32F4_RCC_APB2ENR, 17,	"tim10",	"apb2_mul" },
221 	{ STM32F4_RCC_APB2ENR, 18,	"tim11",	"apb2_mul" },
222 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
223 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
224 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
225 	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
226 };
227 
228 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
229 	{ STM32F4_RCC_AHB1ENR,  0,	"gpioa",	"ahb_div" },
230 	{ STM32F4_RCC_AHB1ENR,  1,	"gpiob",	"ahb_div" },
231 	{ STM32F4_RCC_AHB1ENR,  2,	"gpioc",	"ahb_div" },
232 	{ STM32F4_RCC_AHB1ENR,  3,	"gpiod",	"ahb_div" },
233 	{ STM32F4_RCC_AHB1ENR,  4,	"gpioe",	"ahb_div" },
234 	{ STM32F4_RCC_AHB1ENR,  5,	"gpiof",	"ahb_div" },
235 	{ STM32F4_RCC_AHB1ENR,  6,	"gpiog",	"ahb_div" },
236 	{ STM32F4_RCC_AHB1ENR,  7,	"gpioh",	"ahb_div" },
237 	{ STM32F4_RCC_AHB1ENR,  8,	"gpioi",	"ahb_div" },
238 	{ STM32F4_RCC_AHB1ENR,  9,	"gpioj",	"ahb_div" },
239 	{ STM32F4_RCC_AHB1ENR, 10,	"gpiok",	"ahb_div" },
240 	{ STM32F4_RCC_AHB1ENR, 12,	"crc",		"ahb_div" },
241 	{ STM32F4_RCC_AHB1ENR, 18,	"bkpsra",	"ahb_div" },
242 	{ STM32F4_RCC_AHB1ENR, 20,	"dtcmram",	"ahb_div" },
243 	{ STM32F4_RCC_AHB1ENR, 21,	"dma1",		"ahb_div" },
244 	{ STM32F4_RCC_AHB1ENR, 22,	"dma2",		"ahb_div" },
245 	{ STM32F4_RCC_AHB1ENR, 23,	"dma2d",	"ahb_div" },
246 	{ STM32F4_RCC_AHB1ENR, 25,	"ethmac",	"ahb_div" },
247 	{ STM32F4_RCC_AHB1ENR, 26,	"ethmactx",	"ahb_div" },
248 	{ STM32F4_RCC_AHB1ENR, 27,	"ethmacrx",	"ahb_div" },
249 	{ STM32F4_RCC_AHB1ENR, 28,	"ethmacptp",	"ahb_div" },
250 	{ STM32F4_RCC_AHB1ENR, 29,	"otghs",	"ahb_div" },
251 	{ STM32F4_RCC_AHB1ENR, 30,	"otghsulpi",	"ahb_div" },
252 
253 	{ STM32F4_RCC_AHB2ENR,  0,	"dcmi",		"ahb_div" },
254 	{ STM32F4_RCC_AHB2ENR,  4,	"cryp",		"ahb_div" },
255 	{ STM32F4_RCC_AHB2ENR,  5,	"hash",		"ahb_div" },
256 	{ STM32F4_RCC_AHB2ENR,  6,	"rng",		"pll48"   },
257 	{ STM32F4_RCC_AHB2ENR,  7,	"otgfs",	"pll48"   },
258 
259 	{ STM32F4_RCC_AHB3ENR,  0,	"fmc",		"ahb_div",
260 		CLK_IGNORE_UNUSED },
261 	{ STM32F4_RCC_AHB3ENR,  1,	"qspi",		"ahb_div",
262 		CLK_IGNORE_UNUSED },
263 
264 	{ STM32F4_RCC_APB1ENR,  0,	"tim2",		"apb1_mul" },
265 	{ STM32F4_RCC_APB1ENR,  1,	"tim3",		"apb1_mul" },
266 	{ STM32F4_RCC_APB1ENR,  2,	"tim4",		"apb1_mul" },
267 	{ STM32F4_RCC_APB1ENR,  3,	"tim5",		"apb1_mul" },
268 	{ STM32F4_RCC_APB1ENR,  4,	"tim6",		"apb1_mul" },
269 	{ STM32F4_RCC_APB1ENR,  5,	"tim7",		"apb1_mul" },
270 	{ STM32F4_RCC_APB1ENR,  6,	"tim12",	"apb1_mul" },
271 	{ STM32F4_RCC_APB1ENR,  7,	"tim13",	"apb1_mul" },
272 	{ STM32F4_RCC_APB1ENR,  8,	"tim14",	"apb1_mul" },
273 	{ STM32F4_RCC_APB1ENR, 11,	"wwdg",		"apb1_div" },
274 	{ STM32F4_RCC_APB1ENR, 14,	"spi2",		"apb1_div" },
275 	{ STM32F4_RCC_APB1ENR, 15,	"spi3",		"apb1_div" },
276 	{ STM32F4_RCC_APB1ENR, 16,	"spdifrx",	"apb1_div" },
277 	{ STM32F4_RCC_APB1ENR, 25,	"can1",		"apb1_div" },
278 	{ STM32F4_RCC_APB1ENR, 26,	"can2",		"apb1_div" },
279 	{ STM32F4_RCC_APB1ENR, 27,	"cec",		"apb1_div" },
280 	{ STM32F4_RCC_APB1ENR, 28,	"pwr",		"apb1_div" },
281 	{ STM32F4_RCC_APB1ENR, 29,	"dac",		"apb1_div" },
282 
283 	{ STM32F4_RCC_APB2ENR,  0,	"tim1",		"apb2_mul" },
284 	{ STM32F4_RCC_APB2ENR,  1,	"tim8",		"apb2_mul" },
285 	{ STM32F4_RCC_APB2ENR,  8,	"adc1",		"apb2_div" },
286 	{ STM32F4_RCC_APB2ENR,  9,	"adc2",		"apb2_div" },
287 	{ STM32F4_RCC_APB2ENR, 10,	"adc3",		"apb2_div" },
288 	{ STM32F4_RCC_APB2ENR, 11,	"sdmmc",	"sdmux"    },
289 	{ STM32F4_RCC_APB2ENR, 12,	"spi1",		"apb2_div" },
290 	{ STM32F4_RCC_APB2ENR, 13,	"spi4",		"apb2_div" },
291 	{ STM32F4_RCC_APB2ENR, 14,	"syscfg",	"apb2_div" },
292 	{ STM32F4_RCC_APB2ENR, 16,	"tim9",		"apb2_mul" },
293 	{ STM32F4_RCC_APB2ENR, 17,	"tim10",	"apb2_mul" },
294 	{ STM32F4_RCC_APB2ENR, 18,	"tim11",	"apb2_mul" },
295 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
296 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
297 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
298 	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },
299 	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
300 };
301 
302 /*
303  * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
304  * have gate bits associated with them. Its combined hweight is 71.
305  */
306 #define MAX_GATE_MAP 3
307 
308 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
309 						       0x0000000000000001ull,
310 						       0x04777f33f6fec9ffull };
311 
312 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
313 						       0x0000000000000003ull,
314 						       0x0c777f33f6fec9ffull };
315 
316 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
317 						      0x0000000000000003ull,
318 						      0x04f77f033e01c9ffull };
319 
320 static const u64 *stm32f4_gate_map;
321 
322 static struct clk_hw **clks;
323 
324 static DEFINE_SPINLOCK(stm32f4_clk_lock);
325 static void __iomem *base;
326 
327 static struct regmap *pdrm;
328 
329 static int stm32fx_end_primary_clk;
330 
331 /*
332  * "Multiplier" device for APBx clocks.
333  *
334  * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
335  * mode, they also tap out the one of the low order state bits to run the
336  * timers. ST datasheets represent this feature as a (conditional) clock
337  * multiplier.
338  */
339 struct clk_apb_mul {
340 	struct clk_hw hw;
341 	u8 bit_idx;
342 };
343 
344 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
345 
346 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
347 					     unsigned long parent_rate)
348 {
349 	struct clk_apb_mul *am = to_clk_apb_mul(hw);
350 
351 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
352 		return parent_rate * 2;
353 
354 	return parent_rate;
355 }
356 
357 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
358 				   unsigned long *prate)
359 {
360 	struct clk_apb_mul *am = to_clk_apb_mul(hw);
361 	unsigned long mult = 1;
362 
363 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
364 		mult = 2;
365 
366 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
367 		unsigned long best_parent = rate / mult;
368 
369 		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
370 	}
371 
372 	return *prate * mult;
373 }
374 
375 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
376 				unsigned long parent_rate)
377 {
378 	/*
379 	 * We must report success but we can do so unconditionally because
380 	 * clk_apb_mul_round_rate returns values that ensure this call is a
381 	 * nop.
382 	 */
383 
384 	return 0;
385 }
386 
387 static const struct clk_ops clk_apb_mul_factor_ops = {
388 	.round_rate = clk_apb_mul_round_rate,
389 	.set_rate = clk_apb_mul_set_rate,
390 	.recalc_rate = clk_apb_mul_recalc_rate,
391 };
392 
393 static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
394 					const char *parent_name,
395 					unsigned long flags, u8 bit_idx)
396 {
397 	struct clk_apb_mul *am;
398 	struct clk_init_data init;
399 	struct clk *clk;
400 
401 	am = kzalloc(sizeof(*am), GFP_KERNEL);
402 	if (!am)
403 		return ERR_PTR(-ENOMEM);
404 
405 	am->bit_idx = bit_idx;
406 	am->hw.init = &init;
407 
408 	init.name = name;
409 	init.ops = &clk_apb_mul_factor_ops;
410 	init.flags = flags;
411 	init.parent_names = &parent_name;
412 	init.num_parents = 1;
413 
414 	clk = clk_register(dev, &am->hw);
415 
416 	if (IS_ERR(clk))
417 		kfree(am);
418 
419 	return clk;
420 }
421 
422 enum {
423 	PLL,
424 	PLL_I2S,
425 	PLL_SAI,
426 };
427 
428 static const struct clk_div_table pll_divp_table[] = {
429 	{ 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
430 };
431 
432 static const struct clk_div_table pll_divq_table[] = {
433 	{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
434 	{ 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
435 	{ 14, 14 }, { 15, 15 },
436 	{ 0 }
437 };
438 
439 static const struct clk_div_table pll_divr_table[] = {
440 	{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
441 };
442 
443 struct stm32f4_pll {
444 	spinlock_t *lock;
445 	struct	clk_gate gate;
446 	u8 offset;
447 	u8 bit_rdy_idx;
448 	u8 status;
449 	u8 n_start;
450 };
451 
452 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
453 
454 struct stm32f4_pll_post_div_data {
455 	int idx;
456 	u8 pll_num;
457 	const char *name;
458 	const char *parent;
459 	u8 flag;
460 	u8 offset;
461 	u8 shift;
462 	u8 width;
463 	u8 flag_div;
464 	const struct clk_div_table *div_table;
465 };
466 
467 struct stm32f4_vco_data {
468 	const char *vco_name;
469 	u8 offset;
470 	u8 bit_idx;
471 	u8 bit_rdy_idx;
472 };
473 
474 static const struct stm32f4_vco_data  vco_data[] = {
475 	{ "vco",     STM32F4_RCC_PLLCFGR,    24, 25 },
476 	{ "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
477 	{ "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
478 };
479 
480 
481 static const struct clk_div_table post_divr_table[] = {
482 	{ 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
483 };
484 
485 #define MAX_POST_DIV 3
486 static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
487 	{ CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
488 		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
489 
490 	{ CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
491 		CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
492 
493 	{ NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
494 		STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
495 };
496 
497 struct stm32f4_div_data {
498 	u8 shift;
499 	u8 width;
500 	u8 flag_div;
501 	const struct clk_div_table *div_table;
502 };
503 
504 #define MAX_PLL_DIV 3
505 static const struct stm32f4_div_data  div_data[MAX_PLL_DIV] = {
506 	{ 16, 2, 0, pll_divp_table },
507 	{ 24, 4, 0, pll_divq_table },
508 	{ 28, 3, 0, pll_divr_table },
509 };
510 
511 struct stm32f4_pll_data {
512 	u8 pll_num;
513 	u8 n_start;
514 	const char *div_name[MAX_PLL_DIV];
515 };
516 
517 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
518 	{ PLL,	   192, { "pll", "pll48",    NULL	} },
519 	{ PLL_I2S, 192, { NULL,  "plli2s-q", "plli2s-r" } },
520 	{ PLL_SAI,  49, { NULL,  "pllsai-q", "pllsai-r" } },
521 };
522 
523 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
524 	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
525 	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
526 	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
527 };
528 
529 static int stm32f4_pll_is_enabled(struct clk_hw *hw)
530 {
531 	return clk_gate_ops.is_enabled(hw);
532 }
533 
534 #define PLL_TIMEOUT 10000
535 
536 static int stm32f4_pll_enable(struct clk_hw *hw)
537 {
538 	struct clk_gate *gate = to_clk_gate(hw);
539 	struct stm32f4_pll *pll = to_stm32f4_pll(gate);
540 	int bit_status;
541 	unsigned int timeout = PLL_TIMEOUT;
542 
543 	if (clk_gate_ops.is_enabled(hw))
544 		return 0;
545 
546 	clk_gate_ops.enable(hw);
547 
548 	do {
549 		bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
550 
551 	} while (bit_status && --timeout);
552 
553 	return bit_status;
554 }
555 
556 static void stm32f4_pll_disable(struct clk_hw *hw)
557 {
558 	clk_gate_ops.disable(hw);
559 }
560 
561 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
562 		unsigned long parent_rate)
563 {
564 	struct clk_gate *gate = to_clk_gate(hw);
565 	struct stm32f4_pll *pll = to_stm32f4_pll(gate);
566 	unsigned long n;
567 
568 	n = (readl(base + pll->offset) >> 6) & 0x1ff;
569 
570 	return parent_rate * n;
571 }
572 
573 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
574 		unsigned long *prate)
575 {
576 	struct clk_gate *gate = to_clk_gate(hw);
577 	struct stm32f4_pll *pll = to_stm32f4_pll(gate);
578 	unsigned long n;
579 
580 	n = rate / *prate;
581 
582 	if (n < pll->n_start)
583 		n = pll->n_start;
584 	else if (n > 432)
585 		n = 432;
586 
587 	return *prate * n;
588 }
589 
590 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
591 				unsigned long parent_rate)
592 {
593 	struct clk_gate *gate = to_clk_gate(hw);
594 	struct stm32f4_pll *pll = to_stm32f4_pll(gate);
595 
596 	unsigned long n;
597 	unsigned long val;
598 	int pll_state;
599 
600 	pll_state = stm32f4_pll_is_enabled(hw);
601 
602 	if (pll_state)
603 		stm32f4_pll_disable(hw);
604 
605 	n = rate  / parent_rate;
606 
607 	val = readl(base + pll->offset) & ~(0x1ff << 6);
608 
609 	writel(val | ((n & 0x1ff) <<  6), base + pll->offset);
610 
611 	if (pll_state)
612 		stm32f4_pll_enable(hw);
613 
614 	return 0;
615 }
616 
617 static const struct clk_ops stm32f4_pll_gate_ops = {
618 	.enable		= stm32f4_pll_enable,
619 	.disable	= stm32f4_pll_disable,
620 	.is_enabled	= stm32f4_pll_is_enabled,
621 	.recalc_rate	= stm32f4_pll_recalc,
622 	.round_rate	= stm32f4_pll_round_rate,
623 	.set_rate	= stm32f4_pll_set_rate,
624 };
625 
626 struct stm32f4_pll_div {
627 	struct clk_divider div;
628 	struct clk_hw *hw_pll;
629 };
630 
631 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
632 
633 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
634 		unsigned long parent_rate)
635 {
636 	return clk_divider_ops.recalc_rate(hw, parent_rate);
637 }
638 
639 static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
640 				unsigned long *prate)
641 {
642 	return clk_divider_ops.round_rate(hw, rate, prate);
643 }
644 
645 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
646 				unsigned long parent_rate)
647 {
648 	int pll_state, ret;
649 
650 	struct clk_divider *div = to_clk_divider(hw);
651 	struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
652 
653 	pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
654 
655 	if (pll_state)
656 		stm32f4_pll_disable(pll_div->hw_pll);
657 
658 	ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
659 
660 	if (pll_state)
661 		stm32f4_pll_enable(pll_div->hw_pll);
662 
663 	return ret;
664 }
665 
666 static const struct clk_ops stm32f4_pll_div_ops = {
667 	.recalc_rate = stm32f4_pll_div_recalc_rate,
668 	.round_rate = stm32f4_pll_div_round_rate,
669 	.set_rate = stm32f4_pll_div_set_rate,
670 };
671 
672 static struct clk_hw *clk_register_pll_div(const char *name,
673 		const char *parent_name, unsigned long flags,
674 		void __iomem *reg, u8 shift, u8 width,
675 		u8 clk_divider_flags, const struct clk_div_table *table,
676 		struct clk_hw *pll_hw, spinlock_t *lock)
677 {
678 	struct stm32f4_pll_div *pll_div;
679 	struct clk_hw *hw;
680 	struct clk_init_data init;
681 	int ret;
682 
683 	/* allocate the divider */
684 	pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
685 	if (!pll_div)
686 		return ERR_PTR(-ENOMEM);
687 
688 	init.name = name;
689 	init.ops = &stm32f4_pll_div_ops;
690 	init.flags = flags;
691 	init.parent_names = (parent_name ? &parent_name : NULL);
692 	init.num_parents = (parent_name ? 1 : 0);
693 
694 	/* struct clk_divider assignments */
695 	pll_div->div.reg = reg;
696 	pll_div->div.shift = shift;
697 	pll_div->div.width = width;
698 	pll_div->div.flags = clk_divider_flags;
699 	pll_div->div.lock = lock;
700 	pll_div->div.table = table;
701 	pll_div->div.hw.init = &init;
702 
703 	pll_div->hw_pll = pll_hw;
704 
705 	/* register the clock */
706 	hw = &pll_div->div.hw;
707 	ret = clk_hw_register(NULL, hw);
708 	if (ret) {
709 		kfree(pll_div);
710 		hw = ERR_PTR(ret);
711 	}
712 
713 	return hw;
714 }
715 
716 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
717 		const struct stm32f4_pll_data *data,  spinlock_t *lock)
718 {
719 	struct stm32f4_pll *pll;
720 	struct clk_init_data init = { NULL };
721 	void __iomem *reg;
722 	struct clk_hw *pll_hw;
723 	int ret;
724 	int i;
725 	const struct stm32f4_vco_data *vco;
726 
727 
728 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
729 	if (!pll)
730 		return ERR_PTR(-ENOMEM);
731 
732 	vco = &vco_data[data->pll_num];
733 
734 	init.name = vco->vco_name;
735 	init.ops = &stm32f4_pll_gate_ops;
736 	init.flags = CLK_SET_RATE_GATE;
737 	init.parent_names = &pllsrc;
738 	init.num_parents = 1;
739 
740 	pll->gate.lock = lock;
741 	pll->gate.reg = base + STM32F4_RCC_CR;
742 	pll->gate.bit_idx = vco->bit_idx;
743 	pll->gate.hw.init = &init;
744 
745 	pll->offset = vco->offset;
746 	pll->n_start = data->n_start;
747 	pll->bit_rdy_idx = vco->bit_rdy_idx;
748 	pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
749 
750 	reg = base + pll->offset;
751 
752 	pll_hw = &pll->gate.hw;
753 	ret = clk_hw_register(NULL, pll_hw);
754 	if (ret) {
755 		kfree(pll);
756 		return ERR_PTR(ret);
757 	}
758 
759 	for (i = 0; i < MAX_PLL_DIV; i++)
760 		if (data->div_name[i])
761 			clk_register_pll_div(data->div_name[i],
762 					vco->vco_name,
763 					0,
764 					reg,
765 					div_data[i].shift,
766 					div_data[i].width,
767 					div_data[i].flag_div,
768 					div_data[i].div_table,
769 					pll_hw,
770 					lock);
771 	return pll_hw;
772 }
773 
774 /*
775  * Converts the primary and secondary indices (as they appear in DT) to an
776  * offset into our struct clock array.
777  */
778 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
779 {
780 	u64 table[MAX_GATE_MAP];
781 
782 	if (primary == 1) {
783 		if (WARN_ON(secondary >= stm32fx_end_primary_clk))
784 			return -EINVAL;
785 		return secondary;
786 	}
787 
788 	memcpy(table, stm32f4_gate_map, sizeof(table));
789 
790 	/* only bits set in table can be used as indices */
791 	if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
792 		    0 == (table[BIT_ULL_WORD(secondary)] &
793 			  BIT_ULL_MASK(secondary))))
794 		return -EINVAL;
795 
796 	/* mask out bits above our current index */
797 	table[BIT_ULL_WORD(secondary)] &=
798 	    GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
799 
800 	return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
801 	       (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
802 	       (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
803 }
804 
805 static struct clk_hw *
806 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
807 {
808 	int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
809 
810 	if (i < 0)
811 		return ERR_PTR(-EINVAL);
812 
813 	return clks[i];
814 }
815 
816 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
817 
818 static inline void disable_power_domain_write_protection(void)
819 {
820 	if (pdrm)
821 		regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
822 }
823 
824 static inline void enable_power_domain_write_protection(void)
825 {
826 	if (pdrm)
827 		regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
828 }
829 
830 static inline void sofware_reset_backup_domain(void)
831 {
832 	unsigned long val;
833 
834 	val = readl(base + STM32F4_RCC_BDCR);
835 	writel(val | BIT(16), base + STM32F4_RCC_BDCR);
836 	writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
837 }
838 
839 struct stm32_rgate {
840 	struct	clk_gate gate;
841 	u8	bit_rdy_idx;
842 };
843 
844 #define RGATE_TIMEOUT 50000
845 
846 static int rgclk_enable(struct clk_hw *hw)
847 {
848 	struct clk_gate *gate = to_clk_gate(hw);
849 	struct stm32_rgate *rgate = to_rgclk(gate);
850 	int bit_status;
851 	unsigned int timeout = RGATE_TIMEOUT;
852 
853 	if (clk_gate_ops.is_enabled(hw))
854 		return 0;
855 
856 	disable_power_domain_write_protection();
857 
858 	clk_gate_ops.enable(hw);
859 
860 	do {
861 		bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
862 		if (bit_status)
863 			udelay(100);
864 
865 	} while (bit_status && --timeout);
866 
867 	enable_power_domain_write_protection();
868 
869 	return bit_status;
870 }
871 
872 static void rgclk_disable(struct clk_hw *hw)
873 {
874 	clk_gate_ops.disable(hw);
875 }
876 
877 static int rgclk_is_enabled(struct clk_hw *hw)
878 {
879 	return clk_gate_ops.is_enabled(hw);
880 }
881 
882 static const struct clk_ops rgclk_ops = {
883 	.enable = rgclk_enable,
884 	.disable = rgclk_disable,
885 	.is_enabled = rgclk_is_enabled,
886 };
887 
888 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
889 		const char *parent_name, unsigned long flags,
890 		void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
891 		u8 clk_gate_flags, spinlock_t *lock)
892 {
893 	struct stm32_rgate *rgate;
894 	struct clk_init_data init = { NULL };
895 	struct clk_hw *hw;
896 	int ret;
897 
898 	rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
899 	if (!rgate)
900 		return ERR_PTR(-ENOMEM);
901 
902 	init.name = name;
903 	init.ops = &rgclk_ops;
904 	init.flags = flags;
905 	init.parent_names = &parent_name;
906 	init.num_parents = 1;
907 
908 	rgate->bit_rdy_idx = bit_rdy_idx;
909 
910 	rgate->gate.lock = lock;
911 	rgate->gate.reg = reg;
912 	rgate->gate.bit_idx = bit_idx;
913 	rgate->gate.hw.init = &init;
914 
915 	hw = &rgate->gate.hw;
916 	ret = clk_hw_register(dev, hw);
917 	if (ret) {
918 		kfree(rgate);
919 		hw = ERR_PTR(ret);
920 	}
921 
922 	return hw;
923 }
924 
925 static int cclk_gate_enable(struct clk_hw *hw)
926 {
927 	int ret;
928 
929 	disable_power_domain_write_protection();
930 
931 	ret = clk_gate_ops.enable(hw);
932 
933 	enable_power_domain_write_protection();
934 
935 	return ret;
936 }
937 
938 static void cclk_gate_disable(struct clk_hw *hw)
939 {
940 	disable_power_domain_write_protection();
941 
942 	clk_gate_ops.disable(hw);
943 
944 	enable_power_domain_write_protection();
945 }
946 
947 static int cclk_gate_is_enabled(struct clk_hw *hw)
948 {
949 	return clk_gate_ops.is_enabled(hw);
950 }
951 
952 static const struct clk_ops cclk_gate_ops = {
953 	.enable		= cclk_gate_enable,
954 	.disable	= cclk_gate_disable,
955 	.is_enabled	= cclk_gate_is_enabled,
956 };
957 
958 static u8 cclk_mux_get_parent(struct clk_hw *hw)
959 {
960 	return clk_mux_ops.get_parent(hw);
961 }
962 
963 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
964 {
965 	int ret;
966 
967 	disable_power_domain_write_protection();
968 
969 	sofware_reset_backup_domain();
970 
971 	ret = clk_mux_ops.set_parent(hw, index);
972 
973 	enable_power_domain_write_protection();
974 
975 	return ret;
976 }
977 
978 static const struct clk_ops cclk_mux_ops = {
979 	.get_parent = cclk_mux_get_parent,
980 	.set_parent = cclk_mux_set_parent,
981 };
982 
983 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
984 		const char * const *parent_names, int num_parents,
985 		void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
986 		spinlock_t *lock)
987 {
988 	struct clk_hw *hw;
989 	struct clk_gate *gate;
990 	struct clk_mux *mux;
991 
992 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
993 	if (!gate) {
994 		hw = ERR_PTR(-EINVAL);
995 		goto fail;
996 	}
997 
998 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
999 	if (!mux) {
1000 		kfree(gate);
1001 		hw = ERR_PTR(-EINVAL);
1002 		goto fail;
1003 	}
1004 
1005 	gate->reg = reg;
1006 	gate->bit_idx = bit_idx;
1007 	gate->flags = 0;
1008 	gate->lock = lock;
1009 
1010 	mux->reg = reg;
1011 	mux->shift = shift;
1012 	mux->mask = 3;
1013 	mux->flags = 0;
1014 
1015 	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
1016 			&mux->hw, &cclk_mux_ops,
1017 			NULL, NULL,
1018 			&gate->hw, &cclk_gate_ops,
1019 			flags);
1020 
1021 	if (IS_ERR(hw)) {
1022 		kfree(gate);
1023 		kfree(mux);
1024 	}
1025 
1026 fail:
1027 	return hw;
1028 }
1029 
1030 static const char *sys_parents[] __initdata =   { "hsi", NULL, "pll" };
1031 
1032 static const struct clk_div_table ahb_div_table[] = {
1033 	{ 0x0,   1 }, { 0x1,   1 }, { 0x2,   1 }, { 0x3,   1 },
1034 	{ 0x4,   1 }, { 0x5,   1 }, { 0x6,   1 }, { 0x7,   1 },
1035 	{ 0x8,   2 }, { 0x9,   4 }, { 0xa,   8 }, { 0xb,  16 },
1036 	{ 0xc,  64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1037 	{ 0 },
1038 };
1039 
1040 static const struct clk_div_table apb_div_table[] = {
1041 	{ 0,  1 }, { 0,  1 }, { 0,  1 }, { 0,  1 },
1042 	{ 4,  2 }, { 5,  4 }, { 6,  8 }, { 7, 16 },
1043 	{ 0 },
1044 };
1045 
1046 static const char *rtc_parents[4] = {
1047 	"no-clock", "lse", "lsi", "hse-rtc"
1048 };
1049 
1050 static const char *lcd_parent[1] = { "pllsai-r-div" };
1051 
1052 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1053 
1054 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1055 	"no-clock" };
1056 
1057 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1058 
1059 static const char *sdmux_parents[2] = { "pll48", "sys" };
1060 
1061 static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1062 
1063 static const char *spdif_parent[1] = { "plli2s-p" };
1064 
1065 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1066 
1067 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1068 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1069 
1070 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1071 
1072 struct stm32_aux_clk {
1073 	int idx;
1074 	const char *name;
1075 	const char * const *parent_names;
1076 	int num_parents;
1077 	int offset_mux;
1078 	u8 shift;
1079 	u8 mask;
1080 	int offset_gate;
1081 	u8 bit_idx;
1082 	unsigned long flags;
1083 };
1084 
1085 struct stm32f4_clk_data {
1086 	const struct stm32f4_gate_data *gates_data;
1087 	const u64 *gates_map;
1088 	int gates_num;
1089 	const struct stm32f4_pll_data *pll_data;
1090 	const struct stm32_aux_clk *aux_clk;
1091 	int aux_clk_num;
1092 	int end_primary;
1093 };
1094 
1095 static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1096 	{
1097 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1098 		NO_MUX, 0, 0,
1099 		STM32F4_RCC_APB2ENR, 26,
1100 		CLK_SET_RATE_PARENT
1101 	},
1102 	{
1103 		CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1104 		STM32F4_RCC_CFGR, 23, 1,
1105 		NO_GATE, 0,
1106 		CLK_SET_RATE_PARENT
1107 	},
1108 	{
1109 		CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1110 		STM32F4_RCC_DCKCFGR, 20, 3,
1111 		STM32F4_RCC_APB2ENR, 22,
1112 		CLK_SET_RATE_PARENT
1113 	},
1114 	{
1115 		CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1116 		STM32F4_RCC_DCKCFGR, 22, 3,
1117 		STM32F4_RCC_APB2ENR, 22,
1118 		CLK_SET_RATE_PARENT
1119 	},
1120 };
1121 
1122 static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1123 	{
1124 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1125 		NO_MUX, 0, 0,
1126 		STM32F4_RCC_APB2ENR, 26,
1127 		CLK_SET_RATE_PARENT
1128 	},
1129 	{
1130 		CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1131 		STM32F4_RCC_CFGR, 23, 1,
1132 		NO_GATE, 0,
1133 		CLK_SET_RATE_PARENT
1134 	},
1135 	{
1136 		CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1137 		STM32F4_RCC_DCKCFGR, 20, 3,
1138 		STM32F4_RCC_APB2ENR, 22,
1139 		CLK_SET_RATE_PARENT
1140 	},
1141 	{
1142 		CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1143 		STM32F4_RCC_DCKCFGR, 22, 3,
1144 		STM32F4_RCC_APB2ENR, 22,
1145 		CLK_SET_RATE_PARENT
1146 	},
1147 	{
1148 		NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1149 		STM32F4_RCC_DCKCFGR, 27, 1,
1150 		NO_GATE, 0,
1151 		0
1152 	},
1153 	{
1154 		NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1155 		STM32F4_RCC_DCKCFGR, 28, 1,
1156 		NO_GATE, 0,
1157 		0
1158 	},
1159 };
1160 
1161 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1162 	{
1163 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1164 		NO_MUX, 0, 0,
1165 		STM32F4_RCC_APB2ENR, 26,
1166 		CLK_SET_RATE_PARENT
1167 	},
1168 	{
1169 		CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1170 		STM32F4_RCC_CFGR, 23, 1,
1171 		NO_GATE, 0,
1172 		CLK_SET_RATE_PARENT
1173 	},
1174 	{
1175 		CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1176 		STM32F4_RCC_DCKCFGR, 20, 3,
1177 		STM32F4_RCC_APB2ENR, 22,
1178 		CLK_SET_RATE_PARENT
1179 	},
1180 	{
1181 		CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1182 		STM32F4_RCC_DCKCFGR, 22, 3,
1183 		STM32F4_RCC_APB2ENR, 23,
1184 		CLK_SET_RATE_PARENT
1185 	},
1186 	{
1187 		NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1188 		STM32F7_RCC_DCKCFGR2, 27, 1,
1189 		NO_GATE, 0,
1190 		0
1191 	},
1192 	{
1193 		NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1194 		STM32F7_RCC_DCKCFGR2, 28, 1,
1195 		NO_GATE, 0,
1196 		0
1197 	},
1198 	{
1199 		CLK_HDMI_CEC, "hdmi-cec",
1200 		hdmi_parents, ARRAY_SIZE(hdmi_parents),
1201 		STM32F7_RCC_DCKCFGR2, 26, 1,
1202 		NO_GATE, 0,
1203 		0
1204 	},
1205 	{
1206 		CLK_SPDIF, "spdif-rx",
1207 		spdif_parent, ARRAY_SIZE(spdif_parent),
1208 		STM32F7_RCC_DCKCFGR2, 22, 3,
1209 		STM32F4_RCC_APB2ENR, 23,
1210 		CLK_SET_RATE_PARENT
1211 	},
1212 	{
1213 		CLK_USART1, "usart1",
1214 		uart_parents1, ARRAY_SIZE(uart_parents1),
1215 		STM32F7_RCC_DCKCFGR2, 0, 3,
1216 		STM32F4_RCC_APB2ENR, 4,
1217 		CLK_SET_RATE_PARENT,
1218 	},
1219 	{
1220 		CLK_USART2, "usart2",
1221 		uart_parents2, ARRAY_SIZE(uart_parents1),
1222 		STM32F7_RCC_DCKCFGR2, 2, 3,
1223 		STM32F4_RCC_APB1ENR, 17,
1224 		CLK_SET_RATE_PARENT,
1225 	},
1226 	{
1227 		CLK_USART3, "usart3",
1228 		uart_parents2, ARRAY_SIZE(uart_parents1),
1229 		STM32F7_RCC_DCKCFGR2, 4, 3,
1230 		STM32F4_RCC_APB1ENR, 18,
1231 		CLK_SET_RATE_PARENT,
1232 	},
1233 	{
1234 		CLK_UART4, "uart4",
1235 		uart_parents2, ARRAY_SIZE(uart_parents1),
1236 		STM32F7_RCC_DCKCFGR2, 6, 3,
1237 		STM32F4_RCC_APB1ENR, 19,
1238 		CLK_SET_RATE_PARENT,
1239 	},
1240 	{
1241 		CLK_UART5, "uart5",
1242 		uart_parents2, ARRAY_SIZE(uart_parents1),
1243 		STM32F7_RCC_DCKCFGR2, 8, 3,
1244 		STM32F4_RCC_APB1ENR, 20,
1245 		CLK_SET_RATE_PARENT,
1246 	},
1247 	{
1248 		CLK_USART6, "usart6",
1249 		uart_parents1, ARRAY_SIZE(uart_parents1),
1250 		STM32F7_RCC_DCKCFGR2, 10, 3,
1251 		STM32F4_RCC_APB2ENR, 5,
1252 		CLK_SET_RATE_PARENT,
1253 	},
1254 
1255 	{
1256 		CLK_UART7, "uart7",
1257 		uart_parents2, ARRAY_SIZE(uart_parents1),
1258 		STM32F7_RCC_DCKCFGR2, 12, 3,
1259 		STM32F4_RCC_APB1ENR, 30,
1260 		CLK_SET_RATE_PARENT,
1261 	},
1262 	{
1263 		CLK_UART8, "uart8",
1264 		uart_parents2, ARRAY_SIZE(uart_parents1),
1265 		STM32F7_RCC_DCKCFGR2, 14, 3,
1266 		STM32F4_RCC_APB1ENR, 31,
1267 		CLK_SET_RATE_PARENT,
1268 	},
1269 	{
1270 		CLK_I2C1, "i2c1",
1271 		i2c_parents, ARRAY_SIZE(i2c_parents),
1272 		STM32F7_RCC_DCKCFGR2, 16, 3,
1273 		STM32F4_RCC_APB1ENR, 21,
1274 		CLK_SET_RATE_PARENT,
1275 	},
1276 	{
1277 		CLK_I2C2, "i2c2",
1278 		i2c_parents, ARRAY_SIZE(i2c_parents),
1279 		STM32F7_RCC_DCKCFGR2, 18, 3,
1280 		STM32F4_RCC_APB1ENR, 22,
1281 		CLK_SET_RATE_PARENT,
1282 	},
1283 	{
1284 		CLK_I2C3, "i2c3",
1285 		i2c_parents, ARRAY_SIZE(i2c_parents),
1286 		STM32F7_RCC_DCKCFGR2, 20, 3,
1287 		STM32F4_RCC_APB1ENR, 23,
1288 		CLK_SET_RATE_PARENT,
1289 	},
1290 	{
1291 		CLK_I2C4, "i2c4",
1292 		i2c_parents, ARRAY_SIZE(i2c_parents),
1293 		STM32F7_RCC_DCKCFGR2, 22, 3,
1294 		STM32F4_RCC_APB1ENR, 24,
1295 		CLK_SET_RATE_PARENT,
1296 	},
1297 
1298 	{
1299 		CLK_LPTIMER, "lptim1",
1300 		lptim_parent, ARRAY_SIZE(lptim_parent),
1301 		STM32F7_RCC_DCKCFGR2, 24, 3,
1302 		STM32F4_RCC_APB1ENR, 9,
1303 		CLK_SET_RATE_PARENT
1304 	},
1305 };
1306 
1307 static const struct stm32f4_clk_data stm32f429_clk_data = {
1308 	.end_primary	= END_PRIMARY_CLK,
1309 	.gates_data	= stm32f429_gates,
1310 	.gates_map	= stm32f42xx_gate_map,
1311 	.gates_num	= ARRAY_SIZE(stm32f429_gates),
1312 	.pll_data	= stm32f429_pll,
1313 	.aux_clk	= stm32f429_aux_clk,
1314 	.aux_clk_num	= ARRAY_SIZE(stm32f429_aux_clk),
1315 };
1316 
1317 static const struct stm32f4_clk_data stm32f469_clk_data = {
1318 	.end_primary	= END_PRIMARY_CLK,
1319 	.gates_data	= stm32f469_gates,
1320 	.gates_map	= stm32f46xx_gate_map,
1321 	.gates_num	= ARRAY_SIZE(stm32f469_gates),
1322 	.pll_data	= stm32f469_pll,
1323 	.aux_clk	= stm32f469_aux_clk,
1324 	.aux_clk_num	= ARRAY_SIZE(stm32f469_aux_clk),
1325 };
1326 
1327 static const struct stm32f4_clk_data stm32f746_clk_data = {
1328 	.end_primary	= END_PRIMARY_CLK_F7,
1329 	.gates_data	= stm32f746_gates,
1330 	.gates_map	= stm32f746_gate_map,
1331 	.gates_num	= ARRAY_SIZE(stm32f746_gates),
1332 	.pll_data	= stm32f469_pll,
1333 	.aux_clk	= stm32f746_aux_clk,
1334 	.aux_clk_num	= ARRAY_SIZE(stm32f746_aux_clk),
1335 };
1336 
1337 static const struct of_device_id stm32f4_of_match[] = {
1338 	{
1339 		.compatible = "st,stm32f42xx-rcc",
1340 		.data = &stm32f429_clk_data
1341 	},
1342 	{
1343 		.compatible = "st,stm32f469-rcc",
1344 		.data = &stm32f469_clk_data
1345 	},
1346 	{
1347 		.compatible = "st,stm32f746-rcc",
1348 		.data = &stm32f746_clk_data
1349 	},
1350 	{}
1351 };
1352 
1353 static struct clk_hw *stm32_register_aux_clk(const char *name,
1354 		const char * const *parent_names, int num_parents,
1355 		int offset_mux, u8 shift, u8 mask,
1356 		int offset_gate, u8 bit_idx,
1357 		unsigned long flags, spinlock_t *lock)
1358 {
1359 	struct clk_hw *hw;
1360 	struct clk_gate *gate = NULL;
1361 	struct clk_mux *mux = NULL;
1362 	struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1363 	const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1364 
1365 	if (offset_gate != NO_GATE) {
1366 		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1367 		if (!gate) {
1368 			hw = ERR_PTR(-EINVAL);
1369 			goto fail;
1370 		}
1371 
1372 		gate->reg = base + offset_gate;
1373 		gate->bit_idx = bit_idx;
1374 		gate->flags = 0;
1375 		gate->lock = lock;
1376 		gate_hw = &gate->hw;
1377 		gate_ops = &clk_gate_ops;
1378 	}
1379 
1380 	if (offset_mux != NO_MUX) {
1381 		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1382 		if (!mux) {
1383 			hw = ERR_PTR(-EINVAL);
1384 			goto fail;
1385 		}
1386 
1387 		mux->reg = base + offset_mux;
1388 		mux->shift = shift;
1389 		mux->mask = mask;
1390 		mux->flags = 0;
1391 		mux_hw = &mux->hw;
1392 		mux_ops = &clk_mux_ops;
1393 	}
1394 
1395 	if (mux_hw == NULL && gate_hw == NULL) {
1396 		hw = ERR_PTR(-EINVAL);
1397 		goto fail;
1398 	}
1399 
1400 	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1401 			mux_hw, mux_ops,
1402 			NULL, NULL,
1403 			gate_hw, gate_ops,
1404 			flags);
1405 
1406 fail:
1407 	if (IS_ERR(hw)) {
1408 		kfree(gate);
1409 		kfree(mux);
1410 	}
1411 
1412 	return hw;
1413 }
1414 
1415 static void __init stm32f4_rcc_init(struct device_node *np)
1416 {
1417 	const char *hse_clk, *i2s_in_clk;
1418 	int n;
1419 	const struct of_device_id *match;
1420 	const struct stm32f4_clk_data *data;
1421 	unsigned long pllcfgr;
1422 	const char *pllsrc;
1423 	unsigned long pllm;
1424 
1425 	base = of_iomap(np, 0);
1426 	if (!base) {
1427 		pr_err("%s: unable to map resource", np->name);
1428 		return;
1429 	}
1430 
1431 	pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1432 	if (IS_ERR(pdrm)) {
1433 		pdrm = NULL;
1434 		pr_warn("%s: Unable to get syscfg\n", __func__);
1435 	}
1436 
1437 	match = of_match_node(stm32f4_of_match, np);
1438 	if (WARN_ON(!match))
1439 		return;
1440 
1441 	data = match->data;
1442 
1443 	stm32fx_end_primary_clk = data->end_primary;
1444 
1445 	clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1446 			sizeof(*clks), GFP_KERNEL);
1447 	if (!clks)
1448 		goto fail;
1449 
1450 	stm32f4_gate_map = data->gates_map;
1451 
1452 	hse_clk = of_clk_get_parent_name(np, 0);
1453 
1454 	i2s_in_clk = of_clk_get_parent_name(np, 1);
1455 
1456 	i2s_parents[1] = i2s_in_clk;
1457 	sai_parents[2] = i2s_in_clk;
1458 
1459 	clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1460 			NULL, 0, 16000000, 160000);
1461 
1462 	pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
1463 	pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
1464 	pllm = pllcfgr & 0x3f;
1465 
1466 	clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
1467 					       0, 1, pllm);
1468 
1469 	stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1470 			&stm32f4_clk_lock);
1471 
1472 	clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1473 			&data->pll_data[1], &stm32f4_clk_lock);
1474 
1475 	clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1476 			&data->pll_data[2], &stm32f4_clk_lock);
1477 
1478 	for (n = 0; n < MAX_POST_DIV; n++) {
1479 		const struct stm32f4_pll_post_div_data *post_div;
1480 		struct clk_hw *hw;
1481 
1482 		post_div = &post_div_data[n];
1483 
1484 		hw = clk_register_pll_div(post_div->name,
1485 				post_div->parent,
1486 				post_div->flag,
1487 				base + post_div->offset,
1488 				post_div->shift,
1489 				post_div->width,
1490 				post_div->flag_div,
1491 				post_div->div_table,
1492 				clks[post_div->pll_num],
1493 				&stm32f4_clk_lock);
1494 
1495 		if (post_div->idx != NO_IDX)
1496 			clks[post_div->idx] = hw;
1497 	}
1498 
1499 	sys_parents[1] = hse_clk;
1500 
1501 	clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1502 	    NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1503 	    base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1504 
1505 	clk_register_divider_table(NULL, "ahb_div", "sys",
1506 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1507 				   4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1508 
1509 	clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1510 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1511 				   10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1512 	clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1513 			     CLK_SET_RATE_PARENT, 12);
1514 
1515 	clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1516 				   CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1517 				   13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1518 	clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1519 			     CLK_SET_RATE_PARENT, 15);
1520 
1521 	clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1522 						  0, 1, 8);
1523 	clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1524 					       0, 1, 1);
1525 
1526 	for (n = 0; n < data->gates_num; n++) {
1527 		const struct stm32f4_gate_data *gd;
1528 		unsigned int secondary;
1529 		int idx;
1530 
1531 		gd = &data->gates_data[n];
1532 		secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1533 			gd->bit_idx;
1534 		idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1535 
1536 		if (idx < 0)
1537 			goto fail;
1538 
1539 		clks[idx] = clk_hw_register_gate(
1540 		    NULL, gd->name, gd->parent_name, gd->flags,
1541 		    base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1542 
1543 		if (IS_ERR(clks[idx])) {
1544 			pr_err("%s: Unable to register leaf clock %s\n",
1545 			       np->full_name, gd->name);
1546 			goto fail;
1547 		}
1548 	}
1549 
1550 	clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1551 			base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1552 
1553 	if (IS_ERR(clks[CLK_LSI])) {
1554 		pr_err("Unable to register lsi clock\n");
1555 		goto fail;
1556 	}
1557 
1558 	clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1559 			base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1560 
1561 	if (IS_ERR(clks[CLK_LSE])) {
1562 		pr_err("Unable to register lse clock\n");
1563 		goto fail;
1564 	}
1565 
1566 	clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1567 			0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1568 			&stm32f4_clk_lock);
1569 
1570 	if (IS_ERR(clks[CLK_HSE_RTC])) {
1571 		pr_err("Unable to register hse-rtc clock\n");
1572 		goto fail;
1573 	}
1574 
1575 	clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1576 			base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1577 
1578 	if (IS_ERR(clks[CLK_RTC])) {
1579 		pr_err("Unable to register rtc clock\n");
1580 		goto fail;
1581 	}
1582 
1583 	for (n = 0; n < data->aux_clk_num; n++) {
1584 		const struct stm32_aux_clk *aux_clk;
1585 		struct clk_hw *hw;
1586 
1587 		aux_clk = &data->aux_clk[n];
1588 
1589 		hw = stm32_register_aux_clk(aux_clk->name,
1590 				aux_clk->parent_names, aux_clk->num_parents,
1591 				aux_clk->offset_mux, aux_clk->shift,
1592 				aux_clk->mask, aux_clk->offset_gate,
1593 				aux_clk->bit_idx, aux_clk->flags,
1594 				&stm32f4_clk_lock);
1595 
1596 		if (IS_ERR(hw)) {
1597 			pr_warn("Unable to register %s clk\n", aux_clk->name);
1598 			continue;
1599 		}
1600 
1601 		if (aux_clk->idx != NO_IDX)
1602 			clks[aux_clk->idx] = hw;
1603 	}
1604 
1605 	if (of_device_is_compatible(np, "st,stm32f746-rcc"))
1606 
1607 		clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1608 				1, 488);
1609 
1610 	of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1611 	return;
1612 fail:
1613 	kfree(clks);
1614 	iounmap(base);
1615 }
1616 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1617 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1618 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1619