1 /* 2 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator 3 * 4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 5 * Rabeeh Khoury <rabeeh@solid-run.com> 6 * 7 * References: 8 * [1] "Si5351A/B/C Data Sheet" 9 * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf 10 * [2] "Manually Generating an Si5351 Register Map" 11 * http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/errno.h> 26 #include <linux/rational.h> 27 #include <linux/i2c.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_data/si5351.h> 30 #include <linux/regmap.h> 31 #include <linux/slab.h> 32 #include <linux/string.h> 33 #include <asm/div64.h> 34 35 #include "clk-si5351.h" 36 37 struct si5351_driver_data; 38 39 struct si5351_parameters { 40 unsigned long p1; 41 unsigned long p2; 42 unsigned long p3; 43 int valid; 44 }; 45 46 struct si5351_hw_data { 47 struct clk_hw hw; 48 struct si5351_driver_data *drvdata; 49 struct si5351_parameters params; 50 unsigned char num; 51 }; 52 53 struct si5351_driver_data { 54 enum si5351_variant variant; 55 struct i2c_client *client; 56 struct regmap *regmap; 57 58 struct clk *pxtal; 59 const char *pxtal_name; 60 struct clk_hw xtal; 61 struct clk *pclkin; 62 const char *pclkin_name; 63 struct clk_hw clkin; 64 65 struct si5351_hw_data pll[2]; 66 struct si5351_hw_data *msynth; 67 struct si5351_hw_data *clkout; 68 size_t num_clkout; 69 }; 70 71 static const char * const si5351_input_names[] = { 72 "xtal", "clkin" 73 }; 74 static const char * const si5351_pll_names[] = { 75 "si5351_plla", "si5351_pllb", "si5351_vxco" 76 }; 77 static const char * const si5351_msynth_names[] = { 78 "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7" 79 }; 80 static const char * const si5351_clkout_names[] = { 81 "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7" 82 }; 83 84 /* 85 * Si5351 i2c regmap 86 */ 87 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg) 88 { 89 u32 val; 90 int ret; 91 92 ret = regmap_read(drvdata->regmap, reg, &val); 93 if (ret) { 94 dev_err(&drvdata->client->dev, 95 "unable to read from reg%02x\n", reg); 96 return 0; 97 } 98 99 return (u8)val; 100 } 101 102 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata, 103 u8 reg, u8 count, u8 *buf) 104 { 105 return regmap_bulk_read(drvdata->regmap, reg, buf, count); 106 } 107 108 static inline int si5351_reg_write(struct si5351_driver_data *drvdata, 109 u8 reg, u8 val) 110 { 111 return regmap_write(drvdata->regmap, reg, val); 112 } 113 114 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata, 115 u8 reg, u8 count, const u8 *buf) 116 { 117 return regmap_raw_write(drvdata->regmap, reg, buf, count); 118 } 119 120 static inline int si5351_set_bits(struct si5351_driver_data *drvdata, 121 u8 reg, u8 mask, u8 val) 122 { 123 return regmap_update_bits(drvdata->regmap, reg, mask, val); 124 } 125 126 static inline u8 si5351_msynth_params_address(int num) 127 { 128 if (num > 5) 129 return SI5351_CLK6_PARAMETERS + (num - 6); 130 return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num); 131 } 132 133 static void si5351_read_parameters(struct si5351_driver_data *drvdata, 134 u8 reg, struct si5351_parameters *params) 135 { 136 u8 buf[SI5351_PARAMETERS_LENGTH]; 137 138 switch (reg) { 139 case SI5351_CLK6_PARAMETERS: 140 case SI5351_CLK7_PARAMETERS: 141 buf[0] = si5351_reg_read(drvdata, reg); 142 params->p1 = buf[0]; 143 params->p2 = 0; 144 params->p3 = 1; 145 break; 146 default: 147 si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); 148 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; 149 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7]; 150 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1]; 151 } 152 params->valid = 1; 153 } 154 155 static void si5351_write_parameters(struct si5351_driver_data *drvdata, 156 u8 reg, struct si5351_parameters *params) 157 { 158 u8 buf[SI5351_PARAMETERS_LENGTH]; 159 160 switch (reg) { 161 case SI5351_CLK6_PARAMETERS: 162 case SI5351_CLK7_PARAMETERS: 163 buf[0] = params->p1 & 0xff; 164 si5351_reg_write(drvdata, reg, buf[0]); 165 break; 166 default: 167 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff; 168 buf[1] = params->p3 & 0xff; 169 /* save rdiv and divby4 */ 170 buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03; 171 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; 172 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; 173 buf[4] = params->p1 & 0xff; 174 buf[5] = ((params->p3 & 0xf0000) >> 12) | 175 ((params->p2 & 0xf0000) >> 16); 176 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff; 177 buf[7] = params->p2 & 0xff; 178 si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); 179 } 180 } 181 182 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg) 183 { 184 switch (reg) { 185 case SI5351_DEVICE_STATUS: 186 case SI5351_INTERRUPT_STATUS: 187 case SI5351_PLL_RESET: 188 return true; 189 } 190 return false; 191 } 192 193 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg) 194 { 195 /* reserved registers */ 196 if (reg >= 4 && reg <= 8) 197 return false; 198 if (reg >= 10 && reg <= 14) 199 return false; 200 if (reg >= 173 && reg <= 176) 201 return false; 202 if (reg >= 178 && reg <= 182) 203 return false; 204 /* read-only */ 205 if (reg == SI5351_DEVICE_STATUS) 206 return false; 207 return true; 208 } 209 210 static const struct regmap_config si5351_regmap_config = { 211 .reg_bits = 8, 212 .val_bits = 8, 213 .cache_type = REGCACHE_RBTREE, 214 .max_register = 187, 215 .writeable_reg = si5351_regmap_is_writeable, 216 .volatile_reg = si5351_regmap_is_volatile, 217 }; 218 219 /* 220 * Si5351 xtal clock input 221 */ 222 static int si5351_xtal_prepare(struct clk_hw *hw) 223 { 224 struct si5351_driver_data *drvdata = 225 container_of(hw, struct si5351_driver_data, xtal); 226 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, 227 SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE); 228 return 0; 229 } 230 231 static void si5351_xtal_unprepare(struct clk_hw *hw) 232 { 233 struct si5351_driver_data *drvdata = 234 container_of(hw, struct si5351_driver_data, xtal); 235 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, 236 SI5351_XTAL_ENABLE, 0); 237 } 238 239 static const struct clk_ops si5351_xtal_ops = { 240 .prepare = si5351_xtal_prepare, 241 .unprepare = si5351_xtal_unprepare, 242 }; 243 244 /* 245 * Si5351 clkin clock input (Si5351C only) 246 */ 247 static int si5351_clkin_prepare(struct clk_hw *hw) 248 { 249 struct si5351_driver_data *drvdata = 250 container_of(hw, struct si5351_driver_data, clkin); 251 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, 252 SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE); 253 return 0; 254 } 255 256 static void si5351_clkin_unprepare(struct clk_hw *hw) 257 { 258 struct si5351_driver_data *drvdata = 259 container_of(hw, struct si5351_driver_data, clkin); 260 si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE, 261 SI5351_CLKIN_ENABLE, 0); 262 } 263 264 /* 265 * CMOS clock source constraints: 266 * The input frequency range of the PLL is 10Mhz to 40MHz. 267 * If CLKIN is >40MHz, the input divider must be used. 268 */ 269 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw, 270 unsigned long parent_rate) 271 { 272 struct si5351_driver_data *drvdata = 273 container_of(hw, struct si5351_driver_data, clkin); 274 unsigned long rate; 275 unsigned char idiv; 276 277 rate = parent_rate; 278 if (parent_rate > 160000000) { 279 idiv = SI5351_CLKIN_DIV_8; 280 rate /= 8; 281 } else if (parent_rate > 80000000) { 282 idiv = SI5351_CLKIN_DIV_4; 283 rate /= 4; 284 } else if (parent_rate > 40000000) { 285 idiv = SI5351_CLKIN_DIV_2; 286 rate /= 2; 287 } else { 288 idiv = SI5351_CLKIN_DIV_1; 289 } 290 291 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, 292 SI5351_CLKIN_DIV_MASK, idiv); 293 294 dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n", 295 __func__, (1 << (idiv >> 6)), rate); 296 297 return rate; 298 } 299 300 static const struct clk_ops si5351_clkin_ops = { 301 .prepare = si5351_clkin_prepare, 302 .unprepare = si5351_clkin_unprepare, 303 .recalc_rate = si5351_clkin_recalc_rate, 304 }; 305 306 /* 307 * Si5351 vxco clock input (Si5351B only) 308 */ 309 310 static int si5351_vxco_prepare(struct clk_hw *hw) 311 { 312 struct si5351_hw_data *hwdata = 313 container_of(hw, struct si5351_hw_data, hw); 314 315 dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n"); 316 317 return 0; 318 } 319 320 static void si5351_vxco_unprepare(struct clk_hw *hw) 321 { 322 } 323 324 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw, 325 unsigned long parent_rate) 326 { 327 return 0; 328 } 329 330 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate, 331 unsigned long parent) 332 { 333 return 0; 334 } 335 336 static const struct clk_ops si5351_vxco_ops = { 337 .prepare = si5351_vxco_prepare, 338 .unprepare = si5351_vxco_unprepare, 339 .recalc_rate = si5351_vxco_recalc_rate, 340 .set_rate = si5351_vxco_set_rate, 341 }; 342 343 /* 344 * Si5351 pll a/b 345 * 346 * Feedback Multisynth Divider Equations [2] 347 * 348 * fVCO = fIN * (a + b/c) 349 * 350 * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and 351 * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV 352 * 353 * Feedback Multisynth Register Equations 354 * 355 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 356 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c 357 * (3) MSNx_P3[19:0] = c 358 * 359 * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c 360 * 361 * Using (4) on (1) yields: 362 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512 363 * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c 364 * 365 * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128 366 * = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3) 367 * 368 */ 369 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata, 370 int num, enum si5351_pll_src parent) 371 { 372 u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; 373 374 if (parent == SI5351_PLL_SRC_DEFAULT) 375 return 0; 376 377 if (num > 2) 378 return -EINVAL; 379 380 if (drvdata->variant != SI5351_VARIANT_C && 381 parent != SI5351_PLL_SRC_XTAL) 382 return -EINVAL; 383 384 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask, 385 (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask); 386 return 0; 387 } 388 389 static unsigned char si5351_pll_get_parent(struct clk_hw *hw) 390 { 391 struct si5351_hw_data *hwdata = 392 container_of(hw, struct si5351_hw_data, hw); 393 u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; 394 u8 val; 395 396 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); 397 398 return (val & mask) ? 1 : 0; 399 } 400 401 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index) 402 { 403 struct si5351_hw_data *hwdata = 404 container_of(hw, struct si5351_hw_data, hw); 405 406 if (hwdata->drvdata->variant != SI5351_VARIANT_C && 407 index > 0) 408 return -EPERM; 409 410 if (index > 1) 411 return -EINVAL; 412 413 return _si5351_pll_reparent(hwdata->drvdata, hwdata->num, 414 (index == 0) ? SI5351_PLL_SRC_XTAL : 415 SI5351_PLL_SRC_CLKIN); 416 } 417 418 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw, 419 unsigned long parent_rate) 420 { 421 struct si5351_hw_data *hwdata = 422 container_of(hw, struct si5351_hw_data, hw); 423 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : 424 SI5351_PLLB_PARAMETERS; 425 unsigned long long rate; 426 427 if (!hwdata->params.valid) 428 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); 429 430 if (hwdata->params.p3 == 0) 431 return parent_rate; 432 433 /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */ 434 rate = hwdata->params.p1 * hwdata->params.p3; 435 rate += 512 * hwdata->params.p3; 436 rate += hwdata->params.p2; 437 rate *= parent_rate; 438 do_div(rate, 128 * hwdata->params.p3); 439 440 dev_dbg(&hwdata->drvdata->client->dev, 441 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", 442 __func__, clk_hw_get_name(hw), 443 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, 444 parent_rate, (unsigned long)rate); 445 446 return (unsigned long)rate; 447 } 448 449 static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate, 450 unsigned long *parent_rate) 451 { 452 struct si5351_hw_data *hwdata = 453 container_of(hw, struct si5351_hw_data, hw); 454 unsigned long rfrac, denom, a, b, c; 455 unsigned long long lltmp; 456 457 if (rate < SI5351_PLL_VCO_MIN) 458 rate = SI5351_PLL_VCO_MIN; 459 if (rate > SI5351_PLL_VCO_MAX) 460 rate = SI5351_PLL_VCO_MAX; 461 462 /* determine integer part of feedback equation */ 463 a = rate / *parent_rate; 464 465 if (a < SI5351_PLL_A_MIN) 466 rate = *parent_rate * SI5351_PLL_A_MIN; 467 if (a > SI5351_PLL_A_MAX) 468 rate = *parent_rate * SI5351_PLL_A_MAX; 469 470 /* find best approximation for b/c = fVCO mod fIN */ 471 denom = 1000 * 1000; 472 lltmp = rate % (*parent_rate); 473 lltmp *= denom; 474 do_div(lltmp, *parent_rate); 475 rfrac = (unsigned long)lltmp; 476 477 b = 0; 478 c = 1; 479 if (rfrac) 480 rational_best_approximation(rfrac, denom, 481 SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c); 482 483 /* calculate parameters */ 484 hwdata->params.p3 = c; 485 hwdata->params.p2 = (128 * b) % c; 486 hwdata->params.p1 = 128 * a; 487 hwdata->params.p1 += (128 * b / c); 488 hwdata->params.p1 -= 512; 489 490 /* recalculate rate by fIN * (a + b/c) */ 491 lltmp = *parent_rate; 492 lltmp *= b; 493 do_div(lltmp, c); 494 495 rate = (unsigned long)lltmp; 496 rate += *parent_rate * a; 497 498 dev_dbg(&hwdata->drvdata->client->dev, 499 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", 500 __func__, clk_hw_get_name(hw), a, b, c, 501 *parent_rate, rate); 502 503 return rate; 504 } 505 506 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, 507 unsigned long parent_rate) 508 { 509 struct si5351_hw_data *hwdata = 510 container_of(hw, struct si5351_hw_data, hw); 511 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : 512 SI5351_PLLB_PARAMETERS; 513 514 /* write multisynth parameters */ 515 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); 516 517 /* plla/pllb ctrl is in clk6/clk7 ctrl registers */ 518 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num, 519 SI5351_CLK_INTEGER_MODE, 520 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); 521 522 /* Do a pll soft reset on the affected pll */ 523 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, 524 hwdata->num == 0 ? SI5351_PLL_RESET_A : 525 SI5351_PLL_RESET_B); 526 527 dev_dbg(&hwdata->drvdata->client->dev, 528 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", 529 __func__, clk_hw_get_name(hw), 530 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, 531 parent_rate, rate); 532 533 return 0; 534 } 535 536 static const struct clk_ops si5351_pll_ops = { 537 .set_parent = si5351_pll_set_parent, 538 .get_parent = si5351_pll_get_parent, 539 .recalc_rate = si5351_pll_recalc_rate, 540 .round_rate = si5351_pll_round_rate, 541 .set_rate = si5351_pll_set_rate, 542 }; 543 544 /* 545 * Si5351 multisync divider 546 * 547 * for fOUT <= 150 MHz: 548 * 549 * fOUT = (fIN * (a + b/c)) / CLKOUTDIV 550 * 551 * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and 552 * fIN = fVCO0, fVCO1 553 * 554 * Output Clock Multisynth Register Equations 555 * 556 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512 557 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c 558 * MSx_P3[19:0] = c 559 * 560 * MS[6,7] are integer (P1) divide only, P1 = divide value, 561 * P2 and P3 are not applicable 562 * 563 * for 150MHz < fOUT <= 160MHz: 564 * 565 * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b 566 */ 567 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata, 568 int num, enum si5351_multisynth_src parent) 569 { 570 if (parent == SI5351_MULTISYNTH_SRC_DEFAULT) 571 return 0; 572 573 if (num > 8) 574 return -EINVAL; 575 576 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT, 577 (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 : 578 SI5351_CLK_PLL_SELECT); 579 return 0; 580 } 581 582 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw) 583 { 584 struct si5351_hw_data *hwdata = 585 container_of(hw, struct si5351_hw_data, hw); 586 u8 val; 587 588 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); 589 590 return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0; 591 } 592 593 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index) 594 { 595 struct si5351_hw_data *hwdata = 596 container_of(hw, struct si5351_hw_data, hw); 597 598 return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num, 599 (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 : 600 SI5351_MULTISYNTH_SRC_VCO1); 601 } 602 603 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw, 604 unsigned long parent_rate) 605 { 606 struct si5351_hw_data *hwdata = 607 container_of(hw, struct si5351_hw_data, hw); 608 u8 reg = si5351_msynth_params_address(hwdata->num); 609 unsigned long long rate; 610 unsigned long m; 611 612 if (!hwdata->params.valid) 613 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); 614 615 /* 616 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3) 617 * multisync6-7: fOUT = fIN / P1 618 */ 619 rate = parent_rate; 620 if (hwdata->num > 5) { 621 m = hwdata->params.p1; 622 } else if (hwdata->params.p3 == 0) { 623 return parent_rate; 624 } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & 625 SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) { 626 m = 4; 627 } else { 628 rate *= 128 * hwdata->params.p3; 629 m = hwdata->params.p1 * hwdata->params.p3; 630 m += hwdata->params.p2; 631 m += 512 * hwdata->params.p3; 632 } 633 634 if (m == 0) 635 return 0; 636 do_div(rate, m); 637 638 dev_dbg(&hwdata->drvdata->client->dev, 639 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", 640 __func__, clk_hw_get_name(hw), 641 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, 642 m, parent_rate, (unsigned long)rate); 643 644 return (unsigned long)rate; 645 } 646 647 static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, 648 unsigned long *parent_rate) 649 { 650 struct si5351_hw_data *hwdata = 651 container_of(hw, struct si5351_hw_data, hw); 652 unsigned long long lltmp; 653 unsigned long a, b, c; 654 int divby4; 655 656 /* multisync6-7 can only handle freqencies < 150MHz */ 657 if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ) 658 rate = SI5351_MULTISYNTH67_MAX_FREQ; 659 660 /* multisync frequency is 1MHz .. 160MHz */ 661 if (rate > SI5351_MULTISYNTH_MAX_FREQ) 662 rate = SI5351_MULTISYNTH_MAX_FREQ; 663 if (rate < SI5351_MULTISYNTH_MIN_FREQ) 664 rate = SI5351_MULTISYNTH_MIN_FREQ; 665 666 divby4 = 0; 667 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) 668 divby4 = 1; 669 670 /* multisync can set pll */ 671 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 672 /* 673 * find largest integer divider for max 674 * vco frequency and given target rate 675 */ 676 if (divby4 == 0) { 677 lltmp = SI5351_PLL_VCO_MAX; 678 do_div(lltmp, rate); 679 a = (unsigned long)lltmp; 680 } else 681 a = 4; 682 683 b = 0; 684 c = 1; 685 686 *parent_rate = a * rate; 687 } else if (hwdata->num >= 6) { 688 /* determine the closest integer divider */ 689 a = DIV_ROUND_CLOSEST(*parent_rate, rate); 690 if (a < SI5351_MULTISYNTH_A_MIN) 691 a = SI5351_MULTISYNTH_A_MIN; 692 if (a > SI5351_MULTISYNTH67_A_MAX) 693 a = SI5351_MULTISYNTH67_A_MAX; 694 695 b = 0; 696 c = 1; 697 } else { 698 unsigned long rfrac, denom; 699 700 /* disable divby4 */ 701 if (divby4) { 702 rate = SI5351_MULTISYNTH_DIVBY4_FREQ; 703 divby4 = 0; 704 } 705 706 /* determine integer part of divider equation */ 707 a = *parent_rate / rate; 708 if (a < SI5351_MULTISYNTH_A_MIN) 709 a = SI5351_MULTISYNTH_A_MIN; 710 if (a > SI5351_MULTISYNTH_A_MAX) 711 a = SI5351_MULTISYNTH_A_MAX; 712 713 /* find best approximation for b/c = fVCO mod fOUT */ 714 denom = 1000 * 1000; 715 lltmp = (*parent_rate) % rate; 716 lltmp *= denom; 717 do_div(lltmp, rate); 718 rfrac = (unsigned long)lltmp; 719 720 b = 0; 721 c = 1; 722 if (rfrac) 723 rational_best_approximation(rfrac, denom, 724 SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX, 725 &b, &c); 726 } 727 728 /* recalculate rate by fOUT = fIN / (a + b/c) */ 729 lltmp = *parent_rate; 730 lltmp *= c; 731 do_div(lltmp, a * c + b); 732 rate = (unsigned long)lltmp; 733 734 /* calculate parameters */ 735 if (divby4) { 736 hwdata->params.p3 = 1; 737 hwdata->params.p2 = 0; 738 hwdata->params.p1 = 0; 739 } else if (hwdata->num >= 6) { 740 hwdata->params.p3 = 0; 741 hwdata->params.p2 = 0; 742 hwdata->params.p1 = a; 743 } else { 744 hwdata->params.p3 = c; 745 hwdata->params.p2 = (128 * b) % c; 746 hwdata->params.p1 = 128 * a; 747 hwdata->params.p1 += (128 * b / c); 748 hwdata->params.p1 -= 512; 749 } 750 751 dev_dbg(&hwdata->drvdata->client->dev, 752 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", 753 __func__, clk_hw_get_name(hw), a, b, c, divby4, 754 *parent_rate, rate); 755 756 return rate; 757 } 758 759 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate, 760 unsigned long parent_rate) 761 { 762 struct si5351_hw_data *hwdata = 763 container_of(hw, struct si5351_hw_data, hw); 764 u8 reg = si5351_msynth_params_address(hwdata->num); 765 int divby4 = 0; 766 767 /* write multisynth parameters */ 768 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); 769 770 if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ) 771 divby4 = 1; 772 773 /* enable/disable integer mode and divby4 on multisynth0-5 */ 774 if (hwdata->num < 6) { 775 si5351_set_bits(hwdata->drvdata, reg + 2, 776 SI5351_OUTPUT_CLK_DIVBY4, 777 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0); 778 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, 779 SI5351_CLK_INTEGER_MODE, 780 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); 781 } 782 783 dev_dbg(&hwdata->drvdata->client->dev, 784 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", 785 __func__, clk_hw_get_name(hw), 786 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, 787 divby4, parent_rate, rate); 788 789 return 0; 790 } 791 792 static const struct clk_ops si5351_msynth_ops = { 793 .set_parent = si5351_msynth_set_parent, 794 .get_parent = si5351_msynth_get_parent, 795 .recalc_rate = si5351_msynth_recalc_rate, 796 .round_rate = si5351_msynth_round_rate, 797 .set_rate = si5351_msynth_set_rate, 798 }; 799 800 /* 801 * Si5351 clkout divider 802 */ 803 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata, 804 int num, enum si5351_clkout_src parent) 805 { 806 u8 val; 807 808 if (num > 8) 809 return -EINVAL; 810 811 switch (parent) { 812 case SI5351_CLKOUT_SRC_MSYNTH_N: 813 val = SI5351_CLK_INPUT_MULTISYNTH_N; 814 break; 815 case SI5351_CLKOUT_SRC_MSYNTH_0_4: 816 /* clk0/clk4 can only connect to its own multisync */ 817 if (num == 0 || num == 4) 818 val = SI5351_CLK_INPUT_MULTISYNTH_N; 819 else 820 val = SI5351_CLK_INPUT_MULTISYNTH_0_4; 821 break; 822 case SI5351_CLKOUT_SRC_XTAL: 823 val = SI5351_CLK_INPUT_XTAL; 824 break; 825 case SI5351_CLKOUT_SRC_CLKIN: 826 if (drvdata->variant != SI5351_VARIANT_C) 827 return -EINVAL; 828 829 val = SI5351_CLK_INPUT_CLKIN; 830 break; 831 default: 832 return 0; 833 } 834 835 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, 836 SI5351_CLK_INPUT_MASK, val); 837 return 0; 838 } 839 840 static int _si5351_clkout_set_drive_strength( 841 struct si5351_driver_data *drvdata, int num, 842 enum si5351_drive_strength drive) 843 { 844 u8 mask; 845 846 if (num > 8) 847 return -EINVAL; 848 849 switch (drive) { 850 case SI5351_DRIVE_2MA: 851 mask = SI5351_CLK_DRIVE_STRENGTH_2MA; 852 break; 853 case SI5351_DRIVE_4MA: 854 mask = SI5351_CLK_DRIVE_STRENGTH_4MA; 855 break; 856 case SI5351_DRIVE_6MA: 857 mask = SI5351_CLK_DRIVE_STRENGTH_6MA; 858 break; 859 case SI5351_DRIVE_8MA: 860 mask = SI5351_CLK_DRIVE_STRENGTH_8MA; 861 break; 862 default: 863 return 0; 864 } 865 866 si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, 867 SI5351_CLK_DRIVE_STRENGTH_MASK, mask); 868 return 0; 869 } 870 871 static int _si5351_clkout_set_disable_state( 872 struct si5351_driver_data *drvdata, int num, 873 enum si5351_disable_state state) 874 { 875 u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE : 876 SI5351_CLK7_4_DISABLE_STATE; 877 u8 shift = (num < 4) ? (2 * num) : (2 * (num-4)); 878 u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift; 879 u8 val; 880 881 if (num > 8) 882 return -EINVAL; 883 884 switch (state) { 885 case SI5351_DISABLE_LOW: 886 val = SI5351_CLK_DISABLE_STATE_LOW; 887 break; 888 case SI5351_DISABLE_HIGH: 889 val = SI5351_CLK_DISABLE_STATE_HIGH; 890 break; 891 case SI5351_DISABLE_FLOATING: 892 val = SI5351_CLK_DISABLE_STATE_FLOAT; 893 break; 894 case SI5351_DISABLE_NEVER: 895 val = SI5351_CLK_DISABLE_STATE_NEVER; 896 break; 897 default: 898 return 0; 899 } 900 901 si5351_set_bits(drvdata, reg, mask, val << shift); 902 903 return 0; 904 } 905 906 static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num) 907 { 908 u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num); 909 910 switch (val & SI5351_CLK_INPUT_MASK) { 911 case SI5351_CLK_INPUT_XTAL: 912 case SI5351_CLK_INPUT_CLKIN: 913 return; /* pll not used, no need to reset */ 914 } 915 916 si5351_reg_write(drvdata, SI5351_PLL_RESET, 917 val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B : 918 SI5351_PLL_RESET_A); 919 920 dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n", 921 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), 922 (val & SI5351_CLK_PLL_SELECT) ? 1 : 0); 923 } 924 925 static int si5351_clkout_prepare(struct clk_hw *hw) 926 { 927 struct si5351_hw_data *hwdata = 928 container_of(hw, struct si5351_hw_data, hw); 929 struct si5351_platform_data *pdata = 930 hwdata->drvdata->client->dev.platform_data; 931 932 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, 933 SI5351_CLK_POWERDOWN, 0); 934 935 /* 936 * Do a pll soft reset on the parent pll -- needed to get a 937 * deterministic phase relationship between the output clocks. 938 */ 939 if (pdata->clkout[hwdata->num].pll_reset) 940 _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num); 941 942 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, 943 (1 << hwdata->num), 0); 944 return 0; 945 } 946 947 static void si5351_clkout_unprepare(struct clk_hw *hw) 948 { 949 struct si5351_hw_data *hwdata = 950 container_of(hw, struct si5351_hw_data, hw); 951 952 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, 953 SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN); 954 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, 955 (1 << hwdata->num), (1 << hwdata->num)); 956 } 957 958 static u8 si5351_clkout_get_parent(struct clk_hw *hw) 959 { 960 struct si5351_hw_data *hwdata = 961 container_of(hw, struct si5351_hw_data, hw); 962 int index = 0; 963 unsigned char val; 964 965 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); 966 switch (val & SI5351_CLK_INPUT_MASK) { 967 case SI5351_CLK_INPUT_MULTISYNTH_N: 968 index = 0; 969 break; 970 case SI5351_CLK_INPUT_MULTISYNTH_0_4: 971 index = 1; 972 break; 973 case SI5351_CLK_INPUT_XTAL: 974 index = 2; 975 break; 976 case SI5351_CLK_INPUT_CLKIN: 977 index = 3; 978 break; 979 } 980 981 return index; 982 } 983 984 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index) 985 { 986 struct si5351_hw_data *hwdata = 987 container_of(hw, struct si5351_hw_data, hw); 988 enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT; 989 990 switch (index) { 991 case 0: 992 parent = SI5351_CLKOUT_SRC_MSYNTH_N; 993 break; 994 case 1: 995 parent = SI5351_CLKOUT_SRC_MSYNTH_0_4; 996 break; 997 case 2: 998 parent = SI5351_CLKOUT_SRC_XTAL; 999 break; 1000 case 3: 1001 parent = SI5351_CLKOUT_SRC_CLKIN; 1002 break; 1003 } 1004 1005 return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent); 1006 } 1007 1008 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, 1009 unsigned long parent_rate) 1010 { 1011 struct si5351_hw_data *hwdata = 1012 container_of(hw, struct si5351_hw_data, hw); 1013 unsigned char reg; 1014 unsigned char rdiv; 1015 1016 if (hwdata->num <= 5) 1017 reg = si5351_msynth_params_address(hwdata->num) + 2; 1018 else 1019 reg = SI5351_CLK6_7_OUTPUT_DIVIDER; 1020 1021 rdiv = si5351_reg_read(hwdata->drvdata, reg); 1022 if (hwdata->num == 6) { 1023 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; 1024 } else { 1025 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; 1026 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; 1027 } 1028 1029 return parent_rate >> rdiv; 1030 } 1031 1032 static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, 1033 unsigned long *parent_rate) 1034 { 1035 struct si5351_hw_data *hwdata = 1036 container_of(hw, struct si5351_hw_data, hw); 1037 unsigned char rdiv; 1038 1039 /* clkout6/7 can only handle output freqencies < 150MHz */ 1040 if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ) 1041 rate = SI5351_CLKOUT67_MAX_FREQ; 1042 1043 /* clkout freqency is 8kHz - 160MHz */ 1044 if (rate > SI5351_CLKOUT_MAX_FREQ) 1045 rate = SI5351_CLKOUT_MAX_FREQ; 1046 if (rate < SI5351_CLKOUT_MIN_FREQ) 1047 rate = SI5351_CLKOUT_MIN_FREQ; 1048 1049 /* request frequency if multisync master */ 1050 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 1051 /* use r divider for frequencies below 1MHz */ 1052 rdiv = SI5351_OUTPUT_CLK_DIV_1; 1053 while (rate < SI5351_MULTISYNTH_MIN_FREQ && 1054 rdiv < SI5351_OUTPUT_CLK_DIV_128) { 1055 rdiv += 1; 1056 rate *= 2; 1057 } 1058 *parent_rate = rate; 1059 } else { 1060 unsigned long new_rate, new_err, err; 1061 1062 /* round to closed rdiv */ 1063 rdiv = SI5351_OUTPUT_CLK_DIV_1; 1064 new_rate = *parent_rate; 1065 err = abs(new_rate - rate); 1066 do { 1067 new_rate >>= 1; 1068 new_err = abs(new_rate - rate); 1069 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) 1070 break; 1071 rdiv++; 1072 err = new_err; 1073 } while (1); 1074 } 1075 rate = *parent_rate >> rdiv; 1076 1077 dev_dbg(&hwdata->drvdata->client->dev, 1078 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", 1079 __func__, clk_hw_get_name(hw), (1 << rdiv), 1080 *parent_rate, rate); 1081 1082 return rate; 1083 } 1084 1085 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate, 1086 unsigned long parent_rate) 1087 { 1088 struct si5351_hw_data *hwdata = 1089 container_of(hw, struct si5351_hw_data, hw); 1090 unsigned long new_rate, new_err, err; 1091 unsigned char rdiv; 1092 1093 /* round to closed rdiv */ 1094 rdiv = SI5351_OUTPUT_CLK_DIV_1; 1095 new_rate = parent_rate; 1096 err = abs(new_rate - rate); 1097 do { 1098 new_rate >>= 1; 1099 new_err = abs(new_rate - rate); 1100 if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128) 1101 break; 1102 rdiv++; 1103 err = new_err; 1104 } while (1); 1105 1106 /* write output divider */ 1107 switch (hwdata->num) { 1108 case 6: 1109 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, 1110 SI5351_OUTPUT_CLK6_DIV_MASK, rdiv); 1111 break; 1112 case 7: 1113 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, 1114 SI5351_OUTPUT_CLK_DIV_MASK, 1115 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); 1116 break; 1117 default: 1118 si5351_set_bits(hwdata->drvdata, 1119 si5351_msynth_params_address(hwdata->num) + 2, 1120 SI5351_OUTPUT_CLK_DIV_MASK, 1121 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT); 1122 } 1123 1124 /* powerup clkout */ 1125 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, 1126 SI5351_CLK_POWERDOWN, 0); 1127 1128 dev_dbg(&hwdata->drvdata->client->dev, 1129 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", 1130 __func__, clk_hw_get_name(hw), (1 << rdiv), 1131 parent_rate, rate); 1132 1133 return 0; 1134 } 1135 1136 static const struct clk_ops si5351_clkout_ops = { 1137 .prepare = si5351_clkout_prepare, 1138 .unprepare = si5351_clkout_unprepare, 1139 .set_parent = si5351_clkout_set_parent, 1140 .get_parent = si5351_clkout_get_parent, 1141 .recalc_rate = si5351_clkout_recalc_rate, 1142 .round_rate = si5351_clkout_round_rate, 1143 .set_rate = si5351_clkout_set_rate, 1144 }; 1145 1146 /* 1147 * Si5351 i2c probe and DT 1148 */ 1149 #ifdef CONFIG_OF 1150 static const struct of_device_id si5351_dt_ids[] = { 1151 { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, }, 1152 { .compatible = "silabs,si5351a-msop", 1153 .data = (void *)SI5351_VARIANT_A3, }, 1154 { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, }, 1155 { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, }, 1156 { } 1157 }; 1158 MODULE_DEVICE_TABLE(of, si5351_dt_ids); 1159 1160 static int si5351_dt_parse(struct i2c_client *client, 1161 enum si5351_variant variant) 1162 { 1163 struct device_node *child, *np = client->dev.of_node; 1164 struct si5351_platform_data *pdata; 1165 struct property *prop; 1166 const __be32 *p; 1167 int num = 0; 1168 u32 val; 1169 1170 if (np == NULL) 1171 return 0; 1172 1173 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); 1174 if (!pdata) 1175 return -ENOMEM; 1176 1177 /* 1178 * property silabs,pll-source : <num src>, [<..>] 1179 * allow to selectively set pll source 1180 */ 1181 of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) { 1182 if (num >= 2) { 1183 dev_err(&client->dev, 1184 "invalid pll %d on pll-source prop\n", num); 1185 return -EINVAL; 1186 } 1187 1188 p = of_prop_next_u32(prop, p, &val); 1189 if (!p) { 1190 dev_err(&client->dev, 1191 "missing pll-source for pll %d\n", num); 1192 return -EINVAL; 1193 } 1194 1195 switch (val) { 1196 case 0: 1197 pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; 1198 break; 1199 case 1: 1200 if (variant != SI5351_VARIANT_C) { 1201 dev_err(&client->dev, 1202 "invalid parent %d for pll %d\n", 1203 val, num); 1204 return -EINVAL; 1205 } 1206 pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN; 1207 break; 1208 default: 1209 dev_err(&client->dev, 1210 "invalid parent %d for pll %d\n", val, num); 1211 return -EINVAL; 1212 } 1213 } 1214 1215 /* per clkout properties */ 1216 for_each_child_of_node(np, child) { 1217 if (of_property_read_u32(child, "reg", &num)) { 1218 dev_err(&client->dev, "missing reg property of %pOFn\n", 1219 child); 1220 goto put_child; 1221 } 1222 1223 if (num >= 8 || 1224 (variant == SI5351_VARIANT_A3 && num >= 3)) { 1225 dev_err(&client->dev, "invalid clkout %d\n", num); 1226 goto put_child; 1227 } 1228 1229 if (!of_property_read_u32(child, "silabs,multisynth-source", 1230 &val)) { 1231 switch (val) { 1232 case 0: 1233 pdata->clkout[num].multisynth_src = 1234 SI5351_MULTISYNTH_SRC_VCO0; 1235 break; 1236 case 1: 1237 pdata->clkout[num].multisynth_src = 1238 SI5351_MULTISYNTH_SRC_VCO1; 1239 break; 1240 default: 1241 dev_err(&client->dev, 1242 "invalid parent %d for multisynth %d\n", 1243 val, num); 1244 goto put_child; 1245 } 1246 } 1247 1248 if (!of_property_read_u32(child, "silabs,clock-source", &val)) { 1249 switch (val) { 1250 case 0: 1251 pdata->clkout[num].clkout_src = 1252 SI5351_CLKOUT_SRC_MSYNTH_N; 1253 break; 1254 case 1: 1255 pdata->clkout[num].clkout_src = 1256 SI5351_CLKOUT_SRC_MSYNTH_0_4; 1257 break; 1258 case 2: 1259 pdata->clkout[num].clkout_src = 1260 SI5351_CLKOUT_SRC_XTAL; 1261 break; 1262 case 3: 1263 if (variant != SI5351_VARIANT_C) { 1264 dev_err(&client->dev, 1265 "invalid parent %d for clkout %d\n", 1266 val, num); 1267 goto put_child; 1268 } 1269 pdata->clkout[num].clkout_src = 1270 SI5351_CLKOUT_SRC_CLKIN; 1271 break; 1272 default: 1273 dev_err(&client->dev, 1274 "invalid parent %d for clkout %d\n", 1275 val, num); 1276 goto put_child; 1277 } 1278 } 1279 1280 if (!of_property_read_u32(child, "silabs,drive-strength", 1281 &val)) { 1282 switch (val) { 1283 case SI5351_DRIVE_2MA: 1284 case SI5351_DRIVE_4MA: 1285 case SI5351_DRIVE_6MA: 1286 case SI5351_DRIVE_8MA: 1287 pdata->clkout[num].drive = val; 1288 break; 1289 default: 1290 dev_err(&client->dev, 1291 "invalid drive strength %d for clkout %d\n", 1292 val, num); 1293 goto put_child; 1294 } 1295 } 1296 1297 if (!of_property_read_u32(child, "silabs,disable-state", 1298 &val)) { 1299 switch (val) { 1300 case 0: 1301 pdata->clkout[num].disable_state = 1302 SI5351_DISABLE_LOW; 1303 break; 1304 case 1: 1305 pdata->clkout[num].disable_state = 1306 SI5351_DISABLE_HIGH; 1307 break; 1308 case 2: 1309 pdata->clkout[num].disable_state = 1310 SI5351_DISABLE_FLOATING; 1311 break; 1312 case 3: 1313 pdata->clkout[num].disable_state = 1314 SI5351_DISABLE_NEVER; 1315 break; 1316 default: 1317 dev_err(&client->dev, 1318 "invalid disable state %d for clkout %d\n", 1319 val, num); 1320 goto put_child; 1321 } 1322 } 1323 1324 if (!of_property_read_u32(child, "clock-frequency", &val)) 1325 pdata->clkout[num].rate = val; 1326 1327 pdata->clkout[num].pll_master = 1328 of_property_read_bool(child, "silabs,pll-master"); 1329 1330 pdata->clkout[num].pll_reset = 1331 of_property_read_bool(child, "silabs,pll-reset"); 1332 } 1333 client->dev.platform_data = pdata; 1334 1335 return 0; 1336 put_child: 1337 of_node_put(child); 1338 return -EINVAL; 1339 } 1340 1341 static struct clk_hw * 1342 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data) 1343 { 1344 struct si5351_driver_data *drvdata = data; 1345 unsigned int idx = clkspec->args[0]; 1346 1347 if (idx >= drvdata->num_clkout) { 1348 pr_err("%s: invalid index %u\n", __func__, idx); 1349 return ERR_PTR(-EINVAL); 1350 } 1351 1352 return &drvdata->clkout[idx].hw; 1353 } 1354 #else 1355 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant) 1356 { 1357 return 0; 1358 } 1359 1360 static struct clk_hw * 1361 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data) 1362 { 1363 return NULL; 1364 } 1365 #endif /* CONFIG_OF */ 1366 1367 static int si5351_i2c_probe(struct i2c_client *client, 1368 const struct i2c_device_id *id) 1369 { 1370 enum si5351_variant variant = (enum si5351_variant)id->driver_data; 1371 struct si5351_platform_data *pdata; 1372 struct si5351_driver_data *drvdata; 1373 struct clk_init_data init; 1374 const char *parent_names[4]; 1375 u8 num_parents, num_clocks; 1376 int ret, n; 1377 1378 ret = si5351_dt_parse(client, variant); 1379 if (ret) 1380 return ret; 1381 1382 pdata = client->dev.platform_data; 1383 if (!pdata) 1384 return -EINVAL; 1385 1386 drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL); 1387 if (!drvdata) 1388 return -ENOMEM; 1389 1390 i2c_set_clientdata(client, drvdata); 1391 drvdata->client = client; 1392 drvdata->variant = variant; 1393 drvdata->pxtal = devm_clk_get(&client->dev, "xtal"); 1394 drvdata->pclkin = devm_clk_get(&client->dev, "clkin"); 1395 1396 if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER || 1397 PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER) 1398 return -EPROBE_DEFER; 1399 1400 /* 1401 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL, 1402 * VARIANT_C can have CLKIN instead. 1403 */ 1404 if (IS_ERR(drvdata->pxtal) && 1405 (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) { 1406 dev_err(&client->dev, "missing parent clock\n"); 1407 return -EINVAL; 1408 } 1409 1410 drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); 1411 if (IS_ERR(drvdata->regmap)) { 1412 dev_err(&client->dev, "failed to allocate register map\n"); 1413 return PTR_ERR(drvdata->regmap); 1414 } 1415 1416 /* Disable interrupts */ 1417 si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0); 1418 /* Ensure pll select is on XTAL for Si5351A/B */ 1419 if (drvdata->variant != SI5351_VARIANT_C) 1420 si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, 1421 SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0); 1422 1423 /* setup clock configuration */ 1424 for (n = 0; n < 2; n++) { 1425 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]); 1426 if (ret) { 1427 dev_err(&client->dev, 1428 "failed to reparent pll %d to %d\n", 1429 n, pdata->pll_src[n]); 1430 return ret; 1431 } 1432 } 1433 1434 for (n = 0; n < 8; n++) { 1435 ret = _si5351_msynth_reparent(drvdata, n, 1436 pdata->clkout[n].multisynth_src); 1437 if (ret) { 1438 dev_err(&client->dev, 1439 "failed to reparent multisynth %d to %d\n", 1440 n, pdata->clkout[n].multisynth_src); 1441 return ret; 1442 } 1443 1444 ret = _si5351_clkout_reparent(drvdata, n, 1445 pdata->clkout[n].clkout_src); 1446 if (ret) { 1447 dev_err(&client->dev, 1448 "failed to reparent clkout %d to %d\n", 1449 n, pdata->clkout[n].clkout_src); 1450 return ret; 1451 } 1452 1453 ret = _si5351_clkout_set_drive_strength(drvdata, n, 1454 pdata->clkout[n].drive); 1455 if (ret) { 1456 dev_err(&client->dev, 1457 "failed set drive strength of clkout%d to %d\n", 1458 n, pdata->clkout[n].drive); 1459 return ret; 1460 } 1461 1462 ret = _si5351_clkout_set_disable_state(drvdata, n, 1463 pdata->clkout[n].disable_state); 1464 if (ret) { 1465 dev_err(&client->dev, 1466 "failed set disable state of clkout%d to %d\n", 1467 n, pdata->clkout[n].disable_state); 1468 return ret; 1469 } 1470 } 1471 1472 /* register xtal input clock gate */ 1473 memset(&init, 0, sizeof(init)); 1474 init.name = si5351_input_names[0]; 1475 init.ops = &si5351_xtal_ops; 1476 init.flags = 0; 1477 if (!IS_ERR(drvdata->pxtal)) { 1478 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal); 1479 init.parent_names = &drvdata->pxtal_name; 1480 init.num_parents = 1; 1481 } 1482 drvdata->xtal.init = &init; 1483 ret = devm_clk_hw_register(&client->dev, &drvdata->xtal); 1484 if (ret) { 1485 dev_err(&client->dev, "unable to register %s\n", init.name); 1486 return ret; 1487 } 1488 1489 /* register clkin input clock gate */ 1490 if (drvdata->variant == SI5351_VARIANT_C) { 1491 memset(&init, 0, sizeof(init)); 1492 init.name = si5351_input_names[1]; 1493 init.ops = &si5351_clkin_ops; 1494 if (!IS_ERR(drvdata->pclkin)) { 1495 drvdata->pclkin_name = __clk_get_name(drvdata->pclkin); 1496 init.parent_names = &drvdata->pclkin_name; 1497 init.num_parents = 1; 1498 } 1499 drvdata->clkin.init = &init; 1500 ret = devm_clk_hw_register(&client->dev, &drvdata->clkin); 1501 if (ret) { 1502 dev_err(&client->dev, "unable to register %s\n", 1503 init.name); 1504 return ret; 1505 } 1506 } 1507 1508 /* Si5351C allows to mux either xtal or clkin to PLL input */ 1509 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1; 1510 parent_names[0] = si5351_input_names[0]; 1511 parent_names[1] = si5351_input_names[1]; 1512 1513 /* register PLLA */ 1514 drvdata->pll[0].num = 0; 1515 drvdata->pll[0].drvdata = drvdata; 1516 drvdata->pll[0].hw.init = &init; 1517 memset(&init, 0, sizeof(init)); 1518 init.name = si5351_pll_names[0]; 1519 init.ops = &si5351_pll_ops; 1520 init.flags = 0; 1521 init.parent_names = parent_names; 1522 init.num_parents = num_parents; 1523 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw); 1524 if (ret) { 1525 dev_err(&client->dev, "unable to register %s\n", init.name); 1526 return ret; 1527 } 1528 1529 /* register PLLB or VXCO (Si5351B) */ 1530 drvdata->pll[1].num = 1; 1531 drvdata->pll[1].drvdata = drvdata; 1532 drvdata->pll[1].hw.init = &init; 1533 memset(&init, 0, sizeof(init)); 1534 if (drvdata->variant == SI5351_VARIANT_B) { 1535 init.name = si5351_pll_names[2]; 1536 init.ops = &si5351_vxco_ops; 1537 init.flags = 0; 1538 init.parent_names = NULL; 1539 init.num_parents = 0; 1540 } else { 1541 init.name = si5351_pll_names[1]; 1542 init.ops = &si5351_pll_ops; 1543 init.flags = 0; 1544 init.parent_names = parent_names; 1545 init.num_parents = num_parents; 1546 } 1547 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw); 1548 if (ret) { 1549 dev_err(&client->dev, "unable to register %s\n", init.name); 1550 return ret; 1551 } 1552 1553 /* register clk multisync and clk out divider */ 1554 num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8; 1555 parent_names[0] = si5351_pll_names[0]; 1556 if (drvdata->variant == SI5351_VARIANT_B) 1557 parent_names[1] = si5351_pll_names[2]; 1558 else 1559 parent_names[1] = si5351_pll_names[1]; 1560 1561 drvdata->msynth = devm_kcalloc(&client->dev, num_clocks, 1562 sizeof(*drvdata->msynth), GFP_KERNEL); 1563 drvdata->clkout = devm_kcalloc(&client->dev, num_clocks, 1564 sizeof(*drvdata->clkout), GFP_KERNEL); 1565 drvdata->num_clkout = num_clocks; 1566 1567 if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) { 1568 ret = -ENOMEM; 1569 return ret; 1570 } 1571 1572 for (n = 0; n < num_clocks; n++) { 1573 drvdata->msynth[n].num = n; 1574 drvdata->msynth[n].drvdata = drvdata; 1575 drvdata->msynth[n].hw.init = &init; 1576 memset(&init, 0, sizeof(init)); 1577 init.name = si5351_msynth_names[n]; 1578 init.ops = &si5351_msynth_ops; 1579 init.flags = 0; 1580 if (pdata->clkout[n].pll_master) 1581 init.flags |= CLK_SET_RATE_PARENT; 1582 init.parent_names = parent_names; 1583 init.num_parents = 2; 1584 ret = devm_clk_hw_register(&client->dev, 1585 &drvdata->msynth[n].hw); 1586 if (ret) { 1587 dev_err(&client->dev, "unable to register %s\n", 1588 init.name); 1589 return ret; 1590 } 1591 } 1592 1593 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3; 1594 parent_names[2] = si5351_input_names[0]; 1595 parent_names[3] = si5351_input_names[1]; 1596 for (n = 0; n < num_clocks; n++) { 1597 parent_names[0] = si5351_msynth_names[n]; 1598 parent_names[1] = (n < 4) ? si5351_msynth_names[0] : 1599 si5351_msynth_names[4]; 1600 1601 drvdata->clkout[n].num = n; 1602 drvdata->clkout[n].drvdata = drvdata; 1603 drvdata->clkout[n].hw.init = &init; 1604 memset(&init, 0, sizeof(init)); 1605 init.name = si5351_clkout_names[n]; 1606 init.ops = &si5351_clkout_ops; 1607 init.flags = 0; 1608 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N) 1609 init.flags |= CLK_SET_RATE_PARENT; 1610 init.parent_names = parent_names; 1611 init.num_parents = num_parents; 1612 ret = devm_clk_hw_register(&client->dev, 1613 &drvdata->clkout[n].hw); 1614 if (ret) { 1615 dev_err(&client->dev, "unable to register %s\n", 1616 init.name); 1617 return ret; 1618 } 1619 1620 /* set initial clkout rate */ 1621 if (pdata->clkout[n].rate != 0) { 1622 int ret; 1623 ret = clk_set_rate(drvdata->clkout[n].hw.clk, 1624 pdata->clkout[n].rate); 1625 if (ret != 0) { 1626 dev_err(&client->dev, "Cannot set rate : %d\n", 1627 ret); 1628 } 1629 } 1630 } 1631 1632 ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get, 1633 drvdata); 1634 if (ret) { 1635 dev_err(&client->dev, "unable to add clk provider\n"); 1636 return ret; 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int si5351_i2c_remove(struct i2c_client *client) 1643 { 1644 of_clk_del_provider(client->dev.of_node); 1645 1646 return 0; 1647 } 1648 1649 static const struct i2c_device_id si5351_i2c_ids[] = { 1650 { "si5351a", SI5351_VARIANT_A }, 1651 { "si5351a-msop", SI5351_VARIANT_A3 }, 1652 { "si5351b", SI5351_VARIANT_B }, 1653 { "si5351c", SI5351_VARIANT_C }, 1654 { } 1655 }; 1656 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); 1657 1658 static struct i2c_driver si5351_driver = { 1659 .driver = { 1660 .name = "si5351", 1661 .of_match_table = of_match_ptr(si5351_dt_ids), 1662 }, 1663 .probe = si5351_i2c_probe, 1664 .remove = si5351_i2c_remove, 1665 .id_table = si5351_i2c_ids, 1666 }; 1667 module_i2c_driver(si5351_driver); 1668 1669 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com"); 1670 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver"); 1671 MODULE_LICENSE("GPL"); 1672