1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345 4 * Copyright (C) 2019 Topic Embedded Products 5 * Author: Mike Looijmans <mike.looijmans@topic.nl> 6 * 7 * The Si5341 has 10 outputs and 5 synthesizers. 8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs. 9 * The Si5345 is similar to the Si5341, with the addition of fractional input 10 * dividers and automatic input selection. 11 * The Si5342 and Si5344 are smaller versions of the Si5345. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/gcd.h> 18 #include <linux/math64.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <asm/unaligned.h> 25 26 #define SI5341_NUM_INPUTS 4 27 28 #define SI5340_MAX_NUM_OUTPUTS 4 29 #define SI5341_MAX_NUM_OUTPUTS 10 30 #define SI5342_MAX_NUM_OUTPUTS 2 31 #define SI5344_MAX_NUM_OUTPUTS 4 32 #define SI5345_MAX_NUM_OUTPUTS 10 33 34 #define SI5340_NUM_SYNTH 4 35 #define SI5341_NUM_SYNTH 5 36 #define SI5342_NUM_SYNTH 2 37 #define SI5344_NUM_SYNTH 4 38 #define SI5345_NUM_SYNTH 5 39 40 /* Range of the synthesizer fractional divider */ 41 #define SI5341_SYNTH_N_MIN 10 42 #define SI5341_SYNTH_N_MAX 4095 43 44 /* The chip can get its input clock from 3 input pins or an XTAL */ 45 46 /* There is one PLL running at 13500–14256 MHz */ 47 #define SI5341_PLL_VCO_MIN 13500000000ull 48 #define SI5341_PLL_VCO_MAX 14256000000ull 49 50 /* The 5 frequency synthesizers obtain their input from the PLL */ 51 struct clk_si5341_synth { 52 struct clk_hw hw; 53 struct clk_si5341 *data; 54 u8 index; 55 }; 56 #define to_clk_si5341_synth(_hw) \ 57 container_of(_hw, struct clk_si5341_synth, hw) 58 59 /* The output stages can be connected to any synth (full mux) */ 60 struct clk_si5341_output { 61 struct clk_hw hw; 62 struct clk_si5341 *data; 63 struct regulator *vddo_reg; 64 u8 index; 65 }; 66 #define to_clk_si5341_output(_hw) \ 67 container_of(_hw, struct clk_si5341_output, hw) 68 69 struct clk_si5341 { 70 struct clk_hw hw; 71 struct regmap *regmap; 72 struct i2c_client *i2c_client; 73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH]; 74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; 75 struct clk *input_clk[SI5341_NUM_INPUTS]; 76 const char *input_clk_name[SI5341_NUM_INPUTS]; 77 const u16 *reg_output_offset; 78 const u16 *reg_rdiv_offset; 79 u64 freq_vco; /* 13500–14256 MHz */ 80 u8 num_outputs; 81 u8 num_synth; 82 u16 chip_id; 83 bool xaxb_ext_clk; 84 bool iovdd_33; 85 }; 86 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) 87 88 struct clk_si5341_output_config { 89 u8 out_format_drv_bits; 90 u8 out_cm_ampl_bits; 91 u8 vdd_sel_bits; 92 bool synth_master; 93 bool always_on; 94 }; 95 96 #define SI5341_PAGE 0x0001 97 #define SI5341_PN_BASE 0x0002 98 #define SI5341_DEVICE_REV 0x0005 99 #define SI5341_STATUS 0x000C 100 #define SI5341_LOS 0x000D 101 #define SI5341_STATUS_STICKY 0x0011 102 #define SI5341_LOS_STICKY 0x0012 103 #define SI5341_SOFT_RST 0x001C 104 #define SI5341_IN_SEL 0x0021 105 #define SI5341_DEVICE_READY 0x00FE 106 #define SI5341_XAXB_CFG 0x090E 107 #define SI5341_IO_VDD_SEL 0x0943 108 #define SI5341_IN_EN 0x0949 109 #define SI5341_INX_TO_PFD_EN 0x094A 110 111 /* Status bits */ 112 #define SI5341_STATUS_SYSINCAL BIT(0) 113 #define SI5341_STATUS_LOSXAXB BIT(1) 114 #define SI5341_STATUS_LOSREF BIT(2) 115 #define SI5341_STATUS_LOL BIT(3) 116 117 /* Input selection */ 118 #define SI5341_IN_SEL_MASK 0x06 119 #define SI5341_IN_SEL_SHIFT 1 120 #define SI5341_IN_SEL_REGCTRL 0x01 121 #define SI5341_INX_TO_PFD_SHIFT 4 122 123 /* XTAL config bits */ 124 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0) 125 #define SI5341_XAXB_CFG_PDNB BIT(1) 126 127 /* Input dividers (48-bit) */ 128 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10)) 129 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10)) 130 #define SI5341_PX_UPD 0x0230 131 132 /* PLL configuration */ 133 #define SI5341_PLL_M_NUM 0x0235 134 #define SI5341_PLL_M_DEN 0x023B 135 136 /* Output configuration */ 137 #define SI5341_OUT_CONFIG(output) \ 138 ((output)->data->reg_output_offset[(output)->index]) 139 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) 140 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) 141 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) 142 #define SI5341_OUT_R_REG(output) \ 143 ((output)->data->reg_rdiv_offset[(output)->index]) 144 145 #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38 146 147 /* Synthesize N divider */ 148 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) 149 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) 150 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11)) 151 152 /* Synthesizer output enable, phase bypass, power mode */ 153 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03 154 #define SI5341_SYNTH_N_PIBYP 0x0A04 155 #define SI5341_SYNTH_N_PDNB 0x0A05 156 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A 157 158 #define SI5341_REGISTER_MAX 0xBFF 159 160 /* SI5341_OUT_CONFIG bits */ 161 #define SI5341_OUT_CFG_PDN BIT(0) 162 #define SI5341_OUT_CFG_OE BIT(1) 163 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) 164 165 /* Static configuration (to be moved to firmware) */ 166 struct si5341_reg_default { 167 u16 address; 168 u8 value; 169 }; 170 171 static const char * const si5341_input_clock_names[] = { 172 "in0", "in1", "in2", "xtal" 173 }; 174 175 /* Output configuration registers 0..9 are not quite logically organized */ 176 /* Also for si5345 */ 177 static const u16 si5341_reg_output_offset[] = { 178 0x0108, 179 0x010D, 180 0x0112, 181 0x0117, 182 0x011C, 183 0x0121, 184 0x0126, 185 0x012B, 186 0x0130, 187 0x013A, 188 }; 189 190 /* for si5340, si5342 and si5344 */ 191 static const u16 si5340_reg_output_offset[] = { 192 0x0112, 193 0x0117, 194 0x0126, 195 0x012B, 196 }; 197 198 /* The location of the R divider registers */ 199 static const u16 si5341_reg_rdiv_offset[] = { 200 0x024A, 201 0x024D, 202 0x0250, 203 0x0253, 204 0x0256, 205 0x0259, 206 0x025C, 207 0x025F, 208 0x0262, 209 0x0268, 210 }; 211 static const u16 si5340_reg_rdiv_offset[] = { 212 0x0250, 213 0x0253, 214 0x025C, 215 0x025F, 216 }; 217 218 /* 219 * Programming sequence from ClockBuilder, settings to initialize the system 220 * using only the XTAL input, without pre-divider. 221 * This also contains settings that aren't mentioned anywhere in the datasheet. 222 * The "known" settings like synth and output configuration are done later. 223 */ 224 static const struct si5341_reg_default si5341_reg_defaults[] = { 225 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */ 226 { 0x0018, 0xFF }, /* INT mask */ 227 { 0x0021, 0x0F }, /* Select XTAL as input */ 228 { 0x0022, 0x00 }, /* Not in datasheet */ 229 { 0x002B, 0x02 }, /* SPI config */ 230 { 0x002C, 0x20 }, /* LOS enable for XTAL */ 231 { 0x002D, 0x00 }, /* LOS timing */ 232 { 0x002E, 0x00 }, 233 { 0x002F, 0x00 }, 234 { 0x0030, 0x00 }, 235 { 0x0031, 0x00 }, 236 { 0x0032, 0x00 }, 237 { 0x0033, 0x00 }, 238 { 0x0034, 0x00 }, 239 { 0x0035, 0x00 }, 240 { 0x0036, 0x00 }, 241 { 0x0037, 0x00 }, 242 { 0x0038, 0x00 }, /* LOS setting (thresholds) */ 243 { 0x0039, 0x00 }, 244 { 0x003A, 0x00 }, 245 { 0x003B, 0x00 }, 246 { 0x003C, 0x00 }, 247 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */ 248 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */ 249 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */ 250 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */ 251 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */ 252 { 0x009E, 0x00 }, /* Not in datasheet */ 253 { 0x0102, 0x01 }, /* Enable outputs */ 254 { 0x013F, 0x00 }, /* Not in datasheet */ 255 { 0x0140, 0x00 }, /* Not in datasheet */ 256 { 0x0141, 0x40 }, /* OUT LOS */ 257 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/ 258 { 0x0203, 0x00 }, 259 { 0x0204, 0x00 }, 260 { 0x0205, 0x00 }, 261 { 0x0206, 0x00 }, /* PXAXB (2^x) */ 262 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */ 263 { 0x0209, 0x00 }, 264 { 0x020A, 0x00 }, 265 { 0x020B, 0x00 }, 266 { 0x020C, 0x00 }, 267 { 0x020D, 0x00 }, 268 { 0x020E, 0x00 }, 269 { 0x020F, 0x00 }, 270 { 0x0210, 0x00 }, 271 { 0x0211, 0x00 }, 272 { 0x0212, 0x00 }, 273 { 0x0213, 0x00 }, 274 { 0x0214, 0x00 }, 275 { 0x0215, 0x00 }, 276 { 0x0216, 0x00 }, 277 { 0x0217, 0x00 }, 278 { 0x0218, 0x00 }, 279 { 0x0219, 0x00 }, 280 { 0x021A, 0x00 }, 281 { 0x021B, 0x00 }, 282 { 0x021C, 0x00 }, 283 { 0x021D, 0x00 }, 284 { 0x021E, 0x00 }, 285 { 0x021F, 0x00 }, 286 { 0x0220, 0x00 }, 287 { 0x0221, 0x00 }, 288 { 0x0222, 0x00 }, 289 { 0x0223, 0x00 }, 290 { 0x0224, 0x00 }, 291 { 0x0225, 0x00 }, 292 { 0x0226, 0x00 }, 293 { 0x0227, 0x00 }, 294 { 0x0228, 0x00 }, 295 { 0x0229, 0x00 }, 296 { 0x022A, 0x00 }, 297 { 0x022B, 0x00 }, 298 { 0x022C, 0x00 }, 299 { 0x022D, 0x00 }, 300 { 0x022E, 0x00 }, 301 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */ 302 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */ 303 { 0x026C, 0x00 }, 304 { 0x026D, 0x00 }, 305 { 0x026E, 0x00 }, 306 { 0x026F, 0x00 }, 307 { 0x0270, 0x00 }, 308 { 0x0271, 0x00 }, 309 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */ 310 { 0x0339, 0x1F }, /* N_FSTEP_MSK */ 311 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */ 312 { 0x033C, 0x00 }, 313 { 0x033D, 0x00 }, 314 { 0x033E, 0x00 }, 315 { 0x033F, 0x00 }, 316 { 0x0340, 0x00 }, 317 { 0x0341, 0x00 }, 318 { 0x0342, 0x00 }, 319 { 0x0343, 0x00 }, 320 { 0x0344, 0x00 }, 321 { 0x0345, 0x00 }, 322 { 0x0346, 0x00 }, 323 { 0x0347, 0x00 }, 324 { 0x0348, 0x00 }, 325 { 0x0349, 0x00 }, 326 { 0x034A, 0x00 }, 327 { 0x034B, 0x00 }, 328 { 0x034C, 0x00 }, 329 { 0x034D, 0x00 }, 330 { 0x034E, 0x00 }, 331 { 0x034F, 0x00 }, 332 { 0x0350, 0x00 }, 333 { 0x0351, 0x00 }, 334 { 0x0352, 0x00 }, 335 { 0x0353, 0x00 }, 336 { 0x0354, 0x00 }, 337 { 0x0355, 0x00 }, 338 { 0x0356, 0x00 }, 339 { 0x0357, 0x00 }, 340 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */ 341 { 0x0359, 0x00 }, /* Nx_DELAY */ 342 { 0x035A, 0x00 }, 343 { 0x035B, 0x00 }, 344 { 0x035C, 0x00 }, 345 { 0x035D, 0x00 }, 346 { 0x035E, 0x00 }, 347 { 0x035F, 0x00 }, 348 { 0x0360, 0x00 }, 349 { 0x0361, 0x00 }, 350 { 0x0362, 0x00 }, /* Nx_DELAY end */ 351 { 0x0802, 0x00 }, /* Not in datasheet */ 352 { 0x0803, 0x00 }, /* Not in datasheet */ 353 { 0x0804, 0x00 }, /* Not in datasheet */ 354 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ 355 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ 356 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ 357 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ 358 { 0x0A02, 0x00 }, /* Not in datasheet */ 359 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ 360 { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */ 361 { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */ 362 }; 363 364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ 365 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, 366 u64 *val1, u32 *val2) 367 { 368 int err; 369 u8 r[10]; 370 371 err = regmap_bulk_read(regmap, reg, r, 10); 372 if (err < 0) 373 return err; 374 375 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) | 376 (get_unaligned_le32(r)); 377 *val2 = get_unaligned_le32(&r[6]); 378 379 return 0; 380 } 381 382 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, 383 u64 n_num, u32 n_den) 384 { 385 u8 r[10]; 386 387 /* Shift left as far as possible without overflowing */ 388 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { 389 n_num <<= 1; 390 n_den <<= 1; 391 } 392 393 /* 44 bits (6 bytes) numerator */ 394 put_unaligned_le32(n_num, r); 395 r[4] = (n_num >> 32) & 0xff; 396 r[5] = (n_num >> 40) & 0x0f; 397 /* 32 bits denominator */ 398 put_unaligned_le32(n_den, &r[6]); 399 400 /* Program the fraction */ 401 return regmap_bulk_write(regmap, reg, r, sizeof(r)); 402 } 403 404 /* VCO, we assume it runs at a constant frequency */ 405 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw, 406 unsigned long parent_rate) 407 { 408 struct clk_si5341 *data = to_clk_si5341(hw); 409 int err; 410 u64 res; 411 u64 m_num; 412 u32 m_den; 413 unsigned int shift; 414 415 /* Assume that PDIV is not being used, just read the PLL setting */ 416 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, 417 &m_num, &m_den); 418 if (err < 0) 419 return 0; 420 421 if (!m_num || !m_den) 422 return 0; 423 424 /* 425 * Though m_num is 64-bit, only the upper bits are actually used. While 426 * calculating m_num and m_den, they are shifted as far as possible to 427 * the left. To avoid 96-bit division here, we just shift them back so 428 * we can do with just 64 bits. 429 */ 430 shift = 0; 431 res = m_num; 432 while (res & 0xffff00000000ULL) { 433 ++shift; 434 res >>= 1; 435 } 436 res *= parent_rate; 437 do_div(res, (m_den >> shift)); 438 439 /* We cannot return the actual frequency in 32 bit, store it locally */ 440 data->freq_vco = res; 441 442 /* Report kHz since the value is out of range */ 443 do_div(res, 1000); 444 445 return (unsigned long)res; 446 } 447 448 static int si5341_clk_get_selected_input(struct clk_si5341 *data) 449 { 450 int err; 451 u32 val; 452 453 err = regmap_read(data->regmap, SI5341_IN_SEL, &val); 454 if (err < 0) 455 return err; 456 457 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT; 458 } 459 460 static u8 si5341_clk_get_parent(struct clk_hw *hw) 461 { 462 struct clk_si5341 *data = to_clk_si5341(hw); 463 int res = si5341_clk_get_selected_input(data); 464 465 if (res < 0) 466 return 0; /* Apparently we cannot report errors */ 467 468 return res; 469 } 470 471 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) 472 { 473 int err; 474 u8 val; 475 476 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK; 477 /* Enable register-based input selection */ 478 val |= SI5341_IN_SEL_REGCTRL; 479 480 err = regmap_update_bits(data->regmap, 481 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val); 482 if (err < 0) 483 return err; 484 485 if (index < 3) { 486 /* Enable input buffer for selected input */ 487 err = regmap_update_bits(data->regmap, 488 SI5341_IN_EN, 0x07, BIT(index)); 489 if (err < 0) 490 return err; 491 492 /* Enables the input to phase detector */ 493 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 494 0x7 << SI5341_INX_TO_PFD_SHIFT, 495 BIT(index + SI5341_INX_TO_PFD_SHIFT)); 496 if (err < 0) 497 return err; 498 499 /* Power down XTAL oscillator and buffer */ 500 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 501 SI5341_XAXB_CFG_PDNB, 0); 502 if (err < 0) 503 return err; 504 505 /* 506 * Set the P divider to "1". There's no explanation in the 507 * datasheet of these registers, but the clockbuilder software 508 * programs a "1" when the input is being used. 509 */ 510 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); 511 if (err < 0) 512 return err; 513 514 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); 515 if (err < 0) 516 return err; 517 518 /* Set update PDIV bit */ 519 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); 520 if (err < 0) 521 return err; 522 } else { 523 /* Disable all input buffers */ 524 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); 525 if (err < 0) 526 return err; 527 528 /* Disable input to phase detector */ 529 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 530 0x7 << SI5341_INX_TO_PFD_SHIFT, 0); 531 if (err < 0) 532 return err; 533 534 /* Power up XTAL oscillator and buffer, select clock mode */ 535 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 536 SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN, 537 SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ? 538 SI5341_XAXB_CFG_EXTCLK_EN : 0)); 539 if (err < 0) 540 return err; 541 } 542 543 return 0; 544 } 545 546 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index) 547 { 548 struct clk_si5341 *data = to_clk_si5341(hw); 549 550 return si5341_clk_reparent(data, index); 551 } 552 553 static const struct clk_ops si5341_clk_ops = { 554 .determine_rate = clk_hw_determine_rate_no_reparent, 555 .set_parent = si5341_clk_set_parent, 556 .get_parent = si5341_clk_get_parent, 557 .recalc_rate = si5341_clk_recalc_rate, 558 }; 559 560 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ 561 562 /* The synthesizer is on if all power and enable bits are set */ 563 static int si5341_synth_clk_is_on(struct clk_hw *hw) 564 { 565 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 566 int err; 567 u32 val; 568 u8 index = synth->index; 569 570 err = regmap_read(synth->data->regmap, 571 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); 572 if (err < 0) 573 return 0; 574 575 if (!(val & BIT(index))) 576 return 0; 577 578 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); 579 if (err < 0) 580 return 0; 581 582 if (!(val & BIT(index))) 583 return 0; 584 585 /* This bit must be 0 for the synthesizer to receive clock input */ 586 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); 587 if (err < 0) 588 return 0; 589 590 return !(val & BIT(index)); 591 } 592 593 static void si5341_synth_clk_unprepare(struct clk_hw *hw) 594 { 595 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 596 u8 index = synth->index; /* In range 0..5 */ 597 u8 mask = BIT(index); 598 599 /* Disable output */ 600 regmap_update_bits(synth->data->regmap, 601 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); 602 /* Power down */ 603 regmap_update_bits(synth->data->regmap, 604 SI5341_SYNTH_N_PDNB, mask, 0); 605 /* Disable clock input to synth (set to 1 to disable) */ 606 regmap_update_bits(synth->data->regmap, 607 SI5341_SYNTH_N_CLK_DIS, mask, mask); 608 } 609 610 static int si5341_synth_clk_prepare(struct clk_hw *hw) 611 { 612 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 613 int err; 614 u8 index = synth->index; 615 u8 mask = BIT(index); 616 617 /* Power up */ 618 err = regmap_update_bits(synth->data->regmap, 619 SI5341_SYNTH_N_PDNB, mask, mask); 620 if (err < 0) 621 return err; 622 623 /* Enable clock input to synth (set bit to 0 to enable) */ 624 err = regmap_update_bits(synth->data->regmap, 625 SI5341_SYNTH_N_CLK_DIS, mask, 0); 626 if (err < 0) 627 return err; 628 629 /* Enable output */ 630 return regmap_update_bits(synth->data->regmap, 631 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); 632 } 633 634 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ 635 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, 636 unsigned long parent_rate) 637 { 638 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 639 u64 f; 640 u64 n_num; 641 u32 n_den; 642 int err; 643 644 err = si5341_decode_44_32(synth->data->regmap, 645 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); 646 if (err < 0) 647 return err; 648 /* Check for bogus/uninitialized settings */ 649 if (!n_num || !n_den) 650 return 0; 651 652 /* 653 * n_num and n_den are shifted left as much as possible, so to prevent 654 * overflow in 64-bit math, we shift n_den 4 bits to the right 655 */ 656 f = synth->data->freq_vco; 657 f *= n_den >> 4; 658 659 /* Now we need to do 64-bit division: f/n_num */ 660 /* And compensate for the 4 bits we dropped */ 661 f = div64_u64(f, (n_num >> 4)); 662 663 return f; 664 } 665 666 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate, 667 unsigned long *parent_rate) 668 { 669 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 670 u64 f; 671 672 /* The synthesizer accuracy is such that anything in range will work */ 673 f = synth->data->freq_vco; 674 do_div(f, SI5341_SYNTH_N_MAX); 675 if (rate < f) 676 return f; 677 678 f = synth->data->freq_vco; 679 do_div(f, SI5341_SYNTH_N_MIN); 680 if (rate > f) 681 return f; 682 683 return rate; 684 } 685 686 static int si5341_synth_program(struct clk_si5341_synth *synth, 687 u64 n_num, u32 n_den, bool is_integer) 688 { 689 int err; 690 u8 index = synth->index; 691 692 err = si5341_encode_44_32(synth->data->regmap, 693 SI5341_SYNTH_N_NUM(index), n_num, n_den); 694 695 err = regmap_update_bits(synth->data->regmap, 696 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); 697 if (err < 0) 698 return err; 699 700 return regmap_write(synth->data->regmap, 701 SI5341_SYNTH_N_UPD(index), 0x01); 702 } 703 704 705 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate, 706 unsigned long parent_rate) 707 { 708 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 709 u64 n_num; 710 u32 n_den; 711 u32 r; 712 u32 g; 713 bool is_integer; 714 715 n_num = synth->data->freq_vco; 716 717 /* see if there's an integer solution */ 718 r = do_div(n_num, rate); 719 is_integer = (r == 0); 720 if (is_integer) { 721 /* Integer divider equal to n_num */ 722 n_den = 1; 723 } else { 724 /* Calculate a fractional solution */ 725 g = gcd(r, rate); 726 n_den = rate / g; 727 n_num *= n_den; 728 n_num += r / g; 729 } 730 731 dev_dbg(&synth->data->i2c_client->dev, 732 "%s(%u): n=0x%llx d=0x%x %s\n", __func__, 733 synth->index, n_num, n_den, 734 is_integer ? "int" : "frac"); 735 736 return si5341_synth_program(synth, n_num, n_den, is_integer); 737 } 738 739 static const struct clk_ops si5341_synth_clk_ops = { 740 .is_prepared = si5341_synth_clk_is_on, 741 .prepare = si5341_synth_clk_prepare, 742 .unprepare = si5341_synth_clk_unprepare, 743 .recalc_rate = si5341_synth_clk_recalc_rate, 744 .round_rate = si5341_synth_clk_round_rate, 745 .set_rate = si5341_synth_clk_set_rate, 746 }; 747 748 static int si5341_output_clk_is_on(struct clk_hw *hw) 749 { 750 struct clk_si5341_output *output = to_clk_si5341_output(hw); 751 int err; 752 u32 val; 753 754 err = regmap_read(output->data->regmap, 755 SI5341_OUT_CONFIG(output), &val); 756 if (err < 0) 757 return err; 758 759 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ 760 return (val & 0x03) == SI5341_OUT_CFG_OE; 761 } 762 763 /* Disables and then powers down the output */ 764 static void si5341_output_clk_unprepare(struct clk_hw *hw) 765 { 766 struct clk_si5341_output *output = to_clk_si5341_output(hw); 767 768 regmap_update_bits(output->data->regmap, 769 SI5341_OUT_CONFIG(output), 770 SI5341_OUT_CFG_OE, 0); 771 regmap_update_bits(output->data->regmap, 772 SI5341_OUT_CONFIG(output), 773 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN); 774 } 775 776 /* Powers up and then enables the output */ 777 static int si5341_output_clk_prepare(struct clk_hw *hw) 778 { 779 struct clk_si5341_output *output = to_clk_si5341_output(hw); 780 int err; 781 782 err = regmap_update_bits(output->data->regmap, 783 SI5341_OUT_CONFIG(output), 784 SI5341_OUT_CFG_PDN, 0); 785 if (err < 0) 786 return err; 787 788 return regmap_update_bits(output->data->regmap, 789 SI5341_OUT_CONFIG(output), 790 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE); 791 } 792 793 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, 794 unsigned long parent_rate) 795 { 796 struct clk_si5341_output *output = to_clk_si5341_output(hw); 797 int err; 798 u32 val; 799 u32 r_divider; 800 u8 r[3]; 801 802 err = regmap_read(output->data->regmap, 803 SI5341_OUT_CONFIG(output), &val); 804 if (err < 0) 805 return err; 806 807 /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */ 808 if (val & SI5341_OUT_CFG_RDIV_FORCE2) 809 return parent_rate / 2; 810 811 err = regmap_bulk_read(output->data->regmap, 812 SI5341_OUT_R_REG(output), r, 3); 813 if (err < 0) 814 return err; 815 816 /* Calculate value as 24-bit integer*/ 817 r_divider = r[2] << 16 | r[1] << 8 | r[0]; 818 819 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ 820 if (!r_divider) 821 return 0; 822 823 /* Divider is 2*(Rx_REG+1) */ 824 r_divider += 1; 825 r_divider <<= 1; 826 827 828 return parent_rate / r_divider; 829 } 830 831 static int si5341_output_clk_determine_rate(struct clk_hw *hw, 832 struct clk_rate_request *req) 833 { 834 unsigned long rate = req->rate; 835 unsigned long r; 836 837 if (!rate) 838 return 0; 839 840 r = req->best_parent_rate >> 1; 841 842 /* If rate is an even divisor, no changes to parent required */ 843 if (r && !(r % rate)) 844 return 0; 845 846 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 847 if (rate > 200000000) { 848 /* minimum r-divider is 2 */ 849 r = 2; 850 } else { 851 /* Take a parent frequency near 400 MHz */ 852 r = (400000000u / rate) & ~1; 853 } 854 req->best_parent_rate = r * rate; 855 } else { 856 /* We cannot change our parent's rate, report what we can do */ 857 r /= rate; 858 rate = req->best_parent_rate / (r << 1); 859 } 860 861 req->rate = rate; 862 return 0; 863 } 864 865 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, 866 unsigned long parent_rate) 867 { 868 struct clk_si5341_output *output = to_clk_si5341_output(hw); 869 u32 r_div; 870 int err; 871 u8 r[3]; 872 873 if (!rate) 874 return -EINVAL; 875 876 /* Frequency divider is (r_div + 1) * 2 */ 877 r_div = (parent_rate / rate) >> 1; 878 879 if (r_div <= 1) 880 r_div = 0; 881 else if (r_div >= BIT(24)) 882 r_div = BIT(24) - 1; 883 else 884 --r_div; 885 886 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ 887 err = regmap_update_bits(output->data->regmap, 888 SI5341_OUT_CONFIG(output), 889 SI5341_OUT_CFG_RDIV_FORCE2, 890 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0); 891 if (err < 0) 892 return err; 893 894 /* Always write Rx_REG, because a zero value disables the divider */ 895 r[0] = r_div ? (r_div & 0xff) : 1; 896 r[1] = (r_div >> 8) & 0xff; 897 r[2] = (r_div >> 16) & 0xff; 898 err = regmap_bulk_write(output->data->regmap, 899 SI5341_OUT_R_REG(output), r, 3); 900 901 return 0; 902 } 903 904 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) 905 { 906 return regmap_update_bits(output->data->regmap, 907 SI5341_OUT_MUX_SEL(output), 0x07, index); 908 } 909 910 static int si5341_output_set_parent(struct clk_hw *hw, u8 index) 911 { 912 struct clk_si5341_output *output = to_clk_si5341_output(hw); 913 914 if (index >= output->data->num_synth) 915 return -EINVAL; 916 917 return si5341_output_reparent(output, index); 918 } 919 920 static u8 si5341_output_get_parent(struct clk_hw *hw) 921 { 922 struct clk_si5341_output *output = to_clk_si5341_output(hw); 923 u32 val; 924 925 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val); 926 927 return val & 0x7; 928 } 929 930 static const struct clk_ops si5341_output_clk_ops = { 931 .is_prepared = si5341_output_clk_is_on, 932 .prepare = si5341_output_clk_prepare, 933 .unprepare = si5341_output_clk_unprepare, 934 .recalc_rate = si5341_output_clk_recalc_rate, 935 .determine_rate = si5341_output_clk_determine_rate, 936 .set_rate = si5341_output_clk_set_rate, 937 .set_parent = si5341_output_set_parent, 938 .get_parent = si5341_output_get_parent, 939 }; 940 941 /* 942 * The chip can be bought in a pre-programmed version, or one can program the 943 * NVM in the chip to boot up in a preset mode. This routine tries to determine 944 * if that's the case, or if we need to reset and program everything from 945 * scratch. Returns negative error, or true/false. 946 */ 947 static int si5341_is_programmed_already(struct clk_si5341 *data) 948 { 949 int err; 950 u8 r[4]; 951 952 /* Read the PLL divider value, it must have a non-zero value */ 953 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, 954 r, ARRAY_SIZE(r)); 955 if (err < 0) 956 return err; 957 958 return !!get_unaligned_le32(r); 959 } 960 961 static struct clk_hw * 962 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data) 963 { 964 struct clk_si5341 *data = _data; 965 unsigned int idx = clkspec->args[1]; 966 unsigned int group = clkspec->args[0]; 967 968 switch (group) { 969 case 0: 970 if (idx >= data->num_outputs) { 971 dev_err(&data->i2c_client->dev, 972 "invalid output index %u\n", idx); 973 return ERR_PTR(-EINVAL); 974 } 975 return &data->clk[idx].hw; 976 case 1: 977 if (idx >= data->num_synth) { 978 dev_err(&data->i2c_client->dev, 979 "invalid synthesizer index %u\n", idx); 980 return ERR_PTR(-EINVAL); 981 } 982 return &data->synth[idx].hw; 983 case 2: 984 if (idx > 0) { 985 dev_err(&data->i2c_client->dev, 986 "invalid PLL index %u\n", idx); 987 return ERR_PTR(-EINVAL); 988 } 989 return &data->hw; 990 default: 991 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); 992 return ERR_PTR(-EINVAL); 993 } 994 } 995 996 static int si5341_probe_chip_id(struct clk_si5341 *data) 997 { 998 int err; 999 u8 reg[4]; 1000 u16 model; 1001 1002 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, 1003 ARRAY_SIZE(reg)); 1004 if (err < 0) { 1005 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); 1006 return err; 1007 } 1008 1009 model = get_unaligned_le16(reg); 1010 1011 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", 1012 model, reg[2], reg[3]); 1013 1014 switch (model) { 1015 case 0x5340: 1016 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; 1017 data->num_synth = SI5340_NUM_SYNTH; 1018 data->reg_output_offset = si5340_reg_output_offset; 1019 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 1020 break; 1021 case 0x5341: 1022 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; 1023 data->num_synth = SI5341_NUM_SYNTH; 1024 data->reg_output_offset = si5341_reg_output_offset; 1025 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 1026 break; 1027 case 0x5342: 1028 data->num_outputs = SI5342_MAX_NUM_OUTPUTS; 1029 data->num_synth = SI5342_NUM_SYNTH; 1030 data->reg_output_offset = si5340_reg_output_offset; 1031 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 1032 break; 1033 case 0x5344: 1034 data->num_outputs = SI5344_MAX_NUM_OUTPUTS; 1035 data->num_synth = SI5344_NUM_SYNTH; 1036 data->reg_output_offset = si5340_reg_output_offset; 1037 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 1038 break; 1039 case 0x5345: 1040 data->num_outputs = SI5345_MAX_NUM_OUTPUTS; 1041 data->num_synth = SI5345_NUM_SYNTH; 1042 data->reg_output_offset = si5341_reg_output_offset; 1043 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 1044 break; 1045 default: 1046 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", 1047 model); 1048 return -EINVAL; 1049 } 1050 1051 data->chip_id = model; 1052 1053 return 0; 1054 } 1055 1056 /* Read active settings into the regmap cache for later reference */ 1057 static int si5341_read_settings(struct clk_si5341 *data) 1058 { 1059 int err; 1060 u8 i; 1061 u8 r[10]; 1062 1063 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); 1064 if (err < 0) 1065 return err; 1066 1067 err = regmap_bulk_read(data->regmap, 1068 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3); 1069 if (err < 0) 1070 return err; 1071 1072 err = regmap_bulk_read(data->regmap, 1073 SI5341_SYNTH_N_CLK_DIS, r, 1); 1074 if (err < 0) 1075 return err; 1076 1077 for (i = 0; i < data->num_synth; ++i) { 1078 err = regmap_bulk_read(data->regmap, 1079 SI5341_SYNTH_N_NUM(i), r, 10); 1080 if (err < 0) 1081 return err; 1082 } 1083 1084 for (i = 0; i < data->num_outputs; ++i) { 1085 err = regmap_bulk_read(data->regmap, 1086 data->reg_output_offset[i], r, 4); 1087 if (err < 0) 1088 return err; 1089 1090 err = regmap_bulk_read(data->regmap, 1091 data->reg_rdiv_offset[i], r, 3); 1092 if (err < 0) 1093 return err; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int si5341_write_multiple(struct clk_si5341 *data, 1100 const struct si5341_reg_default *values, unsigned int num_values) 1101 { 1102 unsigned int i; 1103 int res; 1104 1105 for (i = 0; i < num_values; ++i) { 1106 res = regmap_write(data->regmap, 1107 values[i].address, values[i].value); 1108 if (res < 0) { 1109 dev_err(&data->i2c_client->dev, 1110 "Failed to write %#x:%#x\n", 1111 values[i].address, values[i].value); 1112 return res; 1113 } 1114 } 1115 1116 return 0; 1117 } 1118 1119 static const struct si5341_reg_default si5341_preamble[] = { 1120 { 0x0B25, 0x00 }, 1121 { 0x0502, 0x01 }, 1122 { 0x0505, 0x03 }, 1123 { 0x0957, 0x17 }, 1124 { 0x0B4E, 0x1A }, 1125 }; 1126 1127 static const struct si5341_reg_default si5345_preamble[] = { 1128 { 0x0B25, 0x00 }, 1129 { 0x0540, 0x01 }, 1130 }; 1131 1132 static int si5341_send_preamble(struct clk_si5341 *data) 1133 { 1134 int res; 1135 u32 revision; 1136 1137 /* For revision 2 and up, the values are slightly different */ 1138 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1139 if (res < 0) 1140 return res; 1141 1142 /* Write "preamble" as specified by datasheet */ 1143 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); 1144 if (res < 0) 1145 return res; 1146 1147 /* The si5342..si5345 require a different preamble */ 1148 if (data->chip_id > 0x5341) 1149 res = si5341_write_multiple(data, 1150 si5345_preamble, ARRAY_SIZE(si5345_preamble)); 1151 else 1152 res = si5341_write_multiple(data, 1153 si5341_preamble, ARRAY_SIZE(si5341_preamble)); 1154 if (res < 0) 1155 return res; 1156 1157 /* Datasheet specifies a 300ms wait after sending the preamble */ 1158 msleep(300); 1159 1160 return 0; 1161 } 1162 1163 /* Perform a soft reset and write post-amble */ 1164 static int si5341_finalize_defaults(struct clk_si5341 *data) 1165 { 1166 int res; 1167 u32 revision; 1168 1169 res = regmap_write(data->regmap, SI5341_IO_VDD_SEL, 1170 data->iovdd_33 ? 1 : 0); 1171 if (res < 0) 1172 return res; 1173 1174 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1175 if (res < 0) 1176 return res; 1177 1178 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); 1179 1180 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); 1181 if (res < 0) 1182 return res; 1183 1184 /* The si5342..si5345 have an additional post-amble */ 1185 if (data->chip_id > 0x5341) { 1186 res = regmap_write(data->regmap, 0x540, 0x0); 1187 if (res < 0) 1188 return res; 1189 } 1190 1191 /* Datasheet does not explain these nameless registers */ 1192 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); 1193 if (res < 0) 1194 return res; 1195 res = regmap_write(data->regmap, 0x0B25, 0x02); 1196 if (res < 0) 1197 return res; 1198 1199 return 0; 1200 } 1201 1202 1203 static const struct regmap_range si5341_regmap_volatile_range[] = { 1204 regmap_reg_range(0x000C, 0x0012), /* Status */ 1205 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */ 1206 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */ 1207 /* Update bits for P divider and synth config */ 1208 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD), 1209 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)), 1210 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)), 1211 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)), 1212 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)), 1213 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)), 1214 }; 1215 1216 static const struct regmap_access_table si5341_regmap_volatile = { 1217 .yes_ranges = si5341_regmap_volatile_range, 1218 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range), 1219 }; 1220 1221 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ 1222 static const struct regmap_range_cfg si5341_regmap_ranges[] = { 1223 { 1224 .range_min = 0, 1225 .range_max = SI5341_REGISTER_MAX, 1226 .selector_reg = SI5341_PAGE, 1227 .selector_mask = 0xff, 1228 .selector_shift = 0, 1229 .window_start = 0, 1230 .window_len = 256, 1231 }, 1232 }; 1233 1234 static int si5341_wait_device_ready(struct i2c_client *client) 1235 { 1236 int count; 1237 1238 /* Datasheet warns: Any attempt to read or write any register other 1239 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the 1240 * NVM programming and may corrupt the register contents, as they are 1241 * read from NVM. Note that this includes accesses to the PAGE register. 1242 * Also: DEVICE_READY is available on every register page, so no page 1243 * change is needed to read it. 1244 * Do this outside regmap to avoid automatic PAGE register access. 1245 * May take up to 300ms to complete. 1246 */ 1247 for (count = 0; count < 15; ++count) { 1248 s32 result = i2c_smbus_read_byte_data(client, 1249 SI5341_DEVICE_READY); 1250 if (result < 0) 1251 return result; 1252 if (result == 0x0F) 1253 return 0; 1254 msleep(20); 1255 } 1256 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); 1257 return -EIO; 1258 } 1259 1260 static const struct regmap_config si5341_regmap_config = { 1261 .reg_bits = 8, 1262 .val_bits = 8, 1263 .cache_type = REGCACHE_RBTREE, 1264 .ranges = si5341_regmap_ranges, 1265 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges), 1266 .max_register = SI5341_REGISTER_MAX, 1267 .volatile_table = &si5341_regmap_volatile, 1268 }; 1269 1270 static int si5341_dt_parse_dt(struct clk_si5341 *data, 1271 struct clk_si5341_output_config *config) 1272 { 1273 struct device_node *child; 1274 struct device_node *np = data->i2c_client->dev.of_node; 1275 u32 num; 1276 u32 val; 1277 1278 memset(config, 0, sizeof(struct clk_si5341_output_config) * 1279 SI5341_MAX_NUM_OUTPUTS); 1280 1281 for_each_child_of_node(np, child) { 1282 if (of_property_read_u32(child, "reg", &num)) { 1283 dev_err(&data->i2c_client->dev, "missing reg property of %s\n", 1284 child->name); 1285 goto put_child; 1286 } 1287 1288 if (num >= SI5341_MAX_NUM_OUTPUTS) { 1289 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num); 1290 goto put_child; 1291 } 1292 1293 if (!of_property_read_u32(child, "silabs,format", &val)) { 1294 /* Set cm and ampl conservatively to 3v3 settings */ 1295 switch (val) { 1296 case 1: /* normal differential */ 1297 config[num].out_cm_ampl_bits = 0x33; 1298 break; 1299 case 2: /* low-power differential */ 1300 config[num].out_cm_ampl_bits = 0x13; 1301 break; 1302 case 4: /* LVCMOS */ 1303 config[num].out_cm_ampl_bits = 0x33; 1304 /* Set SI recommended impedance for LVCMOS */ 1305 config[num].out_format_drv_bits |= 0xc0; 1306 break; 1307 default: 1308 dev_err(&data->i2c_client->dev, 1309 "invalid silabs,format %u for %u\n", 1310 val, num); 1311 goto put_child; 1312 } 1313 config[num].out_format_drv_bits &= ~0x07; 1314 config[num].out_format_drv_bits |= val & 0x07; 1315 /* Always enable the SYNC feature */ 1316 config[num].out_format_drv_bits |= 0x08; 1317 } 1318 1319 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { 1320 if (val > 0xf) { 1321 dev_err(&data->i2c_client->dev, 1322 "invalid silabs,common-mode %u\n", 1323 val); 1324 goto put_child; 1325 } 1326 config[num].out_cm_ampl_bits &= 0xf0; 1327 config[num].out_cm_ampl_bits |= val & 0x0f; 1328 } 1329 1330 if (!of_property_read_u32(child, "silabs,amplitude", &val)) { 1331 if (val > 0xf) { 1332 dev_err(&data->i2c_client->dev, 1333 "invalid silabs,amplitude %u\n", 1334 val); 1335 goto put_child; 1336 } 1337 config[num].out_cm_ampl_bits &= 0x0f; 1338 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; 1339 } 1340 1341 if (of_property_read_bool(child, "silabs,disable-high")) 1342 config[num].out_format_drv_bits |= 0x10; 1343 1344 config[num].synth_master = 1345 of_property_read_bool(child, "silabs,synth-master"); 1346 1347 config[num].always_on = 1348 of_property_read_bool(child, "always-on"); 1349 1350 config[num].vdd_sel_bits = 0x08; 1351 if (data->clk[num].vddo_reg) { 1352 int vdd = regulator_get_voltage(data->clk[num].vddo_reg); 1353 1354 switch (vdd) { 1355 case 3300000: 1356 config[num].vdd_sel_bits |= 0 << 4; 1357 break; 1358 case 1800000: 1359 config[num].vdd_sel_bits |= 1 << 4; 1360 break; 1361 case 2500000: 1362 config[num].vdd_sel_bits |= 2 << 4; 1363 break; 1364 default: 1365 dev_err(&data->i2c_client->dev, 1366 "unsupported vddo voltage %d for %s\n", 1367 vdd, child->name); 1368 goto put_child; 1369 } 1370 } else { 1371 /* chip seems to default to 2.5V when not set */ 1372 dev_warn(&data->i2c_client->dev, 1373 "no regulator set, defaulting vdd_sel to 2.5V for %s\n", 1374 child->name); 1375 config[num].vdd_sel_bits |= 2 << 4; 1376 } 1377 } 1378 1379 return 0; 1380 1381 put_child: 1382 of_node_put(child); 1383 return -EINVAL; 1384 } 1385 1386 /* 1387 * If not pre-configured, calculate and set the PLL configuration manually. 1388 * For low-jitter performance, the PLL should be set such that the synthesizers 1389 * only need integer division. 1390 * Without any user guidance, we'll set the PLL to 14GHz, which still allows 1391 * the chip to generate any frequency on its outputs, but jitter performance 1392 * may be sub-optimal. 1393 */ 1394 static int si5341_initialize_pll(struct clk_si5341 *data) 1395 { 1396 struct device_node *np = data->i2c_client->dev.of_node; 1397 u32 m_num = 0; 1398 u32 m_den = 0; 1399 int sel; 1400 1401 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { 1402 dev_err(&data->i2c_client->dev, 1403 "PLL configuration requires silabs,pll-m-num\n"); 1404 } 1405 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { 1406 dev_err(&data->i2c_client->dev, 1407 "PLL configuration requires silabs,pll-m-den\n"); 1408 } 1409 1410 if (!m_num || !m_den) { 1411 dev_err(&data->i2c_client->dev, 1412 "PLL configuration invalid, assume 14GHz\n"); 1413 sel = si5341_clk_get_selected_input(data); 1414 if (sel < 0) 1415 return sel; 1416 1417 m_den = clk_get_rate(data->input_clk[sel]) / 10; 1418 m_num = 1400000000; 1419 } 1420 1421 return si5341_encode_44_32(data->regmap, 1422 SI5341_PLL_M_NUM, m_num, m_den); 1423 } 1424 1425 static int si5341_clk_select_active_input(struct clk_si5341 *data) 1426 { 1427 int res; 1428 int err; 1429 int i; 1430 1431 res = si5341_clk_get_selected_input(data); 1432 if (res < 0) 1433 return res; 1434 1435 /* If the current register setting is invalid, pick the first input */ 1436 if (!data->input_clk[res]) { 1437 dev_dbg(&data->i2c_client->dev, 1438 "Input %d not connected, rerouting\n", res); 1439 res = -ENODEV; 1440 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1441 if (data->input_clk[i]) { 1442 res = i; 1443 break; 1444 } 1445 } 1446 if (res < 0) { 1447 dev_err(&data->i2c_client->dev, 1448 "No clock input available\n"); 1449 return res; 1450 } 1451 } 1452 1453 /* Make sure the selected clock is also enabled and routed */ 1454 err = si5341_clk_reparent(data, res); 1455 if (err < 0) 1456 return err; 1457 1458 err = clk_prepare_enable(data->input_clk[res]); 1459 if (err < 0) 1460 return err; 1461 1462 return res; 1463 } 1464 1465 static ssize_t input_present_show(struct device *dev, 1466 struct device_attribute *attr, 1467 char *buf) 1468 { 1469 struct clk_si5341 *data = dev_get_drvdata(dev); 1470 u32 status; 1471 int res = regmap_read(data->regmap, SI5341_STATUS, &status); 1472 1473 if (res < 0) 1474 return res; 1475 res = !(status & SI5341_STATUS_LOSREF); 1476 return sysfs_emit(buf, "%d\n", res); 1477 } 1478 static DEVICE_ATTR_RO(input_present); 1479 1480 static ssize_t input_present_sticky_show(struct device *dev, 1481 struct device_attribute *attr, 1482 char *buf) 1483 { 1484 struct clk_si5341 *data = dev_get_drvdata(dev); 1485 u32 status; 1486 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); 1487 1488 if (res < 0) 1489 return res; 1490 res = !(status & SI5341_STATUS_LOSREF); 1491 return sysfs_emit(buf, "%d\n", res); 1492 } 1493 static DEVICE_ATTR_RO(input_present_sticky); 1494 1495 static ssize_t pll_locked_show(struct device *dev, 1496 struct device_attribute *attr, 1497 char *buf) 1498 { 1499 struct clk_si5341 *data = dev_get_drvdata(dev); 1500 u32 status; 1501 int res = regmap_read(data->regmap, SI5341_STATUS, &status); 1502 1503 if (res < 0) 1504 return res; 1505 res = !(status & SI5341_STATUS_LOL); 1506 return sysfs_emit(buf, "%d\n", res); 1507 } 1508 static DEVICE_ATTR_RO(pll_locked); 1509 1510 static ssize_t pll_locked_sticky_show(struct device *dev, 1511 struct device_attribute *attr, 1512 char *buf) 1513 { 1514 struct clk_si5341 *data = dev_get_drvdata(dev); 1515 u32 status; 1516 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); 1517 1518 if (res < 0) 1519 return res; 1520 res = !(status & SI5341_STATUS_LOL); 1521 return sysfs_emit(buf, "%d\n", res); 1522 } 1523 static DEVICE_ATTR_RO(pll_locked_sticky); 1524 1525 static ssize_t clear_sticky_store(struct device *dev, 1526 struct device_attribute *attr, 1527 const char *buf, size_t count) 1528 { 1529 struct clk_si5341 *data = dev_get_drvdata(dev); 1530 long val; 1531 1532 if (kstrtol(buf, 10, &val)) 1533 return -EINVAL; 1534 if (val) { 1535 int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); 1536 1537 if (res < 0) 1538 return res; 1539 } 1540 return count; 1541 } 1542 static DEVICE_ATTR_WO(clear_sticky); 1543 1544 static const struct attribute *si5341_attributes[] = { 1545 &dev_attr_input_present.attr, 1546 &dev_attr_input_present_sticky.attr, 1547 &dev_attr_pll_locked.attr, 1548 &dev_attr_pll_locked_sticky.attr, 1549 &dev_attr_clear_sticky.attr, 1550 NULL 1551 }; 1552 1553 static int si5341_probe(struct i2c_client *client) 1554 { 1555 struct clk_si5341 *data; 1556 struct clk_init_data init; 1557 struct clk *input; 1558 const char *root_clock_name; 1559 const char *synth_clock_names[SI5341_NUM_SYNTH]; 1560 int err; 1561 unsigned int i; 1562 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; 1563 bool initialization_required; 1564 u32 status; 1565 1566 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 1567 if (!data) 1568 return -ENOMEM; 1569 1570 data->i2c_client = client; 1571 1572 /* Must be done before otherwise touching hardware */ 1573 err = si5341_wait_device_ready(client); 1574 if (err) 1575 return err; 1576 1577 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1578 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); 1579 if (IS_ERR(input)) { 1580 if (PTR_ERR(input) == -EPROBE_DEFER) 1581 return -EPROBE_DEFER; 1582 data->input_clk_name[i] = si5341_input_clock_names[i]; 1583 } else { 1584 data->input_clk[i] = input; 1585 data->input_clk_name[i] = __clk_get_name(input); 1586 } 1587 } 1588 1589 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { 1590 char reg_name[10]; 1591 1592 snprintf(reg_name, sizeof(reg_name), "vddo%d", i); 1593 data->clk[i].vddo_reg = devm_regulator_get_optional( 1594 &client->dev, reg_name); 1595 if (IS_ERR(data->clk[i].vddo_reg)) { 1596 err = PTR_ERR(data->clk[i].vddo_reg); 1597 data->clk[i].vddo_reg = NULL; 1598 if (err == -ENODEV) 1599 continue; 1600 goto cleanup; 1601 } else { 1602 err = regulator_enable(data->clk[i].vddo_reg); 1603 if (err) { 1604 dev_err(&client->dev, 1605 "failed to enable %s regulator: %d\n", 1606 reg_name, err); 1607 data->clk[i].vddo_reg = NULL; 1608 goto cleanup; 1609 } 1610 } 1611 } 1612 1613 err = si5341_dt_parse_dt(data, config); 1614 if (err) 1615 goto cleanup; 1616 1617 if (of_property_read_string(client->dev.of_node, "clock-output-names", 1618 &init.name)) 1619 init.name = client->dev.of_node->name; 1620 root_clock_name = init.name; 1621 1622 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); 1623 if (IS_ERR(data->regmap)) { 1624 err = PTR_ERR(data->regmap); 1625 goto cleanup; 1626 } 1627 1628 i2c_set_clientdata(client, data); 1629 1630 err = si5341_probe_chip_id(data); 1631 if (err < 0) 1632 goto cleanup; 1633 1634 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { 1635 initialization_required = true; 1636 } else { 1637 err = si5341_is_programmed_already(data); 1638 if (err < 0) 1639 goto cleanup; 1640 1641 initialization_required = !err; 1642 } 1643 data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node, 1644 "silabs,xaxb-ext-clk"); 1645 data->iovdd_33 = of_property_read_bool(client->dev.of_node, 1646 "silabs,iovdd-33"); 1647 1648 if (initialization_required) { 1649 /* Populate the regmap cache in preparation for "cache only" */ 1650 err = si5341_read_settings(data); 1651 if (err < 0) 1652 goto cleanup; 1653 1654 err = si5341_send_preamble(data); 1655 if (err < 0) 1656 goto cleanup; 1657 1658 /* 1659 * We intend to send all 'final' register values in a single 1660 * transaction. So cache all register writes until we're done 1661 * configuring. 1662 */ 1663 regcache_cache_only(data->regmap, true); 1664 1665 /* Write the configuration pairs from the firmware blob */ 1666 err = si5341_write_multiple(data, si5341_reg_defaults, 1667 ARRAY_SIZE(si5341_reg_defaults)); 1668 if (err < 0) 1669 goto cleanup; 1670 } 1671 1672 /* Input must be up and running at this point */ 1673 err = si5341_clk_select_active_input(data); 1674 if (err < 0) 1675 goto cleanup; 1676 1677 if (initialization_required) { 1678 /* PLL configuration is required */ 1679 err = si5341_initialize_pll(data); 1680 if (err < 0) 1681 goto cleanup; 1682 } 1683 1684 /* Register the PLL */ 1685 init.parent_names = data->input_clk_name; 1686 init.num_parents = SI5341_NUM_INPUTS; 1687 init.ops = &si5341_clk_ops; 1688 init.flags = 0; 1689 data->hw.init = &init; 1690 1691 err = devm_clk_hw_register(&client->dev, &data->hw); 1692 if (err) { 1693 dev_err(&client->dev, "clock registration failed\n"); 1694 goto cleanup; 1695 } 1696 1697 init.num_parents = 1; 1698 init.parent_names = &root_clock_name; 1699 init.ops = &si5341_synth_clk_ops; 1700 for (i = 0; i < data->num_synth; ++i) { 1701 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, 1702 "%s.N%u", client->dev.of_node->name, i); 1703 init.name = synth_clock_names[i]; 1704 data->synth[i].index = i; 1705 data->synth[i].data = data; 1706 data->synth[i].hw.init = &init; 1707 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); 1708 if (err) { 1709 dev_err(&client->dev, 1710 "synth N%u registration failed\n", i); 1711 } 1712 } 1713 1714 init.num_parents = data->num_synth; 1715 init.parent_names = synth_clock_names; 1716 init.ops = &si5341_output_clk_ops; 1717 for (i = 0; i < data->num_outputs; ++i) { 1718 init.name = kasprintf(GFP_KERNEL, "%s.%d", 1719 client->dev.of_node->name, i); 1720 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0; 1721 data->clk[i].index = i; 1722 data->clk[i].data = data; 1723 data->clk[i].hw.init = &init; 1724 if (config[i].out_format_drv_bits & 0x07) { 1725 regmap_write(data->regmap, 1726 SI5341_OUT_FORMAT(&data->clk[i]), 1727 config[i].out_format_drv_bits); 1728 regmap_write(data->regmap, 1729 SI5341_OUT_CM(&data->clk[i]), 1730 config[i].out_cm_ampl_bits); 1731 regmap_update_bits(data->regmap, 1732 SI5341_OUT_MUX_SEL(&data->clk[i]), 1733 SI5341_OUT_MUX_VDD_SEL_MASK, 1734 config[i].vdd_sel_bits); 1735 } 1736 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 1737 kfree(init.name); /* clock framework made a copy of the name */ 1738 if (err) { 1739 dev_err(&client->dev, 1740 "output %u registration failed\n", i); 1741 goto cleanup; 1742 } 1743 if (config[i].always_on) 1744 clk_prepare(data->clk[i].hw.clk); 1745 } 1746 1747 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get, 1748 data); 1749 if (err) { 1750 dev_err(&client->dev, "unable to add clk provider\n"); 1751 goto cleanup; 1752 } 1753 1754 if (initialization_required) { 1755 /* Synchronize */ 1756 regcache_cache_only(data->regmap, false); 1757 err = regcache_sync(data->regmap); 1758 if (err < 0) 1759 goto cleanup; 1760 1761 err = si5341_finalize_defaults(data); 1762 if (err < 0) 1763 goto cleanup; 1764 } 1765 1766 /* wait for device to report input clock present and PLL lock */ 1767 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status, 1768 !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)), 1769 10000, 250000); 1770 if (err) { 1771 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n"); 1772 goto cleanup; 1773 } 1774 1775 /* clear sticky alarm bits from initialization */ 1776 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); 1777 if (err) { 1778 dev_err(&client->dev, "unable to clear sticky status\n"); 1779 goto cleanup; 1780 } 1781 1782 err = sysfs_create_files(&client->dev.kobj, si5341_attributes); 1783 if (err) { 1784 dev_err(&client->dev, "unable to create sysfs files\n"); 1785 goto cleanup; 1786 } 1787 1788 /* Free the names, clk framework makes copies */ 1789 for (i = 0; i < data->num_synth; ++i) 1790 devm_kfree(&client->dev, (void *)synth_clock_names[i]); 1791 1792 return 0; 1793 1794 cleanup: 1795 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { 1796 if (data->clk[i].vddo_reg) 1797 regulator_disable(data->clk[i].vddo_reg); 1798 } 1799 return err; 1800 } 1801 1802 static void si5341_remove(struct i2c_client *client) 1803 { 1804 struct clk_si5341 *data = i2c_get_clientdata(client); 1805 int i; 1806 1807 sysfs_remove_files(&client->dev.kobj, si5341_attributes); 1808 1809 for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) { 1810 if (data->clk[i].vddo_reg) 1811 regulator_disable(data->clk[i].vddo_reg); 1812 } 1813 } 1814 1815 static const struct i2c_device_id si5341_id[] = { 1816 { "si5340", 0 }, 1817 { "si5341", 1 }, 1818 { "si5342", 2 }, 1819 { "si5344", 4 }, 1820 { "si5345", 5 }, 1821 { } 1822 }; 1823 MODULE_DEVICE_TABLE(i2c, si5341_id); 1824 1825 static const struct of_device_id clk_si5341_of_match[] = { 1826 { .compatible = "silabs,si5340" }, 1827 { .compatible = "silabs,si5341" }, 1828 { .compatible = "silabs,si5342" }, 1829 { .compatible = "silabs,si5344" }, 1830 { .compatible = "silabs,si5345" }, 1831 { } 1832 }; 1833 MODULE_DEVICE_TABLE(of, clk_si5341_of_match); 1834 1835 static struct i2c_driver si5341_driver = { 1836 .driver = { 1837 .name = "si5341", 1838 .of_match_table = clk_si5341_of_match, 1839 }, 1840 .probe_new = si5341_probe, 1841 .remove = si5341_remove, 1842 .id_table = si5341_id, 1843 }; 1844 module_i2c_driver(si5341_driver); 1845 1846 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 1847 MODULE_DESCRIPTION("Si5341 driver"); 1848 MODULE_LICENSE("GPL"); 1849