1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345 4 * Copyright (C) 2019 Topic Embedded Products 5 * Author: Mike Looijmans <mike.looijmans@topic.nl> 6 * 7 * The Si5341 has 10 outputs and 5 synthesizers. 8 * The Si5340 is a smaller version of the Si5341 with only 4 outputs. 9 * The Si5345 is similar to the Si5341, with the addition of fractional input 10 * dividers and automatic input selection. 11 * The Si5342 and Si5344 are smaller versions of the Si5345. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/gcd.h> 18 #include <linux/math64.h> 19 #include <linux/i2c.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 #include <asm/unaligned.h> 24 25 #define SI5341_NUM_INPUTS 4 26 27 #define SI5340_MAX_NUM_OUTPUTS 4 28 #define SI5341_MAX_NUM_OUTPUTS 10 29 #define SI5342_MAX_NUM_OUTPUTS 2 30 #define SI5344_MAX_NUM_OUTPUTS 4 31 #define SI5345_MAX_NUM_OUTPUTS 10 32 33 #define SI5340_NUM_SYNTH 4 34 #define SI5341_NUM_SYNTH 5 35 #define SI5342_NUM_SYNTH 2 36 #define SI5344_NUM_SYNTH 4 37 #define SI5345_NUM_SYNTH 5 38 39 /* Range of the synthesizer fractional divider */ 40 #define SI5341_SYNTH_N_MIN 10 41 #define SI5341_SYNTH_N_MAX 4095 42 43 /* The chip can get its input clock from 3 input pins or an XTAL */ 44 45 /* There is one PLL running at 13500–14256 MHz */ 46 #define SI5341_PLL_VCO_MIN 13500000000ull 47 #define SI5341_PLL_VCO_MAX 14256000000ull 48 49 /* The 5 frequency synthesizers obtain their input from the PLL */ 50 struct clk_si5341_synth { 51 struct clk_hw hw; 52 struct clk_si5341 *data; 53 u8 index; 54 }; 55 #define to_clk_si5341_synth(_hw) \ 56 container_of(_hw, struct clk_si5341_synth, hw) 57 58 /* The output stages can be connected to any synth (full mux) */ 59 struct clk_si5341_output { 60 struct clk_hw hw; 61 struct clk_si5341 *data; 62 u8 index; 63 }; 64 #define to_clk_si5341_output(_hw) \ 65 container_of(_hw, struct clk_si5341_output, hw) 66 67 struct clk_si5341 { 68 struct clk_hw hw; 69 struct regmap *regmap; 70 struct i2c_client *i2c_client; 71 struct clk_si5341_synth synth[SI5341_NUM_SYNTH]; 72 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; 73 struct clk *input_clk[SI5341_NUM_INPUTS]; 74 const char *input_clk_name[SI5341_NUM_INPUTS]; 75 const u16 *reg_output_offset; 76 const u16 *reg_rdiv_offset; 77 u64 freq_vco; /* 13500–14256 MHz */ 78 u8 num_outputs; 79 u8 num_synth; 80 u16 chip_id; 81 }; 82 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) 83 84 struct clk_si5341_output_config { 85 u8 out_format_drv_bits; 86 u8 out_cm_ampl_bits; 87 bool synth_master; 88 bool always_on; 89 }; 90 91 #define SI5341_PAGE 0x0001 92 #define SI5341_PN_BASE 0x0002 93 #define SI5341_DEVICE_REV 0x0005 94 #define SI5341_STATUS 0x000C 95 #define SI5341_SOFT_RST 0x001C 96 #define SI5341_IN_SEL 0x0021 97 #define SI5341_DEVICE_READY 0x00FE 98 #define SI5341_XAXB_CFG 0x090E 99 #define SI5341_IN_EN 0x0949 100 #define SI5341_INX_TO_PFD_EN 0x094A 101 102 /* Input selection */ 103 #define SI5341_IN_SEL_MASK 0x06 104 #define SI5341_IN_SEL_SHIFT 1 105 #define SI5341_IN_SEL_REGCTRL 0x01 106 #define SI5341_INX_TO_PFD_SHIFT 4 107 108 /* XTAL config bits */ 109 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0) 110 #define SI5341_XAXB_CFG_PDNB BIT(1) 111 112 /* Input dividers (48-bit) */ 113 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10)) 114 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10)) 115 #define SI5341_PX_UPD 0x0230 116 117 /* PLL configuration */ 118 #define SI5341_PLL_M_NUM 0x0235 119 #define SI5341_PLL_M_DEN 0x023B 120 121 /* Output configuration */ 122 #define SI5341_OUT_CONFIG(output) \ 123 ((output)->data->reg_output_offset[(output)->index]) 124 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) 125 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) 126 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) 127 #define SI5341_OUT_R_REG(output) \ 128 ((output)->data->reg_rdiv_offset[(output)->index]) 129 130 /* Synthesize N divider */ 131 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) 132 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) 133 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11)) 134 135 /* Synthesizer output enable, phase bypass, power mode */ 136 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03 137 #define SI5341_SYNTH_N_PIBYP 0x0A04 138 #define SI5341_SYNTH_N_PDNB 0x0A05 139 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A 140 141 #define SI5341_REGISTER_MAX 0xBFF 142 143 /* SI5341_OUT_CONFIG bits */ 144 #define SI5341_OUT_CFG_PDN BIT(0) 145 #define SI5341_OUT_CFG_OE BIT(1) 146 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) 147 148 /* Static configuration (to be moved to firmware) */ 149 struct si5341_reg_default { 150 u16 address; 151 u8 value; 152 }; 153 154 static const char * const si5341_input_clock_names[] = { 155 "in0", "in1", "in2", "xtal" 156 }; 157 158 /* Output configuration registers 0..9 are not quite logically organized */ 159 /* Also for si5345 */ 160 static const u16 si5341_reg_output_offset[] = { 161 0x0108, 162 0x010D, 163 0x0112, 164 0x0117, 165 0x011C, 166 0x0121, 167 0x0126, 168 0x012B, 169 0x0130, 170 0x013A, 171 }; 172 173 /* for si5340, si5342 and si5344 */ 174 static const u16 si5340_reg_output_offset[] = { 175 0x0112, 176 0x0117, 177 0x0126, 178 0x012B, 179 }; 180 181 /* The location of the R divider registers */ 182 static const u16 si5341_reg_rdiv_offset[] = { 183 0x024A, 184 0x024D, 185 0x0250, 186 0x0253, 187 0x0256, 188 0x0259, 189 0x025C, 190 0x025F, 191 0x0262, 192 0x0268, 193 }; 194 static const u16 si5340_reg_rdiv_offset[] = { 195 0x0250, 196 0x0253, 197 0x025C, 198 0x025F, 199 }; 200 201 /* 202 * Programming sequence from ClockBuilder, settings to initialize the system 203 * using only the XTAL input, without pre-divider. 204 * This also contains settings that aren't mentioned anywhere in the datasheet. 205 * The "known" settings like synth and output configuration are done later. 206 */ 207 static const struct si5341_reg_default si5341_reg_defaults[] = { 208 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */ 209 { 0x0018, 0xFF }, /* INT mask */ 210 { 0x0021, 0x0F }, /* Select XTAL as input */ 211 { 0x0022, 0x00 }, /* Not in datasheet */ 212 { 0x002B, 0x02 }, /* SPI config */ 213 { 0x002C, 0x20 }, /* LOS enable for XTAL */ 214 { 0x002D, 0x00 }, /* LOS timing */ 215 { 0x002E, 0x00 }, 216 { 0x002F, 0x00 }, 217 { 0x0030, 0x00 }, 218 { 0x0031, 0x00 }, 219 { 0x0032, 0x00 }, 220 { 0x0033, 0x00 }, 221 { 0x0034, 0x00 }, 222 { 0x0035, 0x00 }, 223 { 0x0036, 0x00 }, 224 { 0x0037, 0x00 }, 225 { 0x0038, 0x00 }, /* LOS setting (thresholds) */ 226 { 0x0039, 0x00 }, 227 { 0x003A, 0x00 }, 228 { 0x003B, 0x00 }, 229 { 0x003C, 0x00 }, 230 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */ 231 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */ 232 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */ 233 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */ 234 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */ 235 { 0x009E, 0x00 }, /* Not in datasheet */ 236 { 0x0102, 0x01 }, /* Enable outputs */ 237 { 0x013F, 0x00 }, /* Not in datasheet */ 238 { 0x0140, 0x00 }, /* Not in datasheet */ 239 { 0x0141, 0x40 }, /* OUT LOS */ 240 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/ 241 { 0x0203, 0x00 }, 242 { 0x0204, 0x00 }, 243 { 0x0205, 0x00 }, 244 { 0x0206, 0x00 }, /* PXAXB (2^x) */ 245 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */ 246 { 0x0209, 0x00 }, 247 { 0x020A, 0x00 }, 248 { 0x020B, 0x00 }, 249 { 0x020C, 0x00 }, 250 { 0x020D, 0x00 }, 251 { 0x020E, 0x00 }, 252 { 0x020F, 0x00 }, 253 { 0x0210, 0x00 }, 254 { 0x0211, 0x00 }, 255 { 0x0212, 0x00 }, 256 { 0x0213, 0x00 }, 257 { 0x0214, 0x00 }, 258 { 0x0215, 0x00 }, 259 { 0x0216, 0x00 }, 260 { 0x0217, 0x00 }, 261 { 0x0218, 0x00 }, 262 { 0x0219, 0x00 }, 263 { 0x021A, 0x00 }, 264 { 0x021B, 0x00 }, 265 { 0x021C, 0x00 }, 266 { 0x021D, 0x00 }, 267 { 0x021E, 0x00 }, 268 { 0x021F, 0x00 }, 269 { 0x0220, 0x00 }, 270 { 0x0221, 0x00 }, 271 { 0x0222, 0x00 }, 272 { 0x0223, 0x00 }, 273 { 0x0224, 0x00 }, 274 { 0x0225, 0x00 }, 275 { 0x0226, 0x00 }, 276 { 0x0227, 0x00 }, 277 { 0x0228, 0x00 }, 278 { 0x0229, 0x00 }, 279 { 0x022A, 0x00 }, 280 { 0x022B, 0x00 }, 281 { 0x022C, 0x00 }, 282 { 0x022D, 0x00 }, 283 { 0x022E, 0x00 }, 284 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */ 285 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */ 286 { 0x026C, 0x00 }, 287 { 0x026D, 0x00 }, 288 { 0x026E, 0x00 }, 289 { 0x026F, 0x00 }, 290 { 0x0270, 0x00 }, 291 { 0x0271, 0x00 }, 292 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */ 293 { 0x0339, 0x1F }, /* N_FSTEP_MSK */ 294 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */ 295 { 0x033C, 0x00 }, 296 { 0x033D, 0x00 }, 297 { 0x033E, 0x00 }, 298 { 0x033F, 0x00 }, 299 { 0x0340, 0x00 }, 300 { 0x0341, 0x00 }, 301 { 0x0342, 0x00 }, 302 { 0x0343, 0x00 }, 303 { 0x0344, 0x00 }, 304 { 0x0345, 0x00 }, 305 { 0x0346, 0x00 }, 306 { 0x0347, 0x00 }, 307 { 0x0348, 0x00 }, 308 { 0x0349, 0x00 }, 309 { 0x034A, 0x00 }, 310 { 0x034B, 0x00 }, 311 { 0x034C, 0x00 }, 312 { 0x034D, 0x00 }, 313 { 0x034E, 0x00 }, 314 { 0x034F, 0x00 }, 315 { 0x0350, 0x00 }, 316 { 0x0351, 0x00 }, 317 { 0x0352, 0x00 }, 318 { 0x0353, 0x00 }, 319 { 0x0354, 0x00 }, 320 { 0x0355, 0x00 }, 321 { 0x0356, 0x00 }, 322 { 0x0357, 0x00 }, 323 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */ 324 { 0x0359, 0x00 }, /* Nx_DELAY */ 325 { 0x035A, 0x00 }, 326 { 0x035B, 0x00 }, 327 { 0x035C, 0x00 }, 328 { 0x035D, 0x00 }, 329 { 0x035E, 0x00 }, 330 { 0x035F, 0x00 }, 331 { 0x0360, 0x00 }, 332 { 0x0361, 0x00 }, 333 { 0x0362, 0x00 }, /* Nx_DELAY end */ 334 { 0x0802, 0x00 }, /* Not in datasheet */ 335 { 0x0803, 0x00 }, /* Not in datasheet */ 336 { 0x0804, 0x00 }, /* Not in datasheet */ 337 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ 338 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ 339 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */ 340 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ 341 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ 342 { 0x0A02, 0x00 }, /* Not in datasheet */ 343 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ 344 }; 345 346 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ 347 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, 348 u64 *val1, u32 *val2) 349 { 350 int err; 351 u8 r[10]; 352 353 err = regmap_bulk_read(regmap, reg, r, 10); 354 if (err < 0) 355 return err; 356 357 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) | 358 (get_unaligned_le32(r)); 359 *val2 = get_unaligned_le32(&r[6]); 360 361 return 0; 362 } 363 364 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, 365 u64 n_num, u32 n_den) 366 { 367 u8 r[10]; 368 369 /* Shift left as far as possible without overflowing */ 370 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { 371 n_num <<= 1; 372 n_den <<= 1; 373 } 374 375 /* 44 bits (6 bytes) numerator */ 376 put_unaligned_le32(n_num, r); 377 r[4] = (n_num >> 32) & 0xff; 378 r[5] = (n_num >> 40) & 0x0f; 379 /* 32 bits denominator */ 380 put_unaligned_le32(n_den, &r[6]); 381 382 /* Program the fraction */ 383 return regmap_bulk_write(regmap, reg, r, sizeof(r)); 384 } 385 386 /* VCO, we assume it runs at a constant frequency */ 387 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw, 388 unsigned long parent_rate) 389 { 390 struct clk_si5341 *data = to_clk_si5341(hw); 391 int err; 392 u64 res; 393 u64 m_num; 394 u32 m_den; 395 unsigned int shift; 396 397 /* Assume that PDIV is not being used, just read the PLL setting */ 398 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, 399 &m_num, &m_den); 400 if (err < 0) 401 return 0; 402 403 if (!m_num || !m_den) 404 return 0; 405 406 /* 407 * Though m_num is 64-bit, only the upper bits are actually used. While 408 * calculating m_num and m_den, they are shifted as far as possible to 409 * the left. To avoid 96-bit division here, we just shift them back so 410 * we can do with just 64 bits. 411 */ 412 shift = 0; 413 res = m_num; 414 while (res & 0xffff00000000ULL) { 415 ++shift; 416 res >>= 1; 417 } 418 res *= parent_rate; 419 do_div(res, (m_den >> shift)); 420 421 /* We cannot return the actual frequency in 32 bit, store it locally */ 422 data->freq_vco = res; 423 424 /* Report kHz since the value is out of range */ 425 do_div(res, 1000); 426 427 return (unsigned long)res; 428 } 429 430 static int si5341_clk_get_selected_input(struct clk_si5341 *data) 431 { 432 int err; 433 u32 val; 434 435 err = regmap_read(data->regmap, SI5341_IN_SEL, &val); 436 if (err < 0) 437 return err; 438 439 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT; 440 } 441 442 static u8 si5341_clk_get_parent(struct clk_hw *hw) 443 { 444 struct clk_si5341 *data = to_clk_si5341(hw); 445 int res = si5341_clk_get_selected_input(data); 446 447 if (res < 0) 448 return 0; /* Apparently we cannot report errors */ 449 450 return res; 451 } 452 453 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) 454 { 455 int err; 456 u8 val; 457 458 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK; 459 /* Enable register-based input selection */ 460 val |= SI5341_IN_SEL_REGCTRL; 461 462 err = regmap_update_bits(data->regmap, 463 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val); 464 if (err < 0) 465 return err; 466 467 if (index < 3) { 468 /* Enable input buffer for selected input */ 469 err = regmap_update_bits(data->regmap, 470 SI5341_IN_EN, 0x07, BIT(index)); 471 if (err < 0) 472 return err; 473 474 /* Enables the input to phase detector */ 475 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 476 0x7 << SI5341_INX_TO_PFD_SHIFT, 477 BIT(index + SI5341_INX_TO_PFD_SHIFT)); 478 if (err < 0) 479 return err; 480 481 /* Power down XTAL oscillator and buffer */ 482 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 483 SI5341_XAXB_CFG_PDNB, 0); 484 if (err < 0) 485 return err; 486 487 /* 488 * Set the P divider to "1". There's no explanation in the 489 * datasheet of these registers, but the clockbuilder software 490 * programs a "1" when the input is being used. 491 */ 492 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); 493 if (err < 0) 494 return err; 495 496 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); 497 if (err < 0) 498 return err; 499 500 /* Set update PDIV bit */ 501 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); 502 if (err < 0) 503 return err; 504 } else { 505 /* Disable all input buffers */ 506 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); 507 if (err < 0) 508 return err; 509 510 /* Disable input to phase detector */ 511 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 512 0x7 << SI5341_INX_TO_PFD_SHIFT, 0); 513 if (err < 0) 514 return err; 515 516 /* Power up XTAL oscillator and buffer */ 517 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 518 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB); 519 if (err < 0) 520 return err; 521 } 522 523 return 0; 524 } 525 526 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index) 527 { 528 struct clk_si5341 *data = to_clk_si5341(hw); 529 530 return si5341_clk_reparent(data, index); 531 } 532 533 static const struct clk_ops si5341_clk_ops = { 534 .set_parent = si5341_clk_set_parent, 535 .get_parent = si5341_clk_get_parent, 536 .recalc_rate = si5341_clk_recalc_rate, 537 }; 538 539 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ 540 541 /* The synthesizer is on if all power and enable bits are set */ 542 static int si5341_synth_clk_is_on(struct clk_hw *hw) 543 { 544 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 545 int err; 546 u32 val; 547 u8 index = synth->index; 548 549 err = regmap_read(synth->data->regmap, 550 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); 551 if (err < 0) 552 return 0; 553 554 if (!(val & BIT(index))) 555 return 0; 556 557 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); 558 if (err < 0) 559 return 0; 560 561 if (!(val & BIT(index))) 562 return 0; 563 564 /* This bit must be 0 for the synthesizer to receive clock input */ 565 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); 566 if (err < 0) 567 return 0; 568 569 return !(val & BIT(index)); 570 } 571 572 static void si5341_synth_clk_unprepare(struct clk_hw *hw) 573 { 574 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 575 u8 index = synth->index; /* In range 0..5 */ 576 u8 mask = BIT(index); 577 578 /* Disable output */ 579 regmap_update_bits(synth->data->regmap, 580 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); 581 /* Power down */ 582 regmap_update_bits(synth->data->regmap, 583 SI5341_SYNTH_N_PDNB, mask, 0); 584 /* Disable clock input to synth (set to 1 to disable) */ 585 regmap_update_bits(synth->data->regmap, 586 SI5341_SYNTH_N_CLK_DIS, mask, mask); 587 } 588 589 static int si5341_synth_clk_prepare(struct clk_hw *hw) 590 { 591 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 592 int err; 593 u8 index = synth->index; 594 u8 mask = BIT(index); 595 596 /* Power up */ 597 err = regmap_update_bits(synth->data->regmap, 598 SI5341_SYNTH_N_PDNB, mask, mask); 599 if (err < 0) 600 return err; 601 602 /* Enable clock input to synth (set bit to 0 to enable) */ 603 err = regmap_update_bits(synth->data->regmap, 604 SI5341_SYNTH_N_CLK_DIS, mask, 0); 605 if (err < 0) 606 return err; 607 608 /* Enable output */ 609 return regmap_update_bits(synth->data->regmap, 610 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); 611 } 612 613 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ 614 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, 615 unsigned long parent_rate) 616 { 617 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 618 u64 f; 619 u64 n_num; 620 u32 n_den; 621 int err; 622 623 err = si5341_decode_44_32(synth->data->regmap, 624 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); 625 if (err < 0) 626 return err; 627 628 /* 629 * n_num and n_den are shifted left as much as possible, so to prevent 630 * overflow in 64-bit math, we shift n_den 4 bits to the right 631 */ 632 f = synth->data->freq_vco; 633 f *= n_den >> 4; 634 635 /* Now we need to to 64-bit division: f/n_num */ 636 /* And compensate for the 4 bits we dropped */ 637 f = div64_u64(f, (n_num >> 4)); 638 639 return f; 640 } 641 642 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate, 643 unsigned long *parent_rate) 644 { 645 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 646 u64 f; 647 648 /* The synthesizer accuracy is such that anything in range will work */ 649 f = synth->data->freq_vco; 650 do_div(f, SI5341_SYNTH_N_MAX); 651 if (rate < f) 652 return f; 653 654 f = synth->data->freq_vco; 655 do_div(f, SI5341_SYNTH_N_MIN); 656 if (rate > f) 657 return f; 658 659 return rate; 660 } 661 662 static int si5341_synth_program(struct clk_si5341_synth *synth, 663 u64 n_num, u32 n_den, bool is_integer) 664 { 665 int err; 666 u8 index = synth->index; 667 668 err = si5341_encode_44_32(synth->data->regmap, 669 SI5341_SYNTH_N_NUM(index), n_num, n_den); 670 671 err = regmap_update_bits(synth->data->regmap, 672 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); 673 if (err < 0) 674 return err; 675 676 return regmap_write(synth->data->regmap, 677 SI5341_SYNTH_N_UPD(index), 0x01); 678 } 679 680 681 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate, 682 unsigned long parent_rate) 683 { 684 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 685 u64 n_num; 686 u32 n_den; 687 u32 r; 688 u32 g; 689 bool is_integer; 690 691 n_num = synth->data->freq_vco; 692 693 /* see if there's an integer solution */ 694 r = do_div(n_num, rate); 695 is_integer = (r == 0); 696 if (is_integer) { 697 /* Integer divider equal to n_num */ 698 n_den = 1; 699 } else { 700 /* Calculate a fractional solution */ 701 g = gcd(r, rate); 702 n_den = rate / g; 703 n_num *= n_den; 704 n_num += r / g; 705 } 706 707 dev_dbg(&synth->data->i2c_client->dev, 708 "%s(%u): n=0x%llx d=0x%x %s\n", __func__, 709 synth->index, n_num, n_den, 710 is_integer ? "int" : "frac"); 711 712 return si5341_synth_program(synth, n_num, n_den, is_integer); 713 } 714 715 static const struct clk_ops si5341_synth_clk_ops = { 716 .is_prepared = si5341_synth_clk_is_on, 717 .prepare = si5341_synth_clk_prepare, 718 .unprepare = si5341_synth_clk_unprepare, 719 .recalc_rate = si5341_synth_clk_recalc_rate, 720 .round_rate = si5341_synth_clk_round_rate, 721 .set_rate = si5341_synth_clk_set_rate, 722 }; 723 724 static int si5341_output_clk_is_on(struct clk_hw *hw) 725 { 726 struct clk_si5341_output *output = to_clk_si5341_output(hw); 727 int err; 728 u32 val; 729 730 err = regmap_read(output->data->regmap, 731 SI5341_OUT_CONFIG(output), &val); 732 if (err < 0) 733 return err; 734 735 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ 736 return (val & 0x03) == SI5341_OUT_CFG_OE; 737 } 738 739 /* Disables and then powers down the output */ 740 static void si5341_output_clk_unprepare(struct clk_hw *hw) 741 { 742 struct clk_si5341_output *output = to_clk_si5341_output(hw); 743 744 regmap_update_bits(output->data->regmap, 745 SI5341_OUT_CONFIG(output), 746 SI5341_OUT_CFG_OE, 0); 747 regmap_update_bits(output->data->regmap, 748 SI5341_OUT_CONFIG(output), 749 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN); 750 } 751 752 /* Powers up and then enables the output */ 753 static int si5341_output_clk_prepare(struct clk_hw *hw) 754 { 755 struct clk_si5341_output *output = to_clk_si5341_output(hw); 756 int err; 757 758 err = regmap_update_bits(output->data->regmap, 759 SI5341_OUT_CONFIG(output), 760 SI5341_OUT_CFG_PDN, 0); 761 if (err < 0) 762 return err; 763 764 return regmap_update_bits(output->data->regmap, 765 SI5341_OUT_CONFIG(output), 766 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE); 767 } 768 769 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, 770 unsigned long parent_rate) 771 { 772 struct clk_si5341_output *output = to_clk_si5341_output(hw); 773 int err; 774 u32 val; 775 u32 r_divider; 776 u8 r[3]; 777 778 err = regmap_bulk_read(output->data->regmap, 779 SI5341_OUT_R_REG(output), r, 3); 780 if (err < 0) 781 return err; 782 783 /* Calculate value as 24-bit integer*/ 784 r_divider = r[2] << 16 | r[1] << 8 | r[0]; 785 786 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ 787 if (!r_divider) 788 return 0; 789 790 /* Divider is 2*(Rx_REG+1) */ 791 r_divider += 1; 792 r_divider <<= 1; 793 794 err = regmap_read(output->data->regmap, 795 SI5341_OUT_CONFIG(output), &val); 796 if (err < 0) 797 return err; 798 799 if (val & SI5341_OUT_CFG_RDIV_FORCE2) 800 r_divider = 2; 801 802 return parent_rate / r_divider; 803 } 804 805 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate, 806 unsigned long *parent_rate) 807 { 808 unsigned long r; 809 810 r = *parent_rate >> 1; 811 812 /* If rate is an even divisor, no changes to parent required */ 813 if (r && !(r % rate)) 814 return (long)rate; 815 816 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 817 if (rate > 200000000) { 818 /* minimum r-divider is 2 */ 819 r = 2; 820 } else { 821 /* Take a parent frequency near 400 MHz */ 822 r = (400000000u / rate) & ~1; 823 } 824 *parent_rate = r * rate; 825 } else { 826 /* We cannot change our parent's rate, report what we can do */ 827 r /= rate; 828 rate = *parent_rate / (r << 1); 829 } 830 831 return rate; 832 } 833 834 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, 835 unsigned long parent_rate) 836 { 837 struct clk_si5341_output *output = to_clk_si5341_output(hw); 838 /* Frequency divider is (r_div + 1) * 2 */ 839 u32 r_div = (parent_rate / rate) >> 1; 840 int err; 841 u8 r[3]; 842 843 if (r_div <= 1) 844 r_div = 0; 845 else if (r_div >= BIT(24)) 846 r_div = BIT(24) - 1; 847 else 848 --r_div; 849 850 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ 851 err = regmap_update_bits(output->data->regmap, 852 SI5341_OUT_CONFIG(output), 853 SI5341_OUT_CFG_RDIV_FORCE2, 854 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0); 855 if (err < 0) 856 return err; 857 858 /* Always write Rx_REG, because a zero value disables the divider */ 859 r[0] = r_div ? (r_div & 0xff) : 1; 860 r[1] = (r_div >> 8) & 0xff; 861 r[2] = (r_div >> 16) & 0xff; 862 err = regmap_bulk_write(output->data->regmap, 863 SI5341_OUT_R_REG(output), r, 3); 864 865 return 0; 866 } 867 868 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) 869 { 870 return regmap_update_bits(output->data->regmap, 871 SI5341_OUT_MUX_SEL(output), 0x07, index); 872 } 873 874 static int si5341_output_set_parent(struct clk_hw *hw, u8 index) 875 { 876 struct clk_si5341_output *output = to_clk_si5341_output(hw); 877 878 if (index >= output->data->num_synth) 879 return -EINVAL; 880 881 return si5341_output_reparent(output, index); 882 } 883 884 static u8 si5341_output_get_parent(struct clk_hw *hw) 885 { 886 struct clk_si5341_output *output = to_clk_si5341_output(hw); 887 u32 val; 888 889 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val); 890 891 return val & 0x7; 892 } 893 894 static const struct clk_ops si5341_output_clk_ops = { 895 .is_prepared = si5341_output_clk_is_on, 896 .prepare = si5341_output_clk_prepare, 897 .unprepare = si5341_output_clk_unprepare, 898 .recalc_rate = si5341_output_clk_recalc_rate, 899 .round_rate = si5341_output_clk_round_rate, 900 .set_rate = si5341_output_clk_set_rate, 901 .set_parent = si5341_output_set_parent, 902 .get_parent = si5341_output_get_parent, 903 }; 904 905 /* 906 * The chip can be bought in a pre-programmed version, or one can program the 907 * NVM in the chip to boot up in a preset mode. This routine tries to determine 908 * if that's the case, or if we need to reset and program everything from 909 * scratch. Returns negative error, or true/false. 910 */ 911 static int si5341_is_programmed_already(struct clk_si5341 *data) 912 { 913 int err; 914 u8 r[4]; 915 916 /* Read the PLL divider value, it must have a non-zero value */ 917 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, 918 r, ARRAY_SIZE(r)); 919 if (err < 0) 920 return err; 921 922 return !!get_unaligned_le32(r); 923 } 924 925 static struct clk_hw * 926 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data) 927 { 928 struct clk_si5341 *data = _data; 929 unsigned int idx = clkspec->args[1]; 930 unsigned int group = clkspec->args[0]; 931 932 switch (group) { 933 case 0: 934 if (idx >= data->num_outputs) { 935 dev_err(&data->i2c_client->dev, 936 "invalid output index %u\n", idx); 937 return ERR_PTR(-EINVAL); 938 } 939 return &data->clk[idx].hw; 940 case 1: 941 if (idx >= data->num_synth) { 942 dev_err(&data->i2c_client->dev, 943 "invalid synthesizer index %u\n", idx); 944 return ERR_PTR(-EINVAL); 945 } 946 return &data->synth[idx].hw; 947 case 2: 948 if (idx > 0) { 949 dev_err(&data->i2c_client->dev, 950 "invalid PLL index %u\n", idx); 951 return ERR_PTR(-EINVAL); 952 } 953 return &data->hw; 954 default: 955 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); 956 return ERR_PTR(-EINVAL); 957 } 958 } 959 960 static int si5341_probe_chip_id(struct clk_si5341 *data) 961 { 962 int err; 963 u8 reg[4]; 964 u16 model; 965 966 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, 967 ARRAY_SIZE(reg)); 968 if (err < 0) { 969 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); 970 return err; 971 } 972 973 model = get_unaligned_le16(reg); 974 975 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", 976 model, reg[2], reg[3]); 977 978 switch (model) { 979 case 0x5340: 980 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; 981 data->num_synth = SI5340_NUM_SYNTH; 982 data->reg_output_offset = si5340_reg_output_offset; 983 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 984 break; 985 case 0x5341: 986 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; 987 data->num_synth = SI5341_NUM_SYNTH; 988 data->reg_output_offset = si5341_reg_output_offset; 989 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 990 break; 991 case 0x5342: 992 data->num_outputs = SI5342_MAX_NUM_OUTPUTS; 993 data->num_synth = SI5342_NUM_SYNTH; 994 data->reg_output_offset = si5340_reg_output_offset; 995 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 996 break; 997 case 0x5344: 998 data->num_outputs = SI5344_MAX_NUM_OUTPUTS; 999 data->num_synth = SI5344_NUM_SYNTH; 1000 data->reg_output_offset = si5340_reg_output_offset; 1001 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 1002 break; 1003 case 0x5345: 1004 data->num_outputs = SI5345_MAX_NUM_OUTPUTS; 1005 data->num_synth = SI5345_NUM_SYNTH; 1006 data->reg_output_offset = si5341_reg_output_offset; 1007 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 1008 break; 1009 default: 1010 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", 1011 model); 1012 return -EINVAL; 1013 } 1014 1015 data->chip_id = model; 1016 1017 return 0; 1018 } 1019 1020 /* Read active settings into the regmap cache for later reference */ 1021 static int si5341_read_settings(struct clk_si5341 *data) 1022 { 1023 int err; 1024 u8 i; 1025 u8 r[10]; 1026 1027 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); 1028 if (err < 0) 1029 return err; 1030 1031 err = regmap_bulk_read(data->regmap, 1032 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3); 1033 if (err < 0) 1034 return err; 1035 1036 err = regmap_bulk_read(data->regmap, 1037 SI5341_SYNTH_N_CLK_DIS, r, 1); 1038 if (err < 0) 1039 return err; 1040 1041 for (i = 0; i < data->num_synth; ++i) { 1042 err = regmap_bulk_read(data->regmap, 1043 SI5341_SYNTH_N_NUM(i), r, 10); 1044 if (err < 0) 1045 return err; 1046 } 1047 1048 for (i = 0; i < data->num_outputs; ++i) { 1049 err = regmap_bulk_read(data->regmap, 1050 data->reg_output_offset[i], r, 4); 1051 if (err < 0) 1052 return err; 1053 1054 err = regmap_bulk_read(data->regmap, 1055 data->reg_rdiv_offset[i], r, 3); 1056 if (err < 0) 1057 return err; 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int si5341_write_multiple(struct clk_si5341 *data, 1064 const struct si5341_reg_default *values, unsigned int num_values) 1065 { 1066 unsigned int i; 1067 int res; 1068 1069 for (i = 0; i < num_values; ++i) { 1070 res = regmap_write(data->regmap, 1071 values[i].address, values[i].value); 1072 if (res < 0) { 1073 dev_err(&data->i2c_client->dev, 1074 "Failed to write %#x:%#x\n", 1075 values[i].address, values[i].value); 1076 return res; 1077 } 1078 } 1079 1080 return 0; 1081 } 1082 1083 static const struct si5341_reg_default si5341_preamble[] = { 1084 { 0x0B25, 0x00 }, 1085 { 0x0502, 0x01 }, 1086 { 0x0505, 0x03 }, 1087 { 0x0957, 0x1F }, 1088 { 0x0B4E, 0x1A }, 1089 }; 1090 1091 static const struct si5341_reg_default si5345_preamble[] = { 1092 { 0x0B25, 0x00 }, 1093 { 0x0540, 0x01 }, 1094 }; 1095 1096 static int si5341_send_preamble(struct clk_si5341 *data) 1097 { 1098 int res; 1099 u32 revision; 1100 1101 /* For revision 2 and up, the values are slightly different */ 1102 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1103 if (res < 0) 1104 return res; 1105 1106 /* Write "preamble" as specified by datasheet */ 1107 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); 1108 if (res < 0) 1109 return res; 1110 1111 /* The si5342..si5345 require a different preamble */ 1112 if (data->chip_id > 0x5341) 1113 res = si5341_write_multiple(data, 1114 si5345_preamble, ARRAY_SIZE(si5345_preamble)); 1115 else 1116 res = si5341_write_multiple(data, 1117 si5341_preamble, ARRAY_SIZE(si5341_preamble)); 1118 if (res < 0) 1119 return res; 1120 1121 /* Datasheet specifies a 300ms wait after sending the preamble */ 1122 msleep(300); 1123 1124 return 0; 1125 } 1126 1127 /* Perform a soft reset and write post-amble */ 1128 static int si5341_finalize_defaults(struct clk_si5341 *data) 1129 { 1130 int res; 1131 u32 revision; 1132 1133 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1134 if (res < 0) 1135 return res; 1136 1137 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); 1138 1139 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); 1140 if (res < 0) 1141 return res; 1142 1143 /* The si5342..si5345 have an additional post-amble */ 1144 if (data->chip_id > 0x5341) { 1145 res = regmap_write(data->regmap, 0x540, 0x0); 1146 if (res < 0) 1147 return res; 1148 } 1149 1150 /* Datasheet does not explain these nameless registers */ 1151 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); 1152 if (res < 0) 1153 return res; 1154 res = regmap_write(data->regmap, 0x0B25, 0x02); 1155 if (res < 0) 1156 return res; 1157 1158 return 0; 1159 } 1160 1161 1162 static const struct regmap_range si5341_regmap_volatile_range[] = { 1163 regmap_reg_range(0x000C, 0x0012), /* Status */ 1164 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */ 1165 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */ 1166 /* Update bits for P divider and synth config */ 1167 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD), 1168 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)), 1169 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)), 1170 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)), 1171 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)), 1172 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)), 1173 }; 1174 1175 static const struct regmap_access_table si5341_regmap_volatile = { 1176 .yes_ranges = si5341_regmap_volatile_range, 1177 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range), 1178 }; 1179 1180 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ 1181 static const struct regmap_range_cfg si5341_regmap_ranges[] = { 1182 { 1183 .range_min = 0, 1184 .range_max = SI5341_REGISTER_MAX, 1185 .selector_reg = SI5341_PAGE, 1186 .selector_mask = 0xff, 1187 .selector_shift = 0, 1188 .window_start = 0, 1189 .window_len = 256, 1190 }, 1191 }; 1192 1193 static int si5341_wait_device_ready(struct i2c_client *client) 1194 { 1195 int count; 1196 1197 /* Datasheet warns: Any attempt to read or write any register other 1198 * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the 1199 * NVM programming and may corrupt the register contents, as they are 1200 * read from NVM. Note that this includes accesses to the PAGE register. 1201 * Also: DEVICE_READY is available on every register page, so no page 1202 * change is needed to read it. 1203 * Do this outside regmap to avoid automatic PAGE register access. 1204 * May take up to 300ms to complete. 1205 */ 1206 for (count = 0; count < 15; ++count) { 1207 s32 result = i2c_smbus_read_byte_data(client, 1208 SI5341_DEVICE_READY); 1209 if (result < 0) 1210 return result; 1211 if (result == 0x0F) 1212 return 0; 1213 msleep(20); 1214 } 1215 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); 1216 return -EIO; 1217 } 1218 1219 static const struct regmap_config si5341_regmap_config = { 1220 .reg_bits = 8, 1221 .val_bits = 8, 1222 .cache_type = REGCACHE_RBTREE, 1223 .ranges = si5341_regmap_ranges, 1224 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges), 1225 .max_register = SI5341_REGISTER_MAX, 1226 .volatile_table = &si5341_regmap_volatile, 1227 }; 1228 1229 static int si5341_dt_parse_dt(struct i2c_client *client, 1230 struct clk_si5341_output_config *config) 1231 { 1232 struct device_node *child; 1233 struct device_node *np = client->dev.of_node; 1234 u32 num; 1235 u32 val; 1236 1237 memset(config, 0, sizeof(struct clk_si5341_output_config) * 1238 SI5341_MAX_NUM_OUTPUTS); 1239 1240 for_each_child_of_node(np, child) { 1241 if (of_property_read_u32(child, "reg", &num)) { 1242 dev_err(&client->dev, "missing reg property of %s\n", 1243 child->name); 1244 goto put_child; 1245 } 1246 1247 if (num >= SI5341_MAX_NUM_OUTPUTS) { 1248 dev_err(&client->dev, "invalid clkout %d\n", num); 1249 goto put_child; 1250 } 1251 1252 if (!of_property_read_u32(child, "silabs,format", &val)) { 1253 /* Set cm and ampl conservatively to 3v3 settings */ 1254 switch (val) { 1255 case 1: /* normal differential */ 1256 config[num].out_cm_ampl_bits = 0x33; 1257 break; 1258 case 2: /* low-power differential */ 1259 config[num].out_cm_ampl_bits = 0x13; 1260 break; 1261 case 4: /* LVCMOS */ 1262 config[num].out_cm_ampl_bits = 0x33; 1263 /* Set SI recommended impedance for LVCMOS */ 1264 config[num].out_format_drv_bits |= 0xc0; 1265 break; 1266 default: 1267 dev_err(&client->dev, 1268 "invalid silabs,format %u for %u\n", 1269 val, num); 1270 goto put_child; 1271 } 1272 config[num].out_format_drv_bits &= ~0x07; 1273 config[num].out_format_drv_bits |= val & 0x07; 1274 /* Always enable the SYNC feature */ 1275 config[num].out_format_drv_bits |= 0x08; 1276 } 1277 1278 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { 1279 if (val > 0xf) { 1280 dev_err(&client->dev, 1281 "invalid silabs,common-mode %u\n", 1282 val); 1283 goto put_child; 1284 } 1285 config[num].out_cm_ampl_bits &= 0xf0; 1286 config[num].out_cm_ampl_bits |= val & 0x0f; 1287 } 1288 1289 if (!of_property_read_u32(child, "silabs,amplitude", &val)) { 1290 if (val > 0xf) { 1291 dev_err(&client->dev, 1292 "invalid silabs,amplitude %u\n", 1293 val); 1294 goto put_child; 1295 } 1296 config[num].out_cm_ampl_bits &= 0x0f; 1297 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; 1298 } 1299 1300 if (of_property_read_bool(child, "silabs,disable-high")) 1301 config[num].out_format_drv_bits |= 0x10; 1302 1303 config[num].synth_master = 1304 of_property_read_bool(child, "silabs,synth-master"); 1305 1306 config[num].always_on = 1307 of_property_read_bool(child, "always-on"); 1308 } 1309 1310 return 0; 1311 1312 put_child: 1313 of_node_put(child); 1314 return -EINVAL; 1315 } 1316 1317 /* 1318 * If not pre-configured, calculate and set the PLL configuration manually. 1319 * For low-jitter performance, the PLL should be set such that the synthesizers 1320 * only need integer division. 1321 * Without any user guidance, we'll set the PLL to 14GHz, which still allows 1322 * the chip to generate any frequency on its outputs, but jitter performance 1323 * may be sub-optimal. 1324 */ 1325 static int si5341_initialize_pll(struct clk_si5341 *data) 1326 { 1327 struct device_node *np = data->i2c_client->dev.of_node; 1328 u32 m_num = 0; 1329 u32 m_den = 0; 1330 int sel; 1331 1332 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { 1333 dev_err(&data->i2c_client->dev, 1334 "PLL configuration requires silabs,pll-m-num\n"); 1335 } 1336 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { 1337 dev_err(&data->i2c_client->dev, 1338 "PLL configuration requires silabs,pll-m-den\n"); 1339 } 1340 1341 if (!m_num || !m_den) { 1342 dev_err(&data->i2c_client->dev, 1343 "PLL configuration invalid, assume 14GHz\n"); 1344 sel = si5341_clk_get_selected_input(data); 1345 if (sel < 0) 1346 return sel; 1347 1348 m_den = clk_get_rate(data->input_clk[sel]) / 10; 1349 m_num = 1400000000; 1350 } 1351 1352 return si5341_encode_44_32(data->regmap, 1353 SI5341_PLL_M_NUM, m_num, m_den); 1354 } 1355 1356 static int si5341_clk_select_active_input(struct clk_si5341 *data) 1357 { 1358 int res; 1359 int err; 1360 int i; 1361 1362 res = si5341_clk_get_selected_input(data); 1363 if (res < 0) 1364 return res; 1365 1366 /* If the current register setting is invalid, pick the first input */ 1367 if (!data->input_clk[res]) { 1368 dev_dbg(&data->i2c_client->dev, 1369 "Input %d not connected, rerouting\n", res); 1370 res = -ENODEV; 1371 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1372 if (data->input_clk[i]) { 1373 res = i; 1374 break; 1375 } 1376 } 1377 if (res < 0) { 1378 dev_err(&data->i2c_client->dev, 1379 "No clock input available\n"); 1380 return res; 1381 } 1382 } 1383 1384 /* Make sure the selected clock is also enabled and routed */ 1385 err = si5341_clk_reparent(data, res); 1386 if (err < 0) 1387 return err; 1388 1389 err = clk_prepare_enable(data->input_clk[res]); 1390 if (err < 0) 1391 return err; 1392 1393 return res; 1394 } 1395 1396 static int si5341_probe(struct i2c_client *client, 1397 const struct i2c_device_id *id) 1398 { 1399 struct clk_si5341 *data; 1400 struct clk_init_data init; 1401 struct clk *input; 1402 const char *root_clock_name; 1403 const char *synth_clock_names[SI5341_NUM_SYNTH]; 1404 int err; 1405 unsigned int i; 1406 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; 1407 bool initialization_required; 1408 1409 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 1410 if (!data) 1411 return -ENOMEM; 1412 1413 data->i2c_client = client; 1414 1415 /* Must be done before otherwise touching hardware */ 1416 err = si5341_wait_device_ready(client); 1417 if (err) 1418 return err; 1419 1420 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1421 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); 1422 if (IS_ERR(input)) { 1423 if (PTR_ERR(input) == -EPROBE_DEFER) 1424 return -EPROBE_DEFER; 1425 data->input_clk_name[i] = si5341_input_clock_names[i]; 1426 } else { 1427 data->input_clk[i] = input; 1428 data->input_clk_name[i] = __clk_get_name(input); 1429 } 1430 } 1431 1432 err = si5341_dt_parse_dt(client, config); 1433 if (err) 1434 return err; 1435 1436 if (of_property_read_string(client->dev.of_node, "clock-output-names", 1437 &init.name)) 1438 init.name = client->dev.of_node->name; 1439 root_clock_name = init.name; 1440 1441 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); 1442 if (IS_ERR(data->regmap)) 1443 return PTR_ERR(data->regmap); 1444 1445 i2c_set_clientdata(client, data); 1446 1447 err = si5341_probe_chip_id(data); 1448 if (err < 0) 1449 return err; 1450 1451 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { 1452 initialization_required = true; 1453 } else { 1454 err = si5341_is_programmed_already(data); 1455 if (err < 0) 1456 return err; 1457 1458 initialization_required = !err; 1459 } 1460 1461 if (initialization_required) { 1462 /* Populate the regmap cache in preparation for "cache only" */ 1463 err = si5341_read_settings(data); 1464 if (err < 0) 1465 return err; 1466 1467 err = si5341_send_preamble(data); 1468 if (err < 0) 1469 return err; 1470 1471 /* 1472 * We intend to send all 'final' register values in a single 1473 * transaction. So cache all register writes until we're done 1474 * configuring. 1475 */ 1476 regcache_cache_only(data->regmap, true); 1477 1478 /* Write the configuration pairs from the firmware blob */ 1479 err = si5341_write_multiple(data, si5341_reg_defaults, 1480 ARRAY_SIZE(si5341_reg_defaults)); 1481 if (err < 0) 1482 return err; 1483 } 1484 1485 /* Input must be up and running at this point */ 1486 err = si5341_clk_select_active_input(data); 1487 if (err < 0) 1488 return err; 1489 1490 if (initialization_required) { 1491 /* PLL configuration is required */ 1492 err = si5341_initialize_pll(data); 1493 if (err < 0) 1494 return err; 1495 } 1496 1497 /* Register the PLL */ 1498 init.parent_names = data->input_clk_name; 1499 init.num_parents = SI5341_NUM_INPUTS; 1500 init.ops = &si5341_clk_ops; 1501 init.flags = 0; 1502 data->hw.init = &init; 1503 1504 err = devm_clk_hw_register(&client->dev, &data->hw); 1505 if (err) { 1506 dev_err(&client->dev, "clock registration failed\n"); 1507 return err; 1508 } 1509 1510 init.num_parents = 1; 1511 init.parent_names = &root_clock_name; 1512 init.ops = &si5341_synth_clk_ops; 1513 for (i = 0; i < data->num_synth; ++i) { 1514 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, 1515 "%s.N%u", client->dev.of_node->name, i); 1516 init.name = synth_clock_names[i]; 1517 data->synth[i].index = i; 1518 data->synth[i].data = data; 1519 data->synth[i].hw.init = &init; 1520 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); 1521 if (err) { 1522 dev_err(&client->dev, 1523 "synth N%u registration failed\n", i); 1524 } 1525 } 1526 1527 init.num_parents = data->num_synth; 1528 init.parent_names = synth_clock_names; 1529 init.ops = &si5341_output_clk_ops; 1530 for (i = 0; i < data->num_outputs; ++i) { 1531 init.name = kasprintf(GFP_KERNEL, "%s.%d", 1532 client->dev.of_node->name, i); 1533 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0; 1534 data->clk[i].index = i; 1535 data->clk[i].data = data; 1536 data->clk[i].hw.init = &init; 1537 if (config[i].out_format_drv_bits & 0x07) { 1538 regmap_write(data->regmap, 1539 SI5341_OUT_FORMAT(&data->clk[i]), 1540 config[i].out_format_drv_bits); 1541 regmap_write(data->regmap, 1542 SI5341_OUT_CM(&data->clk[i]), 1543 config[i].out_cm_ampl_bits); 1544 } 1545 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 1546 kfree(init.name); /* clock framework made a copy of the name */ 1547 if (err) { 1548 dev_err(&client->dev, 1549 "output %u registration failed\n", i); 1550 return err; 1551 } 1552 if (config[i].always_on) 1553 clk_prepare(data->clk[i].hw.clk); 1554 } 1555 1556 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get, 1557 data); 1558 if (err) { 1559 dev_err(&client->dev, "unable to add clk provider\n"); 1560 return err; 1561 } 1562 1563 if (initialization_required) { 1564 /* Synchronize */ 1565 regcache_cache_only(data->regmap, false); 1566 err = regcache_sync(data->regmap); 1567 if (err < 0) 1568 return err; 1569 1570 err = si5341_finalize_defaults(data); 1571 if (err < 0) 1572 return err; 1573 } 1574 1575 /* Free the names, clk framework makes copies */ 1576 for (i = 0; i < data->num_synth; ++i) 1577 devm_kfree(&client->dev, (void *)synth_clock_names[i]); 1578 1579 return 0; 1580 } 1581 1582 static const struct i2c_device_id si5341_id[] = { 1583 { "si5340", 0 }, 1584 { "si5341", 1 }, 1585 { "si5342", 2 }, 1586 { "si5344", 4 }, 1587 { "si5345", 5 }, 1588 { } 1589 }; 1590 MODULE_DEVICE_TABLE(i2c, si5341_id); 1591 1592 static const struct of_device_id clk_si5341_of_match[] = { 1593 { .compatible = "silabs,si5340" }, 1594 { .compatible = "silabs,si5341" }, 1595 { .compatible = "silabs,si5342" }, 1596 { .compatible = "silabs,si5344" }, 1597 { .compatible = "silabs,si5345" }, 1598 { } 1599 }; 1600 MODULE_DEVICE_TABLE(of, clk_si5341_of_match); 1601 1602 static struct i2c_driver si5341_driver = { 1603 .driver = { 1604 .name = "si5341", 1605 .of_match_table = clk_si5341_of_match, 1606 }, 1607 .probe = si5341_probe, 1608 .id_table = si5341_id, 1609 }; 1610 module_i2c_driver(si5341_driver); 1611 1612 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 1613 MODULE_DESCRIPTION("Si5341 driver"); 1614 MODULE_LICENSE("GPL"); 1615