1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Silicon Labs Si5341/Si5340 Clock generator 4 * Copyright (C) 2019 Topic Embedded Products 5 * Author: Mike Looijmans <mike.looijmans@topic.nl> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/gcd.h> 12 #include <linux/math64.h> 13 #include <linux/i2c.h> 14 #include <linux/module.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <asm/unaligned.h> 18 19 #define SI5341_NUM_INPUTS 4 20 21 #define SI5341_MAX_NUM_OUTPUTS 10 22 #define SI5340_MAX_NUM_OUTPUTS 4 23 24 #define SI5341_NUM_SYNTH 5 25 #define SI5340_NUM_SYNTH 4 26 27 /* Range of the synthesizer fractional divider */ 28 #define SI5341_SYNTH_N_MIN 10 29 #define SI5341_SYNTH_N_MAX 4095 30 31 /* The chip can get its input clock from 3 input pins or an XTAL */ 32 33 /* There is one PLL running at 13500–14256 MHz */ 34 #define SI5341_PLL_VCO_MIN 13500000000ull 35 #define SI5341_PLL_VCO_MAX 14256000000ull 36 37 /* The 5 frequency synthesizers obtain their input from the PLL */ 38 struct clk_si5341_synth { 39 struct clk_hw hw; 40 struct clk_si5341 *data; 41 u8 index; 42 }; 43 #define to_clk_si5341_synth(_hw) \ 44 container_of(_hw, struct clk_si5341_synth, hw) 45 46 /* The output stages can be connected to any synth (full mux) */ 47 struct clk_si5341_output { 48 struct clk_hw hw; 49 struct clk_si5341 *data; 50 u8 index; 51 }; 52 #define to_clk_si5341_output(_hw) \ 53 container_of(_hw, struct clk_si5341_output, hw) 54 55 struct clk_si5341 { 56 struct clk_hw hw; 57 struct regmap *regmap; 58 struct i2c_client *i2c_client; 59 struct clk_si5341_synth synth[SI5341_NUM_SYNTH]; 60 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; 61 struct clk *input_clk[SI5341_NUM_INPUTS]; 62 const char *input_clk_name[SI5341_NUM_INPUTS]; 63 const u16 *reg_output_offset; 64 const u16 *reg_rdiv_offset; 65 u64 freq_vco; /* 13500–14256 MHz */ 66 u8 num_outputs; 67 u8 num_synth; 68 }; 69 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw) 70 71 struct clk_si5341_output_config { 72 u8 out_format_drv_bits; 73 u8 out_cm_ampl_bits; 74 bool synth_master; 75 bool always_on; 76 }; 77 78 #define SI5341_PAGE 0x0001 79 #define SI5341_PN_BASE 0x0002 80 #define SI5341_DEVICE_REV 0x0005 81 #define SI5341_STATUS 0x000C 82 #define SI5341_SOFT_RST 0x001C 83 #define SI5341_IN_SEL 0x0021 84 #define SI5341_XAXB_CFG 0x090E 85 #define SI5341_IN_EN 0x0949 86 #define SI5341_INX_TO_PFD_EN 0x094A 87 88 /* Input selection */ 89 #define SI5341_IN_SEL_MASK 0x06 90 #define SI5341_IN_SEL_SHIFT 1 91 #define SI5341_IN_SEL_REGCTRL 0x01 92 #define SI5341_INX_TO_PFD_SHIFT 4 93 94 /* XTAL config bits */ 95 #define SI5341_XAXB_CFG_EXTCLK_EN BIT(0) 96 #define SI5341_XAXB_CFG_PDNB BIT(1) 97 98 /* Input dividers (48-bit) */ 99 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10)) 100 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10)) 101 #define SI5341_PX_UPD 0x0230 102 103 /* PLL configuration */ 104 #define SI5341_PLL_M_NUM 0x0235 105 #define SI5341_PLL_M_DEN 0x023B 106 107 /* Output configuration */ 108 #define SI5341_OUT_CONFIG(output) \ 109 ((output)->data->reg_output_offset[(output)->index]) 110 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1) 111 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2) 112 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3) 113 #define SI5341_OUT_R_REG(output) \ 114 ((output)->data->reg_rdiv_offset[(output)->index]) 115 116 /* Synthesize N divider */ 117 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11)) 118 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11)) 119 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11)) 120 121 /* Synthesizer output enable, phase bypass, power mode */ 122 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03 123 #define SI5341_SYNTH_N_PIBYP 0x0A04 124 #define SI5341_SYNTH_N_PDNB 0x0A05 125 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A 126 127 #define SI5341_REGISTER_MAX 0xBFF 128 129 /* SI5341_OUT_CONFIG bits */ 130 #define SI5341_OUT_CFG_PDN BIT(0) 131 #define SI5341_OUT_CFG_OE BIT(1) 132 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2) 133 134 /* Static configuration (to be moved to firmware) */ 135 struct si5341_reg_default { 136 u16 address; 137 u8 value; 138 }; 139 140 static const char * const si5341_input_clock_names[] = { 141 "in0", "in1", "in2", "xtal" 142 }; 143 144 /* Output configuration registers 0..9 are not quite logically organized */ 145 static const u16 si5341_reg_output_offset[] = { 146 0x0108, 147 0x010D, 148 0x0112, 149 0x0117, 150 0x011C, 151 0x0121, 152 0x0126, 153 0x012B, 154 0x0130, 155 0x013A, 156 }; 157 158 static const u16 si5340_reg_output_offset[] = { 159 0x0112, 160 0x0117, 161 0x0126, 162 0x012B, 163 }; 164 165 /* The location of the R divider registers */ 166 static const u16 si5341_reg_rdiv_offset[] = { 167 0x024A, 168 0x024D, 169 0x0250, 170 0x0253, 171 0x0256, 172 0x0259, 173 0x025C, 174 0x025F, 175 0x0262, 176 0x0268, 177 }; 178 static const u16 si5340_reg_rdiv_offset[] = { 179 0x0250, 180 0x0253, 181 0x025C, 182 0x025F, 183 }; 184 185 /* 186 * Programming sequence from ClockBuilder, settings to initialize the system 187 * using only the XTAL input, without pre-divider. 188 * This also contains settings that aren't mentioned anywhere in the datasheet. 189 * The "known" settings like synth and output configuration are done later. 190 */ 191 static const struct si5341_reg_default si5341_reg_defaults[] = { 192 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */ 193 { 0x0018, 0xFF }, /* INT mask */ 194 { 0x0021, 0x0F }, /* Select XTAL as input */ 195 { 0x0022, 0x00 }, /* Not in datasheet */ 196 { 0x002B, 0x02 }, /* SPI config */ 197 { 0x002C, 0x20 }, /* LOS enable for XTAL */ 198 { 0x002D, 0x00 }, /* LOS timing */ 199 { 0x002E, 0x00 }, 200 { 0x002F, 0x00 }, 201 { 0x0030, 0x00 }, 202 { 0x0031, 0x00 }, 203 { 0x0032, 0x00 }, 204 { 0x0033, 0x00 }, 205 { 0x0034, 0x00 }, 206 { 0x0035, 0x00 }, 207 { 0x0036, 0x00 }, 208 { 0x0037, 0x00 }, 209 { 0x0038, 0x00 }, /* LOS setting (thresholds) */ 210 { 0x0039, 0x00 }, 211 { 0x003A, 0x00 }, 212 { 0x003B, 0x00 }, 213 { 0x003C, 0x00 }, 214 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */ 215 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */ 216 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */ 217 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */ 218 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */ 219 { 0x009E, 0x00 }, /* Not in datasheet */ 220 { 0x0102, 0x01 }, /* Enable outputs */ 221 { 0x013F, 0x00 }, /* Not in datasheet */ 222 { 0x0140, 0x00 }, /* Not in datasheet */ 223 { 0x0141, 0x40 }, /* OUT LOS */ 224 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/ 225 { 0x0203, 0x00 }, 226 { 0x0204, 0x00 }, 227 { 0x0205, 0x00 }, 228 { 0x0206, 0x00 }, /* PXAXB (2^x) */ 229 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */ 230 { 0x0209, 0x00 }, 231 { 0x020A, 0x00 }, 232 { 0x020B, 0x00 }, 233 { 0x020C, 0x00 }, 234 { 0x020D, 0x00 }, 235 { 0x020E, 0x00 }, 236 { 0x020F, 0x00 }, 237 { 0x0210, 0x00 }, 238 { 0x0211, 0x00 }, 239 { 0x0212, 0x00 }, 240 { 0x0213, 0x00 }, 241 { 0x0214, 0x00 }, 242 { 0x0215, 0x00 }, 243 { 0x0216, 0x00 }, 244 { 0x0217, 0x00 }, 245 { 0x0218, 0x00 }, 246 { 0x0219, 0x00 }, 247 { 0x021A, 0x00 }, 248 { 0x021B, 0x00 }, 249 { 0x021C, 0x00 }, 250 { 0x021D, 0x00 }, 251 { 0x021E, 0x00 }, 252 { 0x021F, 0x00 }, 253 { 0x0220, 0x00 }, 254 { 0x0221, 0x00 }, 255 { 0x0222, 0x00 }, 256 { 0x0223, 0x00 }, 257 { 0x0224, 0x00 }, 258 { 0x0225, 0x00 }, 259 { 0x0226, 0x00 }, 260 { 0x0227, 0x00 }, 261 { 0x0228, 0x00 }, 262 { 0x0229, 0x00 }, 263 { 0x022A, 0x00 }, 264 { 0x022B, 0x00 }, 265 { 0x022C, 0x00 }, 266 { 0x022D, 0x00 }, 267 { 0x022E, 0x00 }, 268 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */ 269 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */ 270 { 0x026C, 0x00 }, 271 { 0x026D, 0x00 }, 272 { 0x026E, 0x00 }, 273 { 0x026F, 0x00 }, 274 { 0x0270, 0x00 }, 275 { 0x0271, 0x00 }, 276 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */ 277 { 0x0339, 0x1F }, /* N_FSTEP_MSK */ 278 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */ 279 { 0x033C, 0x00 }, 280 { 0x033D, 0x00 }, 281 { 0x033E, 0x00 }, 282 { 0x033F, 0x00 }, 283 { 0x0340, 0x00 }, 284 { 0x0341, 0x00 }, 285 { 0x0342, 0x00 }, 286 { 0x0343, 0x00 }, 287 { 0x0344, 0x00 }, 288 { 0x0345, 0x00 }, 289 { 0x0346, 0x00 }, 290 { 0x0347, 0x00 }, 291 { 0x0348, 0x00 }, 292 { 0x0349, 0x00 }, 293 { 0x034A, 0x00 }, 294 { 0x034B, 0x00 }, 295 { 0x034C, 0x00 }, 296 { 0x034D, 0x00 }, 297 { 0x034E, 0x00 }, 298 { 0x034F, 0x00 }, 299 { 0x0350, 0x00 }, 300 { 0x0351, 0x00 }, 301 { 0x0352, 0x00 }, 302 { 0x0353, 0x00 }, 303 { 0x0354, 0x00 }, 304 { 0x0355, 0x00 }, 305 { 0x0356, 0x00 }, 306 { 0x0357, 0x00 }, 307 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */ 308 { 0x0359, 0x00 }, /* Nx_DELAY */ 309 { 0x035A, 0x00 }, 310 { 0x035B, 0x00 }, 311 { 0x035C, 0x00 }, 312 { 0x035D, 0x00 }, 313 { 0x035E, 0x00 }, 314 { 0x035F, 0x00 }, 315 { 0x0360, 0x00 }, 316 { 0x0361, 0x00 }, 317 { 0x0362, 0x00 }, /* Nx_DELAY end */ 318 { 0x0802, 0x00 }, /* Not in datasheet */ 319 { 0x0803, 0x00 }, /* Not in datasheet */ 320 { 0x0804, 0x00 }, /* Not in datasheet */ 321 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */ 322 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */ 323 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */ 324 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */ 325 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */ 326 { 0x0A02, 0x00 }, /* Not in datasheet */ 327 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */ 328 }; 329 330 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */ 331 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, 332 u64 *val1, u32 *val2) 333 { 334 int err; 335 u8 r[10]; 336 337 err = regmap_bulk_read(regmap, reg, r, 10); 338 if (err < 0) 339 return err; 340 341 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) | 342 (get_unaligned_le32(r)); 343 *val2 = get_unaligned_le32(&r[6]); 344 345 return 0; 346 } 347 348 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, 349 u64 n_num, u32 n_den) 350 { 351 u8 r[10]; 352 353 /* Shift left as far as possible without overflowing */ 354 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) { 355 n_num <<= 1; 356 n_den <<= 1; 357 } 358 359 /* 44 bits (6 bytes) numerator */ 360 put_unaligned_le32(n_num, r); 361 r[4] = (n_num >> 32) & 0xff; 362 r[5] = (n_num >> 40) & 0x0f; 363 /* 32 bits denominator */ 364 put_unaligned_le32(n_den, &r[6]); 365 366 /* Program the fraction */ 367 return regmap_bulk_write(regmap, reg, r, sizeof(r)); 368 } 369 370 /* VCO, we assume it runs at a constant frequency */ 371 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw, 372 unsigned long parent_rate) 373 { 374 struct clk_si5341 *data = to_clk_si5341(hw); 375 int err; 376 u64 res; 377 u64 m_num; 378 u32 m_den; 379 unsigned int shift; 380 381 /* Assume that PDIV is not being used, just read the PLL setting */ 382 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, 383 &m_num, &m_den); 384 if (err < 0) 385 return 0; 386 387 if (!m_num || !m_den) 388 return 0; 389 390 /* 391 * Though m_num is 64-bit, only the upper bits are actually used. While 392 * calculating m_num and m_den, they are shifted as far as possible to 393 * the left. To avoid 96-bit division here, we just shift them back so 394 * we can do with just 64 bits. 395 */ 396 shift = 0; 397 res = m_num; 398 while (res & 0xffff00000000ULL) { 399 ++shift; 400 res >>= 1; 401 } 402 res *= parent_rate; 403 do_div(res, (m_den >> shift)); 404 405 /* We cannot return the actual frequency in 32 bit, store it locally */ 406 data->freq_vco = res; 407 408 /* Report kHz since the value is out of range */ 409 do_div(res, 1000); 410 411 return (unsigned long)res; 412 } 413 414 static int si5341_clk_get_selected_input(struct clk_si5341 *data) 415 { 416 int err; 417 u32 val; 418 419 err = regmap_read(data->regmap, SI5341_IN_SEL, &val); 420 if (err < 0) 421 return err; 422 423 return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT; 424 } 425 426 static u8 si5341_clk_get_parent(struct clk_hw *hw) 427 { 428 struct clk_si5341 *data = to_clk_si5341(hw); 429 int res = si5341_clk_get_selected_input(data); 430 431 if (res < 0) 432 return 0; /* Apparently we cannot report errors */ 433 434 return res; 435 } 436 437 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) 438 { 439 int err; 440 u8 val; 441 442 val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK; 443 /* Enable register-based input selection */ 444 val |= SI5341_IN_SEL_REGCTRL; 445 446 err = regmap_update_bits(data->regmap, 447 SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val); 448 if (err < 0) 449 return err; 450 451 if (index < 3) { 452 /* Enable input buffer for selected input */ 453 err = regmap_update_bits(data->regmap, 454 SI5341_IN_EN, 0x07, BIT(index)); 455 if (err < 0) 456 return err; 457 458 /* Enables the input to phase detector */ 459 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 460 0x7 << SI5341_INX_TO_PFD_SHIFT, 461 BIT(index + SI5341_INX_TO_PFD_SHIFT)); 462 if (err < 0) 463 return err; 464 465 /* Power down XTAL oscillator and buffer */ 466 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 467 SI5341_XAXB_CFG_PDNB, 0); 468 if (err < 0) 469 return err; 470 471 /* 472 * Set the P divider to "1". There's no explanation in the 473 * datasheet of these registers, but the clockbuilder software 474 * programs a "1" when the input is being used. 475 */ 476 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); 477 if (err < 0) 478 return err; 479 480 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); 481 if (err < 0) 482 return err; 483 484 /* Set update PDIV bit */ 485 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); 486 if (err < 0) 487 return err; 488 } else { 489 /* Disable all input buffers */ 490 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); 491 if (err < 0) 492 return err; 493 494 /* Disable input to phase detector */ 495 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, 496 0x7 << SI5341_INX_TO_PFD_SHIFT, 0); 497 if (err < 0) 498 return err; 499 500 /* Power up XTAL oscillator and buffer */ 501 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, 502 SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB); 503 if (err < 0) 504 return err; 505 } 506 507 return 0; 508 } 509 510 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index) 511 { 512 struct clk_si5341 *data = to_clk_si5341(hw); 513 514 return si5341_clk_reparent(data, index); 515 } 516 517 static const struct clk_ops si5341_clk_ops = { 518 .set_parent = si5341_clk_set_parent, 519 .get_parent = si5341_clk_get_parent, 520 .recalc_rate = si5341_clk_recalc_rate, 521 }; 522 523 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */ 524 525 /* The synthesizer is on if all power and enable bits are set */ 526 static int si5341_synth_clk_is_on(struct clk_hw *hw) 527 { 528 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 529 int err; 530 u32 val; 531 u8 index = synth->index; 532 533 err = regmap_read(synth->data->regmap, 534 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val); 535 if (err < 0) 536 return 0; 537 538 if (!(val & BIT(index))) 539 return 0; 540 541 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); 542 if (err < 0) 543 return 0; 544 545 if (!(val & BIT(index))) 546 return 0; 547 548 /* This bit must be 0 for the synthesizer to receive clock input */ 549 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); 550 if (err < 0) 551 return 0; 552 553 return !(val & BIT(index)); 554 } 555 556 static void si5341_synth_clk_unprepare(struct clk_hw *hw) 557 { 558 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 559 u8 index = synth->index; /* In range 0..5 */ 560 u8 mask = BIT(index); 561 562 /* Disable output */ 563 regmap_update_bits(synth->data->regmap, 564 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); 565 /* Power down */ 566 regmap_update_bits(synth->data->regmap, 567 SI5341_SYNTH_N_PDNB, mask, 0); 568 /* Disable clock input to synth (set to 1 to disable) */ 569 regmap_update_bits(synth->data->regmap, 570 SI5341_SYNTH_N_CLK_DIS, mask, mask); 571 } 572 573 static int si5341_synth_clk_prepare(struct clk_hw *hw) 574 { 575 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 576 int err; 577 u8 index = synth->index; 578 u8 mask = BIT(index); 579 580 /* Power up */ 581 err = regmap_update_bits(synth->data->regmap, 582 SI5341_SYNTH_N_PDNB, mask, mask); 583 if (err < 0) 584 return err; 585 586 /* Enable clock input to synth (set bit to 0 to enable) */ 587 err = regmap_update_bits(synth->data->regmap, 588 SI5341_SYNTH_N_CLK_DIS, mask, 0); 589 if (err < 0) 590 return err; 591 592 /* Enable output */ 593 return regmap_update_bits(synth->data->regmap, 594 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); 595 } 596 597 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */ 598 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, 599 unsigned long parent_rate) 600 { 601 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 602 u64 f; 603 u64 n_num; 604 u32 n_den; 605 int err; 606 607 err = si5341_decode_44_32(synth->data->regmap, 608 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); 609 if (err < 0) 610 return err; 611 612 /* 613 * n_num and n_den are shifted left as much as possible, so to prevent 614 * overflow in 64-bit math, we shift n_den 4 bits to the right 615 */ 616 f = synth->data->freq_vco; 617 f *= n_den >> 4; 618 619 /* Now we need to to 64-bit division: f/n_num */ 620 /* And compensate for the 4 bits we dropped */ 621 f = div64_u64(f, (n_num >> 4)); 622 623 return f; 624 } 625 626 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate, 627 unsigned long *parent_rate) 628 { 629 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 630 u64 f; 631 632 /* The synthesizer accuracy is such that anything in range will work */ 633 f = synth->data->freq_vco; 634 do_div(f, SI5341_SYNTH_N_MAX); 635 if (rate < f) 636 return f; 637 638 f = synth->data->freq_vco; 639 do_div(f, SI5341_SYNTH_N_MIN); 640 if (rate > f) 641 return f; 642 643 return rate; 644 } 645 646 static int si5341_synth_program(struct clk_si5341_synth *synth, 647 u64 n_num, u32 n_den, bool is_integer) 648 { 649 int err; 650 u8 index = synth->index; 651 652 err = si5341_encode_44_32(synth->data->regmap, 653 SI5341_SYNTH_N_NUM(index), n_num, n_den); 654 655 err = regmap_update_bits(synth->data->regmap, 656 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0); 657 if (err < 0) 658 return err; 659 660 return regmap_write(synth->data->regmap, 661 SI5341_SYNTH_N_UPD(index), 0x01); 662 } 663 664 665 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate, 666 unsigned long parent_rate) 667 { 668 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw); 669 u64 n_num; 670 u32 n_den; 671 u32 r; 672 u32 g; 673 bool is_integer; 674 675 n_num = synth->data->freq_vco; 676 677 /* see if there's an integer solution */ 678 r = do_div(n_num, rate); 679 is_integer = (r == 0); 680 if (is_integer) { 681 /* Integer divider equal to n_num */ 682 n_den = 1; 683 } else { 684 /* Calculate a fractional solution */ 685 g = gcd(r, rate); 686 n_den = rate / g; 687 n_num *= n_den; 688 n_num += r / g; 689 } 690 691 dev_dbg(&synth->data->i2c_client->dev, 692 "%s(%u): n=0x%llx d=0x%x %s\n", __func__, 693 synth->index, n_num, n_den, 694 is_integer ? "int" : "frac"); 695 696 return si5341_synth_program(synth, n_num, n_den, is_integer); 697 } 698 699 static const struct clk_ops si5341_synth_clk_ops = { 700 .is_prepared = si5341_synth_clk_is_on, 701 .prepare = si5341_synth_clk_prepare, 702 .unprepare = si5341_synth_clk_unprepare, 703 .recalc_rate = si5341_synth_clk_recalc_rate, 704 .round_rate = si5341_synth_clk_round_rate, 705 .set_rate = si5341_synth_clk_set_rate, 706 }; 707 708 static int si5341_output_clk_is_on(struct clk_hw *hw) 709 { 710 struct clk_si5341_output *output = to_clk_si5341_output(hw); 711 int err; 712 u32 val; 713 714 err = regmap_read(output->data->regmap, 715 SI5341_OUT_CONFIG(output), &val); 716 if (err < 0) 717 return err; 718 719 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */ 720 return (val & 0x03) == SI5341_OUT_CFG_OE; 721 } 722 723 /* Disables and then powers down the output */ 724 static void si5341_output_clk_unprepare(struct clk_hw *hw) 725 { 726 struct clk_si5341_output *output = to_clk_si5341_output(hw); 727 728 regmap_update_bits(output->data->regmap, 729 SI5341_OUT_CONFIG(output), 730 SI5341_OUT_CFG_OE, 0); 731 regmap_update_bits(output->data->regmap, 732 SI5341_OUT_CONFIG(output), 733 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN); 734 } 735 736 /* Powers up and then enables the output */ 737 static int si5341_output_clk_prepare(struct clk_hw *hw) 738 { 739 struct clk_si5341_output *output = to_clk_si5341_output(hw); 740 int err; 741 742 err = regmap_update_bits(output->data->regmap, 743 SI5341_OUT_CONFIG(output), 744 SI5341_OUT_CFG_PDN, 0); 745 if (err < 0) 746 return err; 747 748 return regmap_update_bits(output->data->regmap, 749 SI5341_OUT_CONFIG(output), 750 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE); 751 } 752 753 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, 754 unsigned long parent_rate) 755 { 756 struct clk_si5341_output *output = to_clk_si5341_output(hw); 757 int err; 758 u32 val; 759 u32 r_divider; 760 u8 r[3]; 761 762 err = regmap_bulk_read(output->data->regmap, 763 SI5341_OUT_R_REG(output), r, 3); 764 if (err < 0) 765 return err; 766 767 /* Calculate value as 24-bit integer*/ 768 r_divider = r[2] << 16 | r[1] << 8 | r[0]; 769 770 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */ 771 if (!r_divider) 772 return 0; 773 774 /* Divider is 2*(Rx_REG+1) */ 775 r_divider += 1; 776 r_divider <<= 1; 777 778 err = regmap_read(output->data->regmap, 779 SI5341_OUT_CONFIG(output), &val); 780 if (err < 0) 781 return err; 782 783 if (val & SI5341_OUT_CFG_RDIV_FORCE2) 784 r_divider = 2; 785 786 return parent_rate / r_divider; 787 } 788 789 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate, 790 unsigned long *parent_rate) 791 { 792 unsigned long r; 793 794 r = *parent_rate >> 1; 795 796 /* If rate is an even divisor, no changes to parent required */ 797 if (r && !(r % rate)) 798 return (long)rate; 799 800 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { 801 if (rate > 200000000) { 802 /* minimum r-divider is 2 */ 803 r = 2; 804 } else { 805 /* Take a parent frequency near 400 MHz */ 806 r = (400000000u / rate) & ~1; 807 } 808 *parent_rate = r * rate; 809 } else { 810 /* We cannot change our parent's rate, report what we can do */ 811 r /= rate; 812 rate = *parent_rate / (r << 1); 813 } 814 815 return rate; 816 } 817 818 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, 819 unsigned long parent_rate) 820 { 821 struct clk_si5341_output *output = to_clk_si5341_output(hw); 822 /* Frequency divider is (r_div + 1) * 2 */ 823 u32 r_div = (parent_rate / rate) >> 1; 824 int err; 825 u8 r[3]; 826 827 if (r_div <= 1) 828 r_div = 0; 829 else if (r_div >= BIT(24)) 830 r_div = BIT(24) - 1; 831 else 832 --r_div; 833 834 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */ 835 err = regmap_update_bits(output->data->regmap, 836 SI5341_OUT_CONFIG(output), 837 SI5341_OUT_CFG_RDIV_FORCE2, 838 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0); 839 if (err < 0) 840 return err; 841 842 /* Always write Rx_REG, because a zero value disables the divider */ 843 r[0] = r_div ? (r_div & 0xff) : 1; 844 r[1] = (r_div >> 8) & 0xff; 845 r[2] = (r_div >> 16) & 0xff; 846 err = regmap_bulk_write(output->data->regmap, 847 SI5341_OUT_R_REG(output), r, 3); 848 849 return 0; 850 } 851 852 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) 853 { 854 return regmap_update_bits(output->data->regmap, 855 SI5341_OUT_MUX_SEL(output), 0x07, index); 856 } 857 858 static int si5341_output_set_parent(struct clk_hw *hw, u8 index) 859 { 860 struct clk_si5341_output *output = to_clk_si5341_output(hw); 861 862 if (index >= output->data->num_synth) 863 return -EINVAL; 864 865 return si5341_output_reparent(output, index); 866 } 867 868 static u8 si5341_output_get_parent(struct clk_hw *hw) 869 { 870 struct clk_si5341_output *output = to_clk_si5341_output(hw); 871 int err; 872 u32 val; 873 874 err = regmap_read(output->data->regmap, 875 SI5341_OUT_MUX_SEL(output), &val); 876 877 return val & 0x7; 878 } 879 880 static const struct clk_ops si5341_output_clk_ops = { 881 .is_prepared = si5341_output_clk_is_on, 882 .prepare = si5341_output_clk_prepare, 883 .unprepare = si5341_output_clk_unprepare, 884 .recalc_rate = si5341_output_clk_recalc_rate, 885 .round_rate = si5341_output_clk_round_rate, 886 .set_rate = si5341_output_clk_set_rate, 887 .set_parent = si5341_output_set_parent, 888 .get_parent = si5341_output_get_parent, 889 }; 890 891 /* 892 * The chip can be bought in a pre-programmed version, or one can program the 893 * NVM in the chip to boot up in a preset mode. This routine tries to determine 894 * if that's the case, or if we need to reset and program everything from 895 * scratch. Returns negative error, or true/false. 896 */ 897 static int si5341_is_programmed_already(struct clk_si5341 *data) 898 { 899 int err; 900 u8 r[4]; 901 902 /* Read the PLL divider value, it must have a non-zero value */ 903 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, 904 r, ARRAY_SIZE(r)); 905 if (err < 0) 906 return err; 907 908 return !!get_unaligned_le32(r); 909 } 910 911 static struct clk_hw * 912 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data) 913 { 914 struct clk_si5341 *data = _data; 915 unsigned int idx = clkspec->args[1]; 916 unsigned int group = clkspec->args[0]; 917 918 switch (group) { 919 case 0: 920 if (idx >= data->num_outputs) { 921 dev_err(&data->i2c_client->dev, 922 "invalid output index %u\n", idx); 923 return ERR_PTR(-EINVAL); 924 } 925 return &data->clk[idx].hw; 926 case 1: 927 if (idx >= data->num_synth) { 928 dev_err(&data->i2c_client->dev, 929 "invalid synthesizer index %u\n", idx); 930 return ERR_PTR(-EINVAL); 931 } 932 return &data->synth[idx].hw; 933 case 2: 934 if (idx > 0) { 935 dev_err(&data->i2c_client->dev, 936 "invalid PLL index %u\n", idx); 937 return ERR_PTR(-EINVAL); 938 } 939 return &data->hw; 940 default: 941 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); 942 return ERR_PTR(-EINVAL); 943 } 944 } 945 946 static int si5341_probe_chip_id(struct clk_si5341 *data) 947 { 948 int err; 949 u8 reg[4]; 950 u16 model; 951 952 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, 953 ARRAY_SIZE(reg)); 954 if (err < 0) { 955 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); 956 return err; 957 } 958 959 model = get_unaligned_le16(reg); 960 961 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", 962 model, reg[2], reg[3]); 963 964 switch (model) { 965 case 0x5340: 966 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; 967 data->num_synth = SI5340_NUM_SYNTH; 968 data->reg_output_offset = si5340_reg_output_offset; 969 data->reg_rdiv_offset = si5340_reg_rdiv_offset; 970 break; 971 case 0x5341: 972 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; 973 data->num_synth = SI5341_NUM_SYNTH; 974 data->reg_output_offset = si5341_reg_output_offset; 975 data->reg_rdiv_offset = si5341_reg_rdiv_offset; 976 break; 977 default: 978 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", 979 model); 980 return -EINVAL; 981 } 982 983 return 0; 984 } 985 986 /* Read active settings into the regmap cache for later reference */ 987 static int si5341_read_settings(struct clk_si5341 *data) 988 { 989 int err; 990 u8 i; 991 u8 r[10]; 992 993 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); 994 if (err < 0) 995 return err; 996 997 err = regmap_bulk_read(data->regmap, 998 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3); 999 if (err < 0) 1000 return err; 1001 1002 err = regmap_bulk_read(data->regmap, 1003 SI5341_SYNTH_N_CLK_DIS, r, 1); 1004 if (err < 0) 1005 return err; 1006 1007 for (i = 0; i < data->num_synth; ++i) { 1008 err = regmap_bulk_read(data->regmap, 1009 SI5341_SYNTH_N_NUM(i), r, 10); 1010 if (err < 0) 1011 return err; 1012 } 1013 1014 for (i = 0; i < data->num_outputs; ++i) { 1015 err = regmap_bulk_read(data->regmap, 1016 data->reg_output_offset[i], r, 4); 1017 if (err < 0) 1018 return err; 1019 1020 err = regmap_bulk_read(data->regmap, 1021 data->reg_rdiv_offset[i], r, 3); 1022 if (err < 0) 1023 return err; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static int si5341_write_multiple(struct clk_si5341 *data, 1030 const struct si5341_reg_default *values, unsigned int num_values) 1031 { 1032 unsigned int i; 1033 int res; 1034 1035 for (i = 0; i < num_values; ++i) { 1036 res = regmap_write(data->regmap, 1037 values[i].address, values[i].value); 1038 if (res < 0) { 1039 dev_err(&data->i2c_client->dev, 1040 "Failed to write %#x:%#x\n", 1041 values[i].address, values[i].value); 1042 return res; 1043 } 1044 } 1045 1046 return 0; 1047 } 1048 1049 static const struct si5341_reg_default si5341_preamble[] = { 1050 { 0x0B25, 0x00 }, 1051 { 0x0502, 0x01 }, 1052 { 0x0505, 0x03 }, 1053 { 0x0957, 0x1F }, 1054 { 0x0B4E, 0x1A }, 1055 }; 1056 1057 static int si5341_send_preamble(struct clk_si5341 *data) 1058 { 1059 int res; 1060 u32 revision; 1061 1062 /* For revision 2 and up, the values are slightly different */ 1063 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1064 if (res < 0) 1065 return res; 1066 1067 /* Write "preamble" as specified by datasheet */ 1068 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); 1069 if (res < 0) 1070 return res; 1071 res = si5341_write_multiple(data, 1072 si5341_preamble, ARRAY_SIZE(si5341_preamble)); 1073 if (res < 0) 1074 return res; 1075 1076 /* Datasheet specifies a 300ms wait after sending the preamble */ 1077 msleep(300); 1078 1079 return 0; 1080 } 1081 1082 /* Perform a soft reset and write post-amble */ 1083 static int si5341_finalize_defaults(struct clk_si5341 *data) 1084 { 1085 int res; 1086 u32 revision; 1087 1088 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); 1089 if (res < 0) 1090 return res; 1091 1092 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); 1093 1094 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); 1095 if (res < 0) 1096 return res; 1097 1098 /* Datasheet does not explain these nameless registers */ 1099 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); 1100 if (res < 0) 1101 return res; 1102 res = regmap_write(data->regmap, 0x0B25, 0x02); 1103 if (res < 0) 1104 return res; 1105 1106 return 0; 1107 } 1108 1109 1110 static const struct regmap_range si5341_regmap_volatile_range[] = { 1111 regmap_reg_range(0x000C, 0x0012), /* Status */ 1112 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */ 1113 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */ 1114 /* Update bits for P divider and synth config */ 1115 regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD), 1116 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)), 1117 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)), 1118 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)), 1119 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)), 1120 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)), 1121 }; 1122 1123 static const struct regmap_access_table si5341_regmap_volatile = { 1124 .yes_ranges = si5341_regmap_volatile_range, 1125 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range), 1126 }; 1127 1128 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */ 1129 static const struct regmap_range_cfg si5341_regmap_ranges[] = { 1130 { 1131 .range_min = 0, 1132 .range_max = SI5341_REGISTER_MAX, 1133 .selector_reg = SI5341_PAGE, 1134 .selector_mask = 0xff, 1135 .selector_shift = 0, 1136 .window_start = 0, 1137 .window_len = 256, 1138 }, 1139 }; 1140 1141 static const struct regmap_config si5341_regmap_config = { 1142 .reg_bits = 8, 1143 .val_bits = 8, 1144 .cache_type = REGCACHE_RBTREE, 1145 .ranges = si5341_regmap_ranges, 1146 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges), 1147 .max_register = SI5341_REGISTER_MAX, 1148 .volatile_table = &si5341_regmap_volatile, 1149 }; 1150 1151 static int si5341_dt_parse_dt(struct i2c_client *client, 1152 struct clk_si5341_output_config *config) 1153 { 1154 struct device_node *child; 1155 struct device_node *np = client->dev.of_node; 1156 u32 num; 1157 u32 val; 1158 1159 memset(config, 0, sizeof(struct clk_si5341_output_config) * 1160 SI5341_MAX_NUM_OUTPUTS); 1161 1162 for_each_child_of_node(np, child) { 1163 if (of_property_read_u32(child, "reg", &num)) { 1164 dev_err(&client->dev, "missing reg property of %s\n", 1165 child->name); 1166 goto put_child; 1167 } 1168 1169 if (num >= SI5341_MAX_NUM_OUTPUTS) { 1170 dev_err(&client->dev, "invalid clkout %d\n", num); 1171 goto put_child; 1172 } 1173 1174 if (!of_property_read_u32(child, "silabs,format", &val)) { 1175 /* Set cm and ampl conservatively to 3v3 settings */ 1176 switch (val) { 1177 case 1: /* normal differential */ 1178 config[num].out_cm_ampl_bits = 0x33; 1179 break; 1180 case 2: /* low-power differential */ 1181 config[num].out_cm_ampl_bits = 0x13; 1182 break; 1183 case 4: /* LVCMOS */ 1184 config[num].out_cm_ampl_bits = 0x33; 1185 /* Set SI recommended impedance for LVCMOS */ 1186 config[num].out_format_drv_bits |= 0xc0; 1187 break; 1188 default: 1189 dev_err(&client->dev, 1190 "invalid silabs,format %u for %u\n", 1191 val, num); 1192 goto put_child; 1193 } 1194 config[num].out_format_drv_bits &= ~0x07; 1195 config[num].out_format_drv_bits |= val & 0x07; 1196 /* Always enable the SYNC feature */ 1197 config[num].out_format_drv_bits |= 0x08; 1198 } 1199 1200 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { 1201 if (val > 0xf) { 1202 dev_err(&client->dev, 1203 "invalid silabs,common-mode %u\n", 1204 val); 1205 goto put_child; 1206 } 1207 config[num].out_cm_ampl_bits &= 0xf0; 1208 config[num].out_cm_ampl_bits |= val & 0x0f; 1209 } 1210 1211 if (!of_property_read_u32(child, "silabs,amplitude", &val)) { 1212 if (val > 0xf) { 1213 dev_err(&client->dev, 1214 "invalid silabs,amplitude %u\n", 1215 val); 1216 goto put_child; 1217 } 1218 config[num].out_cm_ampl_bits &= 0x0f; 1219 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0; 1220 } 1221 1222 if (of_property_read_bool(child, "silabs,disable-high")) 1223 config[num].out_format_drv_bits |= 0x10; 1224 1225 config[num].synth_master = 1226 of_property_read_bool(child, "silabs,synth-master"); 1227 1228 config[num].always_on = 1229 of_property_read_bool(child, "always-on"); 1230 } 1231 1232 return 0; 1233 1234 put_child: 1235 of_node_put(child); 1236 return -EINVAL; 1237 } 1238 1239 /* 1240 * If not pre-configured, calculate and set the PLL configuration manually. 1241 * For low-jitter performance, the PLL should be set such that the synthesizers 1242 * only need integer division. 1243 * Without any user guidance, we'll set the PLL to 14GHz, which still allows 1244 * the chip to generate any frequency on its outputs, but jitter performance 1245 * may be sub-optimal. 1246 */ 1247 static int si5341_initialize_pll(struct clk_si5341 *data) 1248 { 1249 struct device_node *np = data->i2c_client->dev.of_node; 1250 u32 m_num = 0; 1251 u32 m_den = 0; 1252 int sel; 1253 1254 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { 1255 dev_err(&data->i2c_client->dev, 1256 "PLL configuration requires silabs,pll-m-num\n"); 1257 } 1258 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { 1259 dev_err(&data->i2c_client->dev, 1260 "PLL configuration requires silabs,pll-m-den\n"); 1261 } 1262 1263 if (!m_num || !m_den) { 1264 dev_err(&data->i2c_client->dev, 1265 "PLL configuration invalid, assume 14GHz\n"); 1266 sel = si5341_clk_get_selected_input(data); 1267 if (sel < 0) 1268 return sel; 1269 1270 m_den = clk_get_rate(data->input_clk[sel]) / 10; 1271 m_num = 1400000000; 1272 } 1273 1274 return si5341_encode_44_32(data->regmap, 1275 SI5341_PLL_M_NUM, m_num, m_den); 1276 } 1277 1278 static int si5341_clk_select_active_input(struct clk_si5341 *data) 1279 { 1280 int res; 1281 int err; 1282 int i; 1283 1284 res = si5341_clk_get_selected_input(data); 1285 if (res < 0) 1286 return res; 1287 1288 /* If the current register setting is invalid, pick the first input */ 1289 if (!data->input_clk[res]) { 1290 dev_dbg(&data->i2c_client->dev, 1291 "Input %d not connected, rerouting\n", res); 1292 res = -ENODEV; 1293 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1294 if (data->input_clk[i]) { 1295 res = i; 1296 break; 1297 } 1298 } 1299 if (res < 0) { 1300 dev_err(&data->i2c_client->dev, 1301 "No clock input available\n"); 1302 return res; 1303 } 1304 } 1305 1306 /* Make sure the selected clock is also enabled and routed */ 1307 err = si5341_clk_reparent(data, res); 1308 if (err < 0) 1309 return err; 1310 1311 err = clk_prepare_enable(data->input_clk[res]); 1312 if (err < 0) 1313 return err; 1314 1315 return res; 1316 } 1317 1318 static int si5341_probe(struct i2c_client *client, 1319 const struct i2c_device_id *id) 1320 { 1321 struct clk_si5341 *data; 1322 struct clk_init_data init; 1323 struct clk *input; 1324 const char *root_clock_name; 1325 const char *synth_clock_names[SI5341_NUM_SYNTH]; 1326 int err; 1327 unsigned int i; 1328 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS]; 1329 bool initialization_required; 1330 1331 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 1332 if (!data) 1333 return -ENOMEM; 1334 1335 data->i2c_client = client; 1336 1337 for (i = 0; i < SI5341_NUM_INPUTS; ++i) { 1338 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); 1339 if (IS_ERR(input)) { 1340 if (PTR_ERR(input) == -EPROBE_DEFER) 1341 return -EPROBE_DEFER; 1342 data->input_clk_name[i] = si5341_input_clock_names[i]; 1343 } else { 1344 data->input_clk[i] = input; 1345 data->input_clk_name[i] = __clk_get_name(input); 1346 } 1347 } 1348 1349 err = si5341_dt_parse_dt(client, config); 1350 if (err) 1351 return err; 1352 1353 if (of_property_read_string(client->dev.of_node, "clock-output-names", 1354 &init.name)) 1355 init.name = client->dev.of_node->name; 1356 root_clock_name = init.name; 1357 1358 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); 1359 if (IS_ERR(data->regmap)) 1360 return PTR_ERR(data->regmap); 1361 1362 i2c_set_clientdata(client, data); 1363 1364 err = si5341_probe_chip_id(data); 1365 if (err < 0) 1366 return err; 1367 1368 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { 1369 initialization_required = true; 1370 } else { 1371 err = si5341_is_programmed_already(data); 1372 if (err < 0) 1373 return err; 1374 1375 initialization_required = !err; 1376 } 1377 1378 if (initialization_required) { 1379 /* Populate the regmap cache in preparation for "cache only" */ 1380 err = si5341_read_settings(data); 1381 if (err < 0) 1382 return err; 1383 1384 err = si5341_send_preamble(data); 1385 if (err < 0) 1386 return err; 1387 1388 /* 1389 * We intend to send all 'final' register values in a single 1390 * transaction. So cache all register writes until we're done 1391 * configuring. 1392 */ 1393 regcache_cache_only(data->regmap, true); 1394 1395 /* Write the configuration pairs from the firmware blob */ 1396 err = si5341_write_multiple(data, si5341_reg_defaults, 1397 ARRAY_SIZE(si5341_reg_defaults)); 1398 if (err < 0) 1399 return err; 1400 } 1401 1402 /* Input must be up and running at this point */ 1403 err = si5341_clk_select_active_input(data); 1404 if (err < 0) 1405 return err; 1406 1407 if (initialization_required) { 1408 /* PLL configuration is required */ 1409 err = si5341_initialize_pll(data); 1410 if (err < 0) 1411 return err; 1412 } 1413 1414 /* Register the PLL */ 1415 init.parent_names = data->input_clk_name; 1416 init.num_parents = SI5341_NUM_INPUTS; 1417 init.ops = &si5341_clk_ops; 1418 init.flags = 0; 1419 data->hw.init = &init; 1420 1421 err = devm_clk_hw_register(&client->dev, &data->hw); 1422 if (err) { 1423 dev_err(&client->dev, "clock registration failed\n"); 1424 return err; 1425 } 1426 1427 init.num_parents = 1; 1428 init.parent_names = &root_clock_name; 1429 init.ops = &si5341_synth_clk_ops; 1430 for (i = 0; i < data->num_synth; ++i) { 1431 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, 1432 "%s.N%u", client->dev.of_node->name, i); 1433 init.name = synth_clock_names[i]; 1434 data->synth[i].index = i; 1435 data->synth[i].data = data; 1436 data->synth[i].hw.init = &init; 1437 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); 1438 if (err) { 1439 dev_err(&client->dev, 1440 "synth N%u registration failed\n", i); 1441 } 1442 } 1443 1444 init.num_parents = data->num_synth; 1445 init.parent_names = synth_clock_names; 1446 init.ops = &si5341_output_clk_ops; 1447 for (i = 0; i < data->num_outputs; ++i) { 1448 init.name = kasprintf(GFP_KERNEL, "%s.%d", 1449 client->dev.of_node->name, i); 1450 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0; 1451 data->clk[i].index = i; 1452 data->clk[i].data = data; 1453 data->clk[i].hw.init = &init; 1454 if (config[i].out_format_drv_bits & 0x07) { 1455 regmap_write(data->regmap, 1456 SI5341_OUT_FORMAT(&data->clk[i]), 1457 config[i].out_format_drv_bits); 1458 regmap_write(data->regmap, 1459 SI5341_OUT_CM(&data->clk[i]), 1460 config[i].out_cm_ampl_bits); 1461 } 1462 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 1463 kfree(init.name); /* clock framework made a copy of the name */ 1464 if (err) { 1465 dev_err(&client->dev, 1466 "output %u registration failed\n", i); 1467 return err; 1468 } 1469 if (config[i].always_on) 1470 clk_prepare(data->clk[i].hw.clk); 1471 } 1472 1473 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get, 1474 data); 1475 if (err) { 1476 dev_err(&client->dev, "unable to add clk provider\n"); 1477 return err; 1478 } 1479 1480 if (initialization_required) { 1481 /* Synchronize */ 1482 regcache_cache_only(data->regmap, false); 1483 err = regcache_sync(data->regmap); 1484 if (err < 0) 1485 return err; 1486 1487 err = si5341_finalize_defaults(data); 1488 if (err < 0) 1489 return err; 1490 } 1491 1492 /* Free the names, clk framework makes copies */ 1493 for (i = 0; i < data->num_synth; ++i) 1494 devm_kfree(&client->dev, (void *)synth_clock_names[i]); 1495 1496 return 0; 1497 } 1498 1499 static const struct i2c_device_id si5341_id[] = { 1500 { "si5340", 0 }, 1501 { "si5341", 1 }, 1502 { } 1503 }; 1504 MODULE_DEVICE_TABLE(i2c, si5341_id); 1505 1506 static const struct of_device_id clk_si5341_of_match[] = { 1507 { .compatible = "silabs,si5340" }, 1508 { .compatible = "silabs,si5341" }, 1509 { } 1510 }; 1511 MODULE_DEVICE_TABLE(of, clk_si5341_of_match); 1512 1513 static struct i2c_driver si5341_driver = { 1514 .driver = { 1515 .name = "si5341", 1516 .of_match_table = clk_si5341_of_match, 1517 }, 1518 .probe = si5341_probe, 1519 .id_table = si5341_id, 1520 }; 1521 module_i2c_driver(si5341_driver); 1522 1523 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 1524 MODULE_DESCRIPTION("Si5341 driver"); 1525 MODULE_LICENSE("GPL"); 1526