1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Renesas 9-series PCIe clock generator driver 4 * 5 * The following series can be supported: 6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ 7 * Currently supported: 8 * - 9FGV0241 9 * - 9FGV0441 10 * 11 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/i2c.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/regmap.h> 20 21 #define RS9_REG_OE 0x0 22 #define RS9_REG_SS 0x1 23 #define RS9_REG_SS_AMP_0V6 0x0 24 #define RS9_REG_SS_AMP_0V7 0x1 25 #define RS9_REG_SS_AMP_0V8 0x2 26 #define RS9_REG_SS_AMP_0V9 0x3 27 #define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8 28 #define RS9_REG_SS_AMP_MASK 0x3 29 #define RS9_REG_SS_SSC_100 0 30 #define RS9_REG_SS_SSC_M025 (1 << 3) 31 #define RS9_REG_SS_SSC_M050 (3 << 3) 32 #define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100 33 #define RS9_REG_SS_SSC_MASK (3 << 3) 34 #define RS9_REG_SS_SSC_LOCK BIT(5) 35 #define RS9_REG_SR 0x2 36 #define RS9_REG_REF 0x3 37 #define RS9_REG_REF_OE BIT(4) 38 #define RS9_REG_REF_OD BIT(5) 39 #define RS9_REG_REF_SR_SLOWEST 0 40 #define RS9_REG_REF_SR_SLOW (1 << 6) 41 #define RS9_REG_REF_SR_FAST (2 << 6) 42 #define RS9_REG_REF_SR_FASTER (3 << 6) 43 #define RS9_REG_VID 0x5 44 #define RS9_REG_DID 0x6 45 #define RS9_REG_BCP 0x7 46 47 #define RS9_REG_VID_IDT 0x01 48 49 #define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT) 50 #define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT) 51 #define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT) 52 #define RS9_REG_DID_TYPE_SHIFT 0x6 53 54 /* Supported Renesas 9-series models. */ 55 enum rs9_model { 56 RENESAS_9FGV0241, 57 RENESAS_9FGV0441, 58 }; 59 60 /* Structure to describe features of a particular 9-series model */ 61 struct rs9_chip_info { 62 const enum rs9_model model; 63 unsigned int num_clks; 64 u8 did; 65 }; 66 67 struct rs9_driver_data { 68 struct i2c_client *client; 69 struct regmap *regmap; 70 const struct rs9_chip_info *chip_info; 71 struct clk_hw *clk_dif[4]; 72 u8 pll_amplitude; 73 u8 pll_ssc; 74 u8 clk_dif_sr; 75 }; 76 77 /* 78 * Renesas 9-series i2c regmap 79 */ 80 static const struct regmap_range rs9_readable_ranges[] = { 81 regmap_reg_range(RS9_REG_OE, RS9_REG_REF), 82 regmap_reg_range(RS9_REG_VID, RS9_REG_BCP), 83 }; 84 85 static const struct regmap_access_table rs9_readable_table = { 86 .yes_ranges = rs9_readable_ranges, 87 .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges), 88 }; 89 90 static const struct regmap_range rs9_writeable_ranges[] = { 91 regmap_reg_range(RS9_REG_OE, RS9_REG_REF), 92 regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP), 93 }; 94 95 static const struct regmap_access_table rs9_writeable_table = { 96 .yes_ranges = rs9_writeable_ranges, 97 .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges), 98 }; 99 100 static int rs9_regmap_i2c_write(void *context, 101 unsigned int reg, unsigned int val) 102 { 103 struct i2c_client *i2c = context; 104 const u8 data[3] = { reg, 1, val }; 105 const int count = ARRAY_SIZE(data); 106 int ret; 107 108 ret = i2c_master_send(i2c, data, count); 109 if (ret == count) 110 return 0; 111 else if (ret < 0) 112 return ret; 113 else 114 return -EIO; 115 } 116 117 static int rs9_regmap_i2c_read(void *context, 118 unsigned int reg, unsigned int *val) 119 { 120 struct i2c_client *i2c = context; 121 struct i2c_msg xfer[2]; 122 u8 txdata = reg; 123 u8 rxdata[2]; 124 int ret; 125 126 xfer[0].addr = i2c->addr; 127 xfer[0].flags = 0; 128 xfer[0].len = 1; 129 xfer[0].buf = (void *)&txdata; 130 131 xfer[1].addr = i2c->addr; 132 xfer[1].flags = I2C_M_RD; 133 xfer[1].len = 2; 134 xfer[1].buf = (void *)rxdata; 135 136 ret = i2c_transfer(i2c->adapter, xfer, 2); 137 if (ret < 0) 138 return ret; 139 if (ret != 2) 140 return -EIO; 141 142 /* 143 * Byte 0 is transfer length, which is always 1 due 144 * to BCP register programming to 1 in rs9_probe(), 145 * ignore it and use data from Byte 1. 146 */ 147 *val = rxdata[1]; 148 return 0; 149 } 150 151 static const struct regmap_config rs9_regmap_config = { 152 .reg_bits = 8, 153 .val_bits = 8, 154 .cache_type = REGCACHE_FLAT, 155 .max_register = RS9_REG_BCP, 156 .num_reg_defaults_raw = 0x8, 157 .rd_table = &rs9_readable_table, 158 .wr_table = &rs9_writeable_table, 159 .reg_write = rs9_regmap_i2c_write, 160 .reg_read = rs9_regmap_i2c_read, 161 }; 162 163 static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) 164 { 165 enum rs9_model model = rs9->chip_info->model; 166 167 if (model == RENESAS_9FGV0241) 168 return BIT(idx + 1); 169 else if (model == RENESAS_9FGV0441) 170 return BIT(idx); 171 172 return 0; 173 } 174 175 static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) 176 { 177 struct i2c_client *client = rs9->client; 178 u8 dif = rs9_calc_dif(rs9, idx); 179 unsigned char name[5] = "DIF0"; 180 struct device_node *np; 181 int ret; 182 u32 sr; 183 184 /* Set defaults */ 185 rs9->clk_dif_sr |= dif; 186 187 snprintf(name, 5, "DIF%d", idx); 188 np = of_get_child_by_name(client->dev.of_node, name); 189 if (!np) 190 return 0; 191 192 /* Output clock slew rate */ 193 ret = of_property_read_u32(np, "renesas,slew-rate", &sr); 194 of_node_put(np); 195 if (!ret) { 196 if (sr == 2000000) { /* 2V/ns */ 197 rs9->clk_dif_sr &= ~dif; 198 } else if (sr == 3000000) { /* 3V/ns (default) */ 199 rs9->clk_dif_sr |= dif; 200 } else 201 ret = dev_err_probe(&client->dev, -EINVAL, 202 "Invalid renesas,slew-rate value\n"); 203 } 204 205 return ret; 206 } 207 208 static int rs9_get_common_config(struct rs9_driver_data *rs9) 209 { 210 struct i2c_client *client = rs9->client; 211 struct device_node *np = client->dev.of_node; 212 unsigned int amp, ssc; 213 int ret; 214 215 /* Set defaults */ 216 rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT; 217 rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT; 218 219 /* Output clock amplitude */ 220 ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt", 221 &); 222 if (!ret) { 223 if (amp == 600000) /* 0.6V */ 224 rs9->pll_amplitude = RS9_REG_SS_AMP_0V6; 225 else if (amp == 700000) /* 0.7V (default) */ 226 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; 227 else if (amp == 800000) /* 0.8V */ 228 rs9->pll_amplitude = RS9_REG_SS_AMP_0V8; 229 else if (amp == 900000) /* 0.9V */ 230 rs9->pll_amplitude = RS9_REG_SS_AMP_0V9; 231 else 232 return dev_err_probe(&client->dev, -EINVAL, 233 "Invalid renesas,out-amplitude-microvolt value\n"); 234 } 235 236 /* Output clock spread spectrum */ 237 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); 238 if (!ret) { 239 if (ssc == 100000) /* 100% ... no spread (default) */ 240 rs9->pll_ssc = RS9_REG_SS_SSC_100; 241 else if (ssc == 99750) /* -0.25% ... down spread */ 242 rs9->pll_ssc = RS9_REG_SS_SSC_M025; 243 else if (ssc == 99500) /* -0.50% ... down spread */ 244 rs9->pll_ssc = RS9_REG_SS_SSC_M050; 245 else 246 return dev_err_probe(&client->dev, -EINVAL, 247 "Invalid renesas,out-spread-spectrum value\n"); 248 } 249 250 return 0; 251 } 252 253 static void rs9_update_config(struct rs9_driver_data *rs9) 254 { 255 int i; 256 257 /* If amplitude is non-default, update it. */ 258 if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) { 259 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK, 260 rs9->pll_amplitude); 261 } 262 263 /* If SSC is non-default, update it. */ 264 if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) { 265 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK, 266 rs9->pll_ssc); 267 } 268 269 for (i = 0; i < rs9->chip_info->num_clks; i++) { 270 u8 dif = rs9_calc_dif(rs9, i); 271 272 if (rs9->clk_dif_sr & dif) 273 continue; 274 275 regmap_update_bits(rs9->regmap, RS9_REG_SR, dif, 276 rs9->clk_dif_sr & dif); 277 } 278 } 279 280 static struct clk_hw * 281 rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) 282 { 283 struct rs9_driver_data *rs9 = data; 284 unsigned int idx = clkspec->args[0]; 285 286 return rs9->clk_dif[idx]; 287 } 288 289 static int rs9_probe(struct i2c_client *client) 290 { 291 unsigned char name[5] = "DIF0"; 292 struct rs9_driver_data *rs9; 293 unsigned int vid, did; 294 struct clk_hw *hw; 295 int i, ret; 296 297 rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL); 298 if (!rs9) 299 return -ENOMEM; 300 301 i2c_set_clientdata(client, rs9); 302 rs9->client = client; 303 rs9->chip_info = device_get_match_data(&client->dev); 304 if (!rs9->chip_info) 305 return -EINVAL; 306 307 /* Fetch common configuration from DT (if specified) */ 308 ret = rs9_get_common_config(rs9); 309 if (ret) 310 return ret; 311 312 /* Fetch DIFx output configuration from DT (if specified) */ 313 for (i = 0; i < rs9->chip_info->num_clks; i++) { 314 ret = rs9_get_output_config(rs9, i); 315 if (ret) 316 return ret; 317 } 318 319 rs9->regmap = devm_regmap_init(&client->dev, NULL, 320 client, &rs9_regmap_config); 321 if (IS_ERR(rs9->regmap)) 322 return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap), 323 "Failed to allocate register map\n"); 324 325 /* Always read back 1 Byte via I2C */ 326 ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1); 327 if (ret < 0) 328 return ret; 329 330 ret = regmap_read(rs9->regmap, RS9_REG_VID, &vid); 331 if (ret < 0) 332 return ret; 333 334 ret = regmap_read(rs9->regmap, RS9_REG_DID, &did); 335 if (ret < 0) 336 return ret; 337 338 if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did) 339 return dev_err_probe(&client->dev, -ENODEV, 340 "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n", 341 vid, did, RS9_REG_VID_IDT, 342 rs9->chip_info->did); 343 344 /* Register clock */ 345 for (i = 0; i < rs9->chip_info->num_clks; i++) { 346 snprintf(name, 5, "DIF%d", i); 347 hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name, 348 0, 0, 4, 1); 349 if (IS_ERR(hw)) 350 return PTR_ERR(hw); 351 352 rs9->clk_dif[i] = hw; 353 } 354 355 ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9); 356 if (!ret) 357 rs9_update_config(rs9); 358 359 return ret; 360 } 361 362 static int __maybe_unused rs9_suspend(struct device *dev) 363 { 364 struct rs9_driver_data *rs9 = dev_get_drvdata(dev); 365 366 regcache_cache_only(rs9->regmap, true); 367 regcache_mark_dirty(rs9->regmap); 368 369 return 0; 370 } 371 372 static int __maybe_unused rs9_resume(struct device *dev) 373 { 374 struct rs9_driver_data *rs9 = dev_get_drvdata(dev); 375 int ret; 376 377 regcache_cache_only(rs9->regmap, false); 378 ret = regcache_sync(rs9->regmap); 379 if (ret) 380 dev_err(dev, "Failed to restore register map: %d\n", ret); 381 return ret; 382 } 383 384 static const struct rs9_chip_info renesas_9fgv0241_info = { 385 .model = RENESAS_9FGV0241, 386 .num_clks = 2, 387 .did = RS9_REG_DID_TYPE_FGV | 0x02, 388 }; 389 390 static const struct rs9_chip_info renesas_9fgv0441_info = { 391 .model = RENESAS_9FGV0441, 392 .num_clks = 4, 393 .did = RS9_REG_DID_TYPE_FGV | 0x04, 394 }; 395 396 static const struct i2c_device_id rs9_id[] = { 397 { "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info }, 398 { "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info }, 399 { } 400 }; 401 MODULE_DEVICE_TABLE(i2c, rs9_id); 402 403 static const struct of_device_id clk_rs9_of_match[] = { 404 { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, 405 { .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info }, 406 { } 407 }; 408 MODULE_DEVICE_TABLE(of, clk_rs9_of_match); 409 410 static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume); 411 412 static struct i2c_driver rs9_driver = { 413 .driver = { 414 .name = "clk-renesas-pcie-9series", 415 .pm = &rs9_pm_ops, 416 .of_match_table = clk_rs9_of_match, 417 }, 418 .probe = rs9_probe, 419 .id_table = rs9_id, 420 }; 421 module_i2c_driver(rs9_driver); 422 423 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 424 MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver"); 425 MODULE_LICENSE("GPL"); 426