1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * clock driver for Freescale QorIQ SoCs. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/clkdev.h> 14 #include <linux/fsl/guts.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_platform.h> 20 #include <linux/of.h> 21 #include <linux/slab.h> 22 23 #define PLL_DIV1 0 24 #define PLL_DIV2 1 25 #define PLL_DIV3 2 26 #define PLL_DIV4 3 27 28 #define PLATFORM_PLL 0 29 #define CGA_PLL1 1 30 #define CGA_PLL2 2 31 #define CGA_PLL3 3 32 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */ 33 #define CGB_PLL1 4 34 #define CGB_PLL2 5 35 #define MAX_PLL_DIV 32 36 37 struct clockgen_pll_div { 38 struct clk *clk; 39 char name[32]; 40 }; 41 42 struct clockgen_pll { 43 struct clockgen_pll_div div[MAX_PLL_DIV]; 44 }; 45 46 #define CLKSEL_VALID 1 47 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */ 48 49 struct clockgen_sourceinfo { 50 u32 flags; /* CLKSEL_xxx */ 51 int pll; /* CGx_PLLn */ 52 int div; /* PLL_DIVn */ 53 }; 54 55 #define NUM_MUX_PARENTS 16 56 57 struct clockgen_muxinfo { 58 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; 59 }; 60 61 #define NUM_HWACCEL 5 62 #define NUM_CMUX 8 63 64 struct clockgen; 65 66 /* 67 * cmux freq must be >= platform pll. 68 * If not set, cmux freq must be >= platform pll/2 69 */ 70 #define CG_CMUX_GE_PLAT 1 71 72 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */ 73 #define CG_VER3 4 /* version 3 cg: reg layout different */ 74 #define CG_LITTLE_ENDIAN 8 75 76 struct clockgen_chipinfo { 77 const char *compat, *guts_compat; 78 const struct clockgen_muxinfo *cmux_groups[2]; 79 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; 80 void (*init_periph)(struct clockgen *cg); 81 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */ 82 u32 pll_mask; /* 1 << n bit set if PLL n is valid */ 83 u32 flags; /* CG_xxx */ 84 }; 85 86 struct clockgen { 87 struct device_node *node; 88 void __iomem *regs; 89 struct clockgen_chipinfo info; /* mutable copy */ 90 struct clk *sysclk, *coreclk; 91 struct clockgen_pll pll[6]; 92 struct clk *cmux[NUM_CMUX]; 93 struct clk *hwaccel[NUM_HWACCEL]; 94 struct clk *fman[2]; 95 struct ccsr_guts __iomem *guts; 96 }; 97 98 static struct clockgen clockgen; 99 static bool add_cpufreq_dev __initdata; 100 101 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) 102 { 103 if (cg->info.flags & CG_LITTLE_ENDIAN) 104 iowrite32(val, reg); 105 else 106 iowrite32be(val, reg); 107 } 108 109 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) 110 { 111 u32 val; 112 113 if (cg->info.flags & CG_LITTLE_ENDIAN) 114 val = ioread32(reg); 115 else 116 val = ioread32be(reg); 117 118 return val; 119 } 120 121 static const struct clockgen_muxinfo p2041_cmux_grp1 = { 122 { 123 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 124 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 125 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 126 } 127 }; 128 129 static const struct clockgen_muxinfo p2041_cmux_grp2 = { 130 { 131 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 132 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 133 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 134 } 135 }; 136 137 static const struct clockgen_muxinfo p5020_cmux_grp1 = { 138 { 139 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 140 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 141 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, 142 } 143 }; 144 145 static const struct clockgen_muxinfo p5020_cmux_grp2 = { 146 { 147 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 148 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 149 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 150 } 151 }; 152 153 static const struct clockgen_muxinfo p5040_cmux_grp1 = { 154 { 155 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 156 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 157 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, 158 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 }, 159 } 160 }; 161 162 static const struct clockgen_muxinfo p5040_cmux_grp2 = { 163 { 164 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 165 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 }, 166 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 167 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 168 } 169 }; 170 171 static const struct clockgen_muxinfo p4080_cmux_grp1 = { 172 { 173 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 174 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 175 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 176 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 177 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 }, 178 } 179 }; 180 181 static const struct clockgen_muxinfo p4080_cmux_grp2 = { 182 { 183 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 184 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, 185 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, 186 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 }, 187 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 }, 188 } 189 }; 190 191 static const struct clockgen_muxinfo t1023_cmux = { 192 { 193 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 194 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 195 } 196 }; 197 198 static const struct clockgen_muxinfo t1040_cmux = { 199 { 200 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 201 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 202 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 203 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 204 } 205 }; 206 207 208 static const struct clockgen_muxinfo clockgen2_cmux_cga = { 209 { 210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 213 {}, 214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 217 {}, 218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, 219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, 220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 }, 221 }, 222 }; 223 224 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = { 225 { 226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 229 {}, 230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 233 }, 234 }; 235 236 static const struct clockgen_muxinfo clockgen2_cmux_cgb = { 237 { 238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 }, 239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, 241 {}, 242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 }, 243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, 245 }, 246 }; 247 248 static const struct clockgen_muxinfo ls1021a_cmux = { 249 { 250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 253 } 254 }; 255 256 static const struct clockgen_muxinfo ls1028a_hwa1 = { 257 { 258 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 259 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 262 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 263 {}, 264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 266 }, 267 }; 268 269 static const struct clockgen_muxinfo ls1028a_hwa2 = { 270 { 271 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 272 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 275 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 276 {}, 277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 279 }, 280 }; 281 282 static const struct clockgen_muxinfo ls1028a_hwa3 = { 283 { 284 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 285 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 289 {}, 290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 292 }, 293 }; 294 295 static const struct clockgen_muxinfo ls1028a_hwa4 = { 296 { 297 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 298 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 302 {}, 303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 304 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 305 }, 306 }; 307 308 static const struct clockgen_muxinfo ls1043a_hwa1 = { 309 { 310 {}, 311 {}, 312 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 313 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 314 {}, 315 {}, 316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 318 }, 319 }; 320 321 static const struct clockgen_muxinfo ls1043a_hwa2 = { 322 { 323 {}, 324 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 325 {}, 326 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 327 }, 328 }; 329 330 static const struct clockgen_muxinfo ls1046a_hwa1 = { 331 { 332 {}, 333 {}, 334 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 336 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 337 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 340 }, 341 }; 342 343 static const struct clockgen_muxinfo ls1046a_hwa2 = { 344 { 345 {}, 346 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 348 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 349 {}, 350 {}, 351 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 352 }, 353 }; 354 355 static const struct clockgen_muxinfo ls1088a_hwa1 = { 356 { 357 {}, 358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 362 {}, 363 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 364 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 365 }, 366 }; 367 368 static const struct clockgen_muxinfo ls1088a_hwa2 = { 369 { 370 {}, 371 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 374 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 375 {}, 376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 377 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 378 }, 379 }; 380 381 static const struct clockgen_muxinfo ls1012a_cmux = { 382 { 383 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 384 {}, 385 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 386 } 387 }; 388 389 static const struct clockgen_muxinfo t1023_hwa1 = { 390 { 391 {}, 392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 394 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 395 }, 396 }; 397 398 static const struct clockgen_muxinfo t1023_hwa2 = { 399 { 400 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 401 }, 402 }; 403 404 static const struct clockgen_muxinfo t2080_hwa1 = { 405 { 406 {}, 407 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 410 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 411 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 412 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 413 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 414 }, 415 }; 416 417 static const struct clockgen_muxinfo t2080_hwa2 = { 418 { 419 {}, 420 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 423 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 424 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 426 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 427 }, 428 }; 429 430 static const struct clockgen_muxinfo t4240_hwa1 = { 431 { 432 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 }, 433 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 436 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 437 {}, 438 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 439 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 440 }, 441 }; 442 443 static const struct clockgen_muxinfo t4240_hwa4 = { 444 { 445 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 446 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, 447 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, 448 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 449 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 450 }, 451 }; 452 453 static const struct clockgen_muxinfo t4240_hwa5 = { 454 { 455 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 456 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 }, 457 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, 458 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 459 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 460 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, 461 }, 462 }; 463 464 #define RCWSR7_FM1_CLK_SEL 0x40000000 465 #define RCWSR7_FM2_CLK_SEL 0x20000000 466 #define RCWSR7_HWA_ASYNC_DIV 0x04000000 467 468 static void __init p2041_init_periph(struct clockgen *cg) 469 { 470 u32 reg; 471 472 reg = ioread32be(&cg->guts->rcwsr[7]); 473 474 if (reg & RCWSR7_FM1_CLK_SEL) 475 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; 476 else 477 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 478 } 479 480 static void __init p4080_init_periph(struct clockgen *cg) 481 { 482 u32 reg; 483 484 reg = ioread32be(&cg->guts->rcwsr[7]); 485 486 if (reg & RCWSR7_FM1_CLK_SEL) 487 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 488 else 489 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 490 491 if (reg & RCWSR7_FM2_CLK_SEL) 492 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 493 else 494 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 495 } 496 497 static void __init p5020_init_periph(struct clockgen *cg) 498 { 499 u32 reg; 500 int div = PLL_DIV2; 501 502 reg = ioread32be(&cg->guts->rcwsr[7]); 503 if (reg & RCWSR7_HWA_ASYNC_DIV) 504 div = PLL_DIV4; 505 506 if (reg & RCWSR7_FM1_CLK_SEL) 507 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; 508 else 509 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 510 } 511 512 static void __init p5040_init_periph(struct clockgen *cg) 513 { 514 u32 reg; 515 int div = PLL_DIV2; 516 517 reg = ioread32be(&cg->guts->rcwsr[7]); 518 if (reg & RCWSR7_HWA_ASYNC_DIV) 519 div = PLL_DIV4; 520 521 if (reg & RCWSR7_FM1_CLK_SEL) 522 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; 523 else 524 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 525 526 if (reg & RCWSR7_FM2_CLK_SEL) 527 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; 528 else 529 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 530 } 531 532 static void __init t1023_init_periph(struct clockgen *cg) 533 { 534 cg->fman[0] = cg->hwaccel[1]; 535 } 536 537 static void __init t1040_init_periph(struct clockgen *cg) 538 { 539 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; 540 } 541 542 static void __init t2080_init_periph(struct clockgen *cg) 543 { 544 cg->fman[0] = cg->hwaccel[0]; 545 } 546 547 static void __init t4240_init_periph(struct clockgen *cg) 548 { 549 cg->fman[0] = cg->hwaccel[3]; 550 cg->fman[1] = cg->hwaccel[4]; 551 } 552 553 static const struct clockgen_chipinfo chipinfo[] = { 554 { 555 .compat = "fsl,b4420-clockgen", 556 .guts_compat = "fsl,b4860-device-config", 557 .init_periph = t2080_init_periph, 558 .cmux_groups = { 559 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 560 }, 561 .hwaccel = { 562 &t2080_hwa1 563 }, 564 .cmux_to_group = { 565 0, 1, 1, 1, -1 566 }, 567 .pll_mask = 0x3f, 568 .flags = CG_PLL_8BIT, 569 }, 570 { 571 .compat = "fsl,b4860-clockgen", 572 .guts_compat = "fsl,b4860-device-config", 573 .init_periph = t2080_init_periph, 574 .cmux_groups = { 575 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 576 }, 577 .hwaccel = { 578 &t2080_hwa1 579 }, 580 .cmux_to_group = { 581 0, 1, 1, 1, -1 582 }, 583 .pll_mask = 0x3f, 584 .flags = CG_PLL_8BIT, 585 }, 586 { 587 .compat = "fsl,ls1021a-clockgen", 588 .cmux_groups = { 589 &ls1021a_cmux 590 }, 591 .cmux_to_group = { 592 0, -1 593 }, 594 .pll_mask = 0x03, 595 }, 596 { 597 .compat = "fsl,ls1028a-clockgen", 598 .cmux_groups = { 599 &clockgen2_cmux_cga12 600 }, 601 .hwaccel = { 602 &ls1028a_hwa1, &ls1028a_hwa2, 603 &ls1028a_hwa3, &ls1028a_hwa4 604 }, 605 .cmux_to_group = { 606 0, 0, 0, 0, -1 607 }, 608 .pll_mask = 0x07, 609 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 610 }, 611 { 612 .compat = "fsl,ls1043a-clockgen", 613 .init_periph = t2080_init_periph, 614 .cmux_groups = { 615 &t1040_cmux 616 }, 617 .hwaccel = { 618 &ls1043a_hwa1, &ls1043a_hwa2 619 }, 620 .cmux_to_group = { 621 0, -1 622 }, 623 .pll_mask = 0x07, 624 .flags = CG_PLL_8BIT, 625 }, 626 { 627 .compat = "fsl,ls1046a-clockgen", 628 .init_periph = t2080_init_periph, 629 .cmux_groups = { 630 &t1040_cmux 631 }, 632 .hwaccel = { 633 &ls1046a_hwa1, &ls1046a_hwa2 634 }, 635 .cmux_to_group = { 636 0, -1 637 }, 638 .pll_mask = 0x07, 639 .flags = CG_PLL_8BIT, 640 }, 641 { 642 .compat = "fsl,ls1088a-clockgen", 643 .cmux_groups = { 644 &clockgen2_cmux_cga12 645 }, 646 .hwaccel = { 647 &ls1088a_hwa1, &ls1088a_hwa2 648 }, 649 .cmux_to_group = { 650 0, 0, -1 651 }, 652 .pll_mask = 0x07, 653 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 654 }, 655 { 656 .compat = "fsl,ls1012a-clockgen", 657 .cmux_groups = { 658 &ls1012a_cmux 659 }, 660 .cmux_to_group = { 661 0, -1 662 }, 663 .pll_mask = 0x03, 664 }, 665 { 666 .compat = "fsl,ls2080a-clockgen", 667 .cmux_groups = { 668 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 669 }, 670 .cmux_to_group = { 671 0, 0, 1, 1, -1 672 }, 673 .pll_mask = 0x37, 674 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 675 }, 676 { 677 .compat = "fsl,lx2160a-clockgen", 678 .cmux_groups = { 679 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 680 }, 681 .cmux_to_group = { 682 0, 0, 0, 0, 1, 1, 1, 1, -1 683 }, 684 .pll_mask = 0x37, 685 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 686 }, 687 { 688 .compat = "fsl,p2041-clockgen", 689 .guts_compat = "fsl,qoriq-device-config-1.0", 690 .init_periph = p2041_init_periph, 691 .cmux_groups = { 692 &p2041_cmux_grp1, &p2041_cmux_grp2 693 }, 694 .cmux_to_group = { 695 0, 0, 1, 1, -1 696 }, 697 .pll_mask = 0x07, 698 }, 699 { 700 .compat = "fsl,p3041-clockgen", 701 .guts_compat = "fsl,qoriq-device-config-1.0", 702 .init_periph = p2041_init_periph, 703 .cmux_groups = { 704 &p2041_cmux_grp1, &p2041_cmux_grp2 705 }, 706 .cmux_to_group = { 707 0, 0, 1, 1, -1 708 }, 709 .pll_mask = 0x07, 710 }, 711 { 712 .compat = "fsl,p4080-clockgen", 713 .guts_compat = "fsl,qoriq-device-config-1.0", 714 .init_periph = p4080_init_periph, 715 .cmux_groups = { 716 &p4080_cmux_grp1, &p4080_cmux_grp2 717 }, 718 .cmux_to_group = { 719 0, 0, 0, 0, 1, 1, 1, 1, -1 720 }, 721 .pll_mask = 0x1f, 722 }, 723 { 724 .compat = "fsl,p5020-clockgen", 725 .guts_compat = "fsl,qoriq-device-config-1.0", 726 .init_periph = p5020_init_periph, 727 .cmux_groups = { 728 &p5020_cmux_grp1, &p5020_cmux_grp2 729 }, 730 .cmux_to_group = { 731 0, 1, -1 732 }, 733 .pll_mask = 0x07, 734 }, 735 { 736 .compat = "fsl,p5040-clockgen", 737 .guts_compat = "fsl,p5040-device-config", 738 .init_periph = p5040_init_periph, 739 .cmux_groups = { 740 &p5040_cmux_grp1, &p5040_cmux_grp2 741 }, 742 .cmux_to_group = { 743 0, 0, 1, 1, -1 744 }, 745 .pll_mask = 0x0f, 746 }, 747 { 748 .compat = "fsl,t1023-clockgen", 749 .guts_compat = "fsl,t1023-device-config", 750 .init_periph = t1023_init_periph, 751 .cmux_groups = { 752 &t1023_cmux 753 }, 754 .hwaccel = { 755 &t1023_hwa1, &t1023_hwa2 756 }, 757 .cmux_to_group = { 758 0, 0, -1 759 }, 760 .pll_mask = 0x03, 761 .flags = CG_PLL_8BIT, 762 }, 763 { 764 .compat = "fsl,t1040-clockgen", 765 .guts_compat = "fsl,t1040-device-config", 766 .init_periph = t1040_init_periph, 767 .cmux_groups = { 768 &t1040_cmux 769 }, 770 .cmux_to_group = { 771 0, 0, 0, 0, -1 772 }, 773 .pll_mask = 0x07, 774 .flags = CG_PLL_8BIT, 775 }, 776 { 777 .compat = "fsl,t2080-clockgen", 778 .guts_compat = "fsl,t2080-device-config", 779 .init_periph = t2080_init_periph, 780 .cmux_groups = { 781 &clockgen2_cmux_cga12 782 }, 783 .hwaccel = { 784 &t2080_hwa1, &t2080_hwa2 785 }, 786 .cmux_to_group = { 787 0, -1 788 }, 789 .pll_mask = 0x07, 790 .flags = CG_PLL_8BIT, 791 }, 792 { 793 .compat = "fsl,t4240-clockgen", 794 .guts_compat = "fsl,t4240-device-config", 795 .init_periph = t4240_init_periph, 796 .cmux_groups = { 797 &clockgen2_cmux_cga, &clockgen2_cmux_cgb 798 }, 799 .hwaccel = { 800 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5 801 }, 802 .cmux_to_group = { 803 0, 0, 1, -1 804 }, 805 .pll_mask = 0x3f, 806 .flags = CG_PLL_8BIT, 807 }, 808 {}, 809 }; 810 811 struct mux_hwclock { 812 struct clk_hw hw; 813 struct clockgen *cg; 814 const struct clockgen_muxinfo *info; 815 u32 __iomem *reg; 816 u8 parent_to_clksel[NUM_MUX_PARENTS]; 817 s8 clksel_to_parent[NUM_MUX_PARENTS]; 818 int num_parents; 819 }; 820 821 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw) 822 #define CLKSEL_MASK 0x78000000 823 #define CLKSEL_SHIFT 27 824 825 static int mux_set_parent(struct clk_hw *hw, u8 idx) 826 { 827 struct mux_hwclock *hwc = to_mux_hwclock(hw); 828 u32 clksel; 829 830 if (idx >= hwc->num_parents) 831 return -EINVAL; 832 833 clksel = hwc->parent_to_clksel[idx]; 834 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); 835 836 return 0; 837 } 838 839 static u8 mux_get_parent(struct clk_hw *hw) 840 { 841 struct mux_hwclock *hwc = to_mux_hwclock(hw); 842 u32 clksel; 843 s8 ret; 844 845 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; 846 847 ret = hwc->clksel_to_parent[clksel]; 848 if (ret < 0) { 849 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); 850 return 0; 851 } 852 853 return ret; 854 } 855 856 static const struct clk_ops cmux_ops = { 857 .get_parent = mux_get_parent, 858 .set_parent = mux_set_parent, 859 }; 860 861 /* 862 * Don't allow setting for now, as the clock options haven't been 863 * sanitized for additional restrictions. 864 */ 865 static const struct clk_ops hwaccel_ops = { 866 .get_parent = mux_get_parent, 867 }; 868 869 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, 870 struct mux_hwclock *hwc, 871 int idx) 872 { 873 int pll, div; 874 875 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) 876 return NULL; 877 878 pll = hwc->info->clksel[idx].pll; 879 div = hwc->info->clksel[idx].div; 880 881 return &cg->pll[pll].div[div]; 882 } 883 884 static struct clk * __init create_mux_common(struct clockgen *cg, 885 struct mux_hwclock *hwc, 886 const struct clk_ops *ops, 887 unsigned long min_rate, 888 unsigned long max_rate, 889 unsigned long pct80_rate, 890 const char *fmt, int idx) 891 { 892 struct clk_init_data init = {}; 893 struct clk *clk; 894 const struct clockgen_pll_div *div; 895 const char *parent_names[NUM_MUX_PARENTS]; 896 char name[32]; 897 int i, j; 898 899 snprintf(name, sizeof(name), fmt, idx); 900 901 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) { 902 unsigned long rate; 903 904 hwc->clksel_to_parent[i] = -1; 905 906 div = get_pll_div(cg, hwc, i); 907 if (!div) 908 continue; 909 910 rate = clk_get_rate(div->clk); 911 912 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && 913 rate > pct80_rate) 914 continue; 915 if (rate < min_rate) 916 continue; 917 if (rate > max_rate) 918 continue; 919 920 parent_names[j] = div->name; 921 hwc->parent_to_clksel[j] = i; 922 hwc->clksel_to_parent[i] = j; 923 j++; 924 } 925 926 init.name = name; 927 init.ops = ops; 928 init.parent_names = parent_names; 929 init.num_parents = hwc->num_parents = j; 930 init.flags = 0; 931 hwc->hw.init = &init; 932 hwc->cg = cg; 933 934 clk = clk_register(NULL, &hwc->hw); 935 if (IS_ERR(clk)) { 936 pr_err("%s: Couldn't register %s: %ld\n", __func__, name, 937 PTR_ERR(clk)); 938 kfree(hwc); 939 return NULL; 940 } 941 942 return clk; 943 } 944 945 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) 946 { 947 struct mux_hwclock *hwc; 948 const struct clockgen_pll_div *div; 949 unsigned long plat_rate, min_rate; 950 u64 max_rate, pct80_rate; 951 u32 clksel; 952 953 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); 954 if (!hwc) 955 return NULL; 956 957 if (cg->info.flags & CG_VER3) 958 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; 959 else 960 hwc->reg = cg->regs + 0x20 * idx; 961 962 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; 963 964 /* 965 * Find the rate for the default clksel, and treat it as the 966 * maximum rated core frequency. If this is an incorrect 967 * assumption, certain clock options (possibly including the 968 * default clksel) may be inappropriately excluded on certain 969 * chips. 970 */ 971 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; 972 div = get_pll_div(cg, hwc, clksel); 973 if (!div) { 974 kfree(hwc); 975 return NULL; 976 } 977 978 max_rate = clk_get_rate(div->clk); 979 pct80_rate = max_rate * 8; 980 do_div(pct80_rate, 10); 981 982 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); 983 984 if (cg->info.flags & CG_CMUX_GE_PLAT) 985 min_rate = plat_rate; 986 else 987 min_rate = plat_rate / 2; 988 989 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate, 990 pct80_rate, "cg-cmux%d", idx); 991 } 992 993 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) 994 { 995 struct mux_hwclock *hwc; 996 997 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); 998 if (!hwc) 999 return NULL; 1000 1001 hwc->reg = cg->regs + 0x20 * idx + 0x10; 1002 hwc->info = cg->info.hwaccel[idx]; 1003 1004 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0, 1005 "cg-hwaccel%d", idx); 1006 } 1007 1008 static void __init create_muxes(struct clockgen *cg) 1009 { 1010 int i; 1011 1012 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { 1013 if (cg->info.cmux_to_group[i] < 0) 1014 break; 1015 if (cg->info.cmux_to_group[i] >= 1016 ARRAY_SIZE(cg->info.cmux_groups)) { 1017 WARN_ON_ONCE(1); 1018 continue; 1019 } 1020 1021 cg->cmux[i] = create_one_cmux(cg, i); 1022 } 1023 1024 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { 1025 if (!cg->info.hwaccel[i]) 1026 continue; 1027 1028 cg->hwaccel[i] = create_one_hwaccel(cg, i); 1029 } 1030 } 1031 1032 static void __init _clockgen_init(struct device_node *np, bool legacy); 1033 1034 /* 1035 * Legacy nodes may get probed before the parent clockgen node. 1036 * It is assumed that device trees with legacy nodes will not 1037 * contain a "clocks" property -- otherwise the input clocks may 1038 * not be initialized at this point. 1039 */ 1040 static void __init legacy_init_clockgen(struct device_node *np) 1041 { 1042 if (!clockgen.node) 1043 _clockgen_init(of_get_parent(np), true); 1044 } 1045 1046 /* Legacy node */ 1047 static void __init core_mux_init(struct device_node *np) 1048 { 1049 struct clk *clk; 1050 struct resource res; 1051 int idx, rc; 1052 1053 legacy_init_clockgen(np); 1054 1055 if (of_address_to_resource(np, 0, &res)) 1056 return; 1057 1058 idx = (res.start & 0xf0) >> 5; 1059 clk = clockgen.cmux[idx]; 1060 1061 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 1062 if (rc) { 1063 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1064 __func__, np, rc); 1065 return; 1066 } 1067 } 1068 1069 static struct clk __init 1070 *sysclk_from_fixed(struct device_node *node, const char *name) 1071 { 1072 u32 rate; 1073 1074 if (of_property_read_u32(node, "clock-frequency", &rate)) 1075 return ERR_PTR(-ENODEV); 1076 1077 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 1078 } 1079 1080 static struct clk __init *input_clock(const char *name, struct clk *clk) 1081 { 1082 const char *input_name; 1083 1084 /* Register the input clock under the desired name. */ 1085 input_name = __clk_get_name(clk); 1086 clk = clk_register_fixed_factor(NULL, name, input_name, 1087 0, 1, 1); 1088 if (IS_ERR(clk)) 1089 pr_err("%s: Couldn't register %s: %ld\n", __func__, name, 1090 PTR_ERR(clk)); 1091 1092 return clk; 1093 } 1094 1095 static struct clk __init *input_clock_by_name(const char *name, 1096 const char *dtname) 1097 { 1098 struct clk *clk; 1099 1100 clk = of_clk_get_by_name(clockgen.node, dtname); 1101 if (IS_ERR(clk)) 1102 return clk; 1103 1104 return input_clock(name, clk); 1105 } 1106 1107 static struct clk __init *input_clock_by_index(const char *name, int idx) 1108 { 1109 struct clk *clk; 1110 1111 clk = of_clk_get(clockgen.node, 0); 1112 if (IS_ERR(clk)) 1113 return clk; 1114 1115 return input_clock(name, clk); 1116 } 1117 1118 static struct clk * __init create_sysclk(const char *name) 1119 { 1120 struct device_node *sysclk; 1121 struct clk *clk; 1122 1123 clk = sysclk_from_fixed(clockgen.node, name); 1124 if (!IS_ERR(clk)) 1125 return clk; 1126 1127 clk = input_clock_by_name(name, "sysclk"); 1128 if (!IS_ERR(clk)) 1129 return clk; 1130 1131 clk = input_clock_by_index(name, 0); 1132 if (!IS_ERR(clk)) 1133 return clk; 1134 1135 sysclk = of_get_child_by_name(clockgen.node, "sysclk"); 1136 if (sysclk) { 1137 clk = sysclk_from_fixed(sysclk, name); 1138 if (!IS_ERR(clk)) 1139 return clk; 1140 } 1141 1142 pr_err("%s: No input sysclk\n", __func__); 1143 return NULL; 1144 } 1145 1146 static struct clk * __init create_coreclk(const char *name) 1147 { 1148 struct clk *clk; 1149 1150 clk = input_clock_by_name(name, "coreclk"); 1151 if (!IS_ERR(clk)) 1152 return clk; 1153 1154 /* 1155 * This indicates a mix of legacy nodes with the new coreclk 1156 * mechanism, which should never happen. If this error occurs, 1157 * don't use the wrong input clock just because coreclk isn't 1158 * ready yet. 1159 */ 1160 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) 1161 return clk; 1162 1163 return NULL; 1164 } 1165 1166 /* Legacy node */ 1167 static void __init sysclk_init(struct device_node *node) 1168 { 1169 struct clk *clk; 1170 1171 legacy_init_clockgen(node); 1172 1173 clk = clockgen.sysclk; 1174 if (clk) 1175 of_clk_add_provider(node, of_clk_src_simple_get, clk); 1176 } 1177 1178 #define PLL_KILL BIT(31) 1179 1180 static void __init create_one_pll(struct clockgen *cg, int idx) 1181 { 1182 u32 __iomem *reg; 1183 u32 mult; 1184 struct clockgen_pll *pll = &cg->pll[idx]; 1185 const char *input = "cg-sysclk"; 1186 int i; 1187 1188 if (!(cg->info.pll_mask & (1 << idx))) 1189 return; 1190 1191 if (cg->coreclk && idx != PLATFORM_PLL) { 1192 if (IS_ERR(cg->coreclk)) 1193 return; 1194 1195 input = "cg-coreclk"; 1196 } 1197 1198 if (cg->info.flags & CG_VER3) { 1199 switch (idx) { 1200 case PLATFORM_PLL: 1201 reg = cg->regs + 0x60080; 1202 break; 1203 case CGA_PLL1: 1204 reg = cg->regs + 0x80; 1205 break; 1206 case CGA_PLL2: 1207 reg = cg->regs + 0xa0; 1208 break; 1209 case CGB_PLL1: 1210 reg = cg->regs + 0x10080; 1211 break; 1212 case CGB_PLL2: 1213 reg = cg->regs + 0x100a0; 1214 break; 1215 default: 1216 WARN_ONCE(1, "index %d\n", idx); 1217 return; 1218 } 1219 } else { 1220 if (idx == PLATFORM_PLL) 1221 reg = cg->regs + 0xc00; 1222 else 1223 reg = cg->regs + 0x800 + 0x20 * (idx - 1); 1224 } 1225 1226 /* Get the multiple of PLL */ 1227 mult = cg_in(cg, reg); 1228 1229 /* Check if this PLL is disabled */ 1230 if (mult & PLL_KILL) { 1231 pr_debug("%s(): pll %p disabled\n", __func__, reg); 1232 return; 1233 } 1234 1235 if ((cg->info.flags & CG_VER3) || 1236 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) 1237 mult = (mult & GENMASK(8, 1)) >> 1; 1238 else 1239 mult = (mult & GENMASK(6, 1)) >> 1; 1240 1241 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { 1242 struct clk *clk; 1243 int ret; 1244 1245 /* 1246 * For platform PLL, there are MAX_PLL_DIV divider clocks. 1247 * For core PLL, there are 4 divider clocks at most. 1248 */ 1249 if (idx != PLATFORM_PLL && i >= 4) 1250 break; 1251 1252 snprintf(pll->div[i].name, sizeof(pll->div[i].name), 1253 "cg-pll%d-div%d", idx, i + 1); 1254 1255 clk = clk_register_fixed_factor(NULL, 1256 pll->div[i].name, input, 0, mult, i + 1); 1257 if (IS_ERR(clk)) { 1258 pr_err("%s: %s: register failed %ld\n", 1259 __func__, pll->div[i].name, PTR_ERR(clk)); 1260 continue; 1261 } 1262 1263 pll->div[i].clk = clk; 1264 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); 1265 if (ret != 0) 1266 pr_err("%s: %s: register to lookup table failed %d\n", 1267 __func__, pll->div[i].name, ret); 1268 1269 } 1270 } 1271 1272 static void __init create_plls(struct clockgen *cg) 1273 { 1274 int i; 1275 1276 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) 1277 create_one_pll(cg, i); 1278 } 1279 1280 static void __init legacy_pll_init(struct device_node *np, int idx) 1281 { 1282 struct clockgen_pll *pll; 1283 struct clk_onecell_data *onecell_data; 1284 struct clk **subclks; 1285 int count, rc; 1286 1287 legacy_init_clockgen(np); 1288 1289 pll = &clockgen.pll[idx]; 1290 count = of_property_count_strings(np, "clock-output-names"); 1291 1292 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); 1293 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); 1294 if (!subclks) 1295 return; 1296 1297 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL); 1298 if (!onecell_data) 1299 goto err_clks; 1300 1301 if (count <= 3) { 1302 subclks[0] = pll->div[0].clk; 1303 subclks[1] = pll->div[1].clk; 1304 subclks[2] = pll->div[3].clk; 1305 } else { 1306 subclks[0] = pll->div[0].clk; 1307 subclks[1] = pll->div[1].clk; 1308 subclks[2] = pll->div[2].clk; 1309 subclks[3] = pll->div[3].clk; 1310 } 1311 1312 onecell_data->clks = subclks; 1313 onecell_data->clk_num = count; 1314 1315 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); 1316 if (rc) { 1317 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1318 __func__, np, rc); 1319 goto err_cell; 1320 } 1321 1322 return; 1323 err_cell: 1324 kfree(onecell_data); 1325 err_clks: 1326 kfree(subclks); 1327 } 1328 1329 /* Legacy node */ 1330 static void __init pltfrm_pll_init(struct device_node *np) 1331 { 1332 legacy_pll_init(np, PLATFORM_PLL); 1333 } 1334 1335 /* Legacy node */ 1336 static void __init core_pll_init(struct device_node *np) 1337 { 1338 struct resource res; 1339 int idx; 1340 1341 if (of_address_to_resource(np, 0, &res)) 1342 return; 1343 1344 if ((res.start & 0xfff) == 0xc00) { 1345 /* 1346 * ls1021a devtree labels the platform PLL 1347 * with the core PLL compatible 1348 */ 1349 pltfrm_pll_init(np); 1350 } else { 1351 idx = (res.start & 0xf0) >> 5; 1352 legacy_pll_init(np, CGA_PLL1 + idx); 1353 } 1354 } 1355 1356 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) 1357 { 1358 struct clockgen *cg = data; 1359 struct clk *clk; 1360 struct clockgen_pll *pll; 1361 u32 type, idx; 1362 1363 if (clkspec->args_count < 2) { 1364 pr_err("%s: insufficient phandle args\n", __func__); 1365 return ERR_PTR(-EINVAL); 1366 } 1367 1368 type = clkspec->args[0]; 1369 idx = clkspec->args[1]; 1370 1371 switch (type) { 1372 case QORIQ_CLK_SYSCLK: 1373 if (idx != 0) 1374 goto bad_args; 1375 clk = cg->sysclk; 1376 break; 1377 case QORIQ_CLK_CMUX: 1378 if (idx >= ARRAY_SIZE(cg->cmux)) 1379 goto bad_args; 1380 clk = cg->cmux[idx]; 1381 break; 1382 case QORIQ_CLK_HWACCEL: 1383 if (idx >= ARRAY_SIZE(cg->hwaccel)) 1384 goto bad_args; 1385 clk = cg->hwaccel[idx]; 1386 break; 1387 case QORIQ_CLK_FMAN: 1388 if (idx >= ARRAY_SIZE(cg->fman)) 1389 goto bad_args; 1390 clk = cg->fman[idx]; 1391 break; 1392 case QORIQ_CLK_PLATFORM_PLL: 1393 pll = &cg->pll[PLATFORM_PLL]; 1394 if (idx >= ARRAY_SIZE(pll->div)) 1395 goto bad_args; 1396 clk = pll->div[idx].clk; 1397 break; 1398 case QORIQ_CLK_CORECLK: 1399 if (idx != 0) 1400 goto bad_args; 1401 clk = cg->coreclk; 1402 if (IS_ERR(clk)) 1403 clk = NULL; 1404 break; 1405 default: 1406 goto bad_args; 1407 } 1408 1409 if (!clk) 1410 return ERR_PTR(-ENOENT); 1411 return clk; 1412 1413 bad_args: 1414 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx); 1415 return ERR_PTR(-EINVAL); 1416 } 1417 1418 #ifdef CONFIG_PPC 1419 #include <asm/mpc85xx.h> 1420 1421 static const u32 a4510_svrs[] __initconst = { 1422 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ 1423 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */ 1424 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */ 1425 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */ 1426 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */ 1427 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */ 1428 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */ 1429 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */ 1430 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */ 1431 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */ 1432 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */ 1433 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */ 1434 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */ 1435 }; 1436 1437 #define SVR_SECURITY 0x80000 /* The Security (E) bit */ 1438 1439 static bool __init has_erratum_a4510(void) 1440 { 1441 u32 svr = mfspr(SPRN_SVR); 1442 int i; 1443 1444 svr &= ~SVR_SECURITY; 1445 1446 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) { 1447 if (svr == a4510_svrs[i]) 1448 return true; 1449 } 1450 1451 return false; 1452 } 1453 #else 1454 static bool __init has_erratum_a4510(void) 1455 { 1456 return false; 1457 } 1458 #endif 1459 1460 static void __init _clockgen_init(struct device_node *np, bool legacy) 1461 { 1462 int i, ret; 1463 bool is_old_ls1021a = false; 1464 1465 /* May have already been called by a legacy probe */ 1466 if (clockgen.node) 1467 return; 1468 1469 clockgen.node = np; 1470 clockgen.regs = of_iomap(np, 0); 1471 if (!clockgen.regs && 1472 of_device_is_compatible(of_root, "fsl,ls1021a")) { 1473 /* Compatibility hack for old, broken device trees */ 1474 clockgen.regs = ioremap(0x1ee1000, 0x1000); 1475 is_old_ls1021a = true; 1476 } 1477 if (!clockgen.regs) { 1478 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np); 1479 return; 1480 } 1481 1482 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) { 1483 if (of_device_is_compatible(np, chipinfo[i].compat)) 1484 break; 1485 if (is_old_ls1021a && 1486 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) 1487 break; 1488 } 1489 1490 if (i == ARRAY_SIZE(chipinfo)) { 1491 pr_err("%s: unknown clockgen node %pOF\n", __func__, np); 1492 goto err; 1493 } 1494 clockgen.info = chipinfo[i]; 1495 1496 if (clockgen.info.guts_compat) { 1497 struct device_node *guts; 1498 1499 guts = of_find_compatible_node(NULL, NULL, 1500 clockgen.info.guts_compat); 1501 if (guts) { 1502 clockgen.guts = of_iomap(guts, 0); 1503 if (!clockgen.guts) { 1504 pr_err("%s: Couldn't map %pOF regs\n", __func__, 1505 guts); 1506 } 1507 of_node_put(guts); 1508 } 1509 1510 } 1511 1512 if (has_erratum_a4510()) 1513 clockgen.info.flags |= CG_CMUX_GE_PLAT; 1514 1515 clockgen.sysclk = create_sysclk("cg-sysclk"); 1516 clockgen.coreclk = create_coreclk("cg-coreclk"); 1517 create_plls(&clockgen); 1518 create_muxes(&clockgen); 1519 1520 if (clockgen.info.init_periph) 1521 clockgen.info.init_periph(&clockgen); 1522 1523 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen); 1524 if (ret) { 1525 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1526 __func__, np, ret); 1527 } 1528 1529 /* Don't create cpufreq device for legacy clockgen blocks */ 1530 add_cpufreq_dev = !legacy; 1531 1532 return; 1533 err: 1534 iounmap(clockgen.regs); 1535 clockgen.regs = NULL; 1536 } 1537 1538 static void __init clockgen_init(struct device_node *np) 1539 { 1540 _clockgen_init(np, false); 1541 } 1542 1543 static int __init clockgen_cpufreq_init(void) 1544 { 1545 struct platform_device *pdev; 1546 1547 if (add_cpufreq_dev) { 1548 pdev = platform_device_register_simple("qoriq-cpufreq", -1, 1549 NULL, 0); 1550 if (IS_ERR(pdev)) 1551 pr_err("Couldn't register qoriq-cpufreq err=%ld\n", 1552 PTR_ERR(pdev)); 1553 } 1554 return 0; 1555 } 1556 device_initcall(clockgen_cpufreq_init); 1557 1558 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); 1559 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); 1560 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init); 1561 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init); 1562 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); 1563 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); 1564 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init); 1565 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); 1566 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); 1567 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init); 1568 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); 1569 CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init); 1570 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init); 1571 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init); 1572 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init); 1573 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init); 1574 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init); 1575 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init); 1576 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init); 1577 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init); 1578 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init); 1579 1580 /* Legacy nodes */ 1581 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); 1582 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); 1583 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); 1584 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); 1585 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); 1586 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); 1587 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); 1588 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init); 1589