1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * clock driver for Freescale QorIQ SoCs. 9 */ 10 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clkdev.h> 16 #include <linux/fsl/guts.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/of.h> 23 #include <linux/slab.h> 24 25 #define PLL_DIV1 0 26 #define PLL_DIV2 1 27 #define PLL_DIV3 2 28 #define PLL_DIV4 3 29 30 #define PLATFORM_PLL 0 31 #define CGA_PLL1 1 32 #define CGA_PLL2 2 33 #define CGA_PLL3 3 34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */ 35 #define CGB_PLL1 4 36 #define CGB_PLL2 5 37 #define MAX_PLL_DIV 16 38 39 struct clockgen_pll_div { 40 struct clk *clk; 41 char name[32]; 42 }; 43 44 struct clockgen_pll { 45 struct clockgen_pll_div div[MAX_PLL_DIV]; 46 }; 47 48 #define CLKSEL_VALID 1 49 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */ 50 51 struct clockgen_sourceinfo { 52 u32 flags; /* CLKSEL_xxx */ 53 int pll; /* CGx_PLLn */ 54 int div; /* PLL_DIVn */ 55 }; 56 57 #define NUM_MUX_PARENTS 16 58 59 struct clockgen_muxinfo { 60 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; 61 }; 62 63 #define NUM_HWACCEL 5 64 #define NUM_CMUX 8 65 66 struct clockgen; 67 68 /* 69 * cmux freq must be >= platform pll. 70 * If not set, cmux freq must be >= platform pll/2 71 */ 72 #define CG_CMUX_GE_PLAT 1 73 74 #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */ 75 #define CG_VER3 4 /* version 3 cg: reg layout different */ 76 #define CG_LITTLE_ENDIAN 8 77 78 struct clockgen_chipinfo { 79 const char *compat, *guts_compat; 80 const struct clockgen_muxinfo *cmux_groups[2]; 81 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; 82 void (*init_periph)(struct clockgen *cg); 83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */ 84 u32 pll_mask; /* 1 << n bit set if PLL n is valid */ 85 u32 flags; /* CG_xxx */ 86 }; 87 88 struct clockgen { 89 struct device_node *node; 90 void __iomem *regs; 91 struct clockgen_chipinfo info; /* mutable copy */ 92 struct clk *sysclk, *coreclk; 93 struct clockgen_pll pll[6]; 94 struct clk *cmux[NUM_CMUX]; 95 struct clk *hwaccel[NUM_HWACCEL]; 96 struct clk *fman[2]; 97 struct ccsr_guts __iomem *guts; 98 }; 99 100 static struct clockgen clockgen; 101 102 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) 103 { 104 if (cg->info.flags & CG_LITTLE_ENDIAN) 105 iowrite32(val, reg); 106 else 107 iowrite32be(val, reg); 108 } 109 110 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) 111 { 112 u32 val; 113 114 if (cg->info.flags & CG_LITTLE_ENDIAN) 115 val = ioread32(reg); 116 else 117 val = ioread32be(reg); 118 119 return val; 120 } 121 122 static const struct clockgen_muxinfo p2041_cmux_grp1 = { 123 { 124 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 125 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 126 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 127 } 128 }; 129 130 static const struct clockgen_muxinfo p2041_cmux_grp2 = { 131 { 132 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 133 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 134 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 135 } 136 }; 137 138 static const struct clockgen_muxinfo p5020_cmux_grp1 = { 139 { 140 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 141 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 142 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, 143 } 144 }; 145 146 static const struct clockgen_muxinfo p5020_cmux_grp2 = { 147 { 148 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 149 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 150 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 151 } 152 }; 153 154 static const struct clockgen_muxinfo p5040_cmux_grp1 = { 155 { 156 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 157 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 158 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, 159 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 }, 160 } 161 }; 162 163 static const struct clockgen_muxinfo p5040_cmux_grp2 = { 164 { 165 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 166 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 }, 167 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 168 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 169 } 170 }; 171 172 static const struct clockgen_muxinfo p4080_cmux_grp1 = { 173 { 174 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 175 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 176 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 177 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 178 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 }, 179 } 180 }; 181 182 static const struct clockgen_muxinfo p4080_cmux_grp2 = { 183 { 184 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, 185 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, 186 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, 187 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 }, 188 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 }, 189 } 190 }; 191 192 static const struct clockgen_muxinfo t1023_cmux = { 193 { 194 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 195 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 196 } 197 }; 198 199 static const struct clockgen_muxinfo t1040_cmux = { 200 { 201 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 202 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 203 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 204 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 205 } 206 }; 207 208 209 static const struct clockgen_muxinfo clockgen2_cmux_cga = { 210 { 211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 213 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 214 {}, 215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 217 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 218 {}, 219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, 220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, 221 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 }, 222 }, 223 }; 224 225 static const struct clockgen_muxinfo clockgen2_cmux_cga12 = { 226 { 227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 229 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 230 {}, 231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 233 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 234 }, 235 }; 236 237 static const struct clockgen_muxinfo clockgen2_cmux_cgb = { 238 { 239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 }, 240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 241 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, 242 {}, 243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 }, 244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 245 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, 246 }, 247 }; 248 249 static const struct clockgen_muxinfo ls1028a_hwa1 = { 250 { 251 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 254 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 255 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 256 {}, 257 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 258 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 259 }, 260 }; 261 262 static const struct clockgen_muxinfo ls1028a_hwa2 = { 263 { 264 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 267 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 268 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 269 {}, 270 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 271 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 272 }, 273 }; 274 275 static const struct clockgen_muxinfo ls1028a_hwa3 = { 276 { 277 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 280 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 281 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 282 {}, 283 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 284 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 285 }, 286 }; 287 288 static const struct clockgen_muxinfo ls1028a_hwa4 = { 289 { 290 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 293 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 294 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 295 {}, 296 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 297 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 298 }, 299 }; 300 301 static const struct clockgen_muxinfo ls1043a_hwa1 = { 302 { 303 {}, 304 {}, 305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 307 {}, 308 {}, 309 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 310 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 311 }, 312 }; 313 314 static const struct clockgen_muxinfo ls1043a_hwa2 = { 315 { 316 {}, 317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 318 {}, 319 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 320 }, 321 }; 322 323 static const struct clockgen_muxinfo ls1046a_hwa1 = { 324 { 325 {}, 326 {}, 327 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 328 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 329 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 330 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 331 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 332 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 333 }, 334 }; 335 336 static const struct clockgen_muxinfo ls1046a_hwa2 = { 337 { 338 {}, 339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 340 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 341 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 342 {}, 343 {}, 344 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 345 }, 346 }; 347 348 static const struct clockgen_muxinfo ls1012a_cmux = { 349 { 350 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 351 {}, 352 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 353 } 354 }; 355 356 static const struct clockgen_muxinfo t1023_hwa1 = { 357 { 358 {}, 359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 362 }, 363 }; 364 365 static const struct clockgen_muxinfo t1023_hwa2 = { 366 { 367 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 368 }, 369 }; 370 371 static const struct clockgen_muxinfo t2080_hwa1 = { 372 { 373 {}, 374 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 375 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 377 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 378 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 379 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 380 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 381 }, 382 }; 383 384 static const struct clockgen_muxinfo t2080_hwa2 = { 385 { 386 {}, 387 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, 388 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 389 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 390 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, 391 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 394 }, 395 }; 396 397 static const struct clockgen_muxinfo t4240_hwa1 = { 398 { 399 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 }, 400 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, 401 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, 402 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, 403 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, 404 {}, 405 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, 406 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, 407 }, 408 }; 409 410 static const struct clockgen_muxinfo t4240_hwa4 = { 411 { 412 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 413 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, 414 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, 415 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 416 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 417 }, 418 }; 419 420 static const struct clockgen_muxinfo t4240_hwa5 = { 421 { 422 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, 423 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 }, 424 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, 425 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, 426 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, 427 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, 428 }, 429 }; 430 431 #define RCWSR7_FM1_CLK_SEL 0x40000000 432 #define RCWSR7_FM2_CLK_SEL 0x20000000 433 #define RCWSR7_HWA_ASYNC_DIV 0x04000000 434 435 static void __init p2041_init_periph(struct clockgen *cg) 436 { 437 u32 reg; 438 439 reg = ioread32be(&cg->guts->rcwsr[7]); 440 441 if (reg & RCWSR7_FM1_CLK_SEL) 442 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; 443 else 444 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 445 } 446 447 static void __init p4080_init_periph(struct clockgen *cg) 448 { 449 u32 reg; 450 451 reg = ioread32be(&cg->guts->rcwsr[7]); 452 453 if (reg & RCWSR7_FM1_CLK_SEL) 454 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 455 else 456 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 457 458 if (reg & RCWSR7_FM2_CLK_SEL) 459 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 460 else 461 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 462 } 463 464 static void __init p5020_init_periph(struct clockgen *cg) 465 { 466 u32 reg; 467 int div = PLL_DIV2; 468 469 reg = ioread32be(&cg->guts->rcwsr[7]); 470 if (reg & RCWSR7_HWA_ASYNC_DIV) 471 div = PLL_DIV4; 472 473 if (reg & RCWSR7_FM1_CLK_SEL) 474 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; 475 else 476 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 477 } 478 479 static void __init p5040_init_periph(struct clockgen *cg) 480 { 481 u32 reg; 482 int div = PLL_DIV2; 483 484 reg = ioread32be(&cg->guts->rcwsr[7]); 485 if (reg & RCWSR7_HWA_ASYNC_DIV) 486 div = PLL_DIV4; 487 488 if (reg & RCWSR7_FM1_CLK_SEL) 489 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; 490 else 491 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 492 493 if (reg & RCWSR7_FM2_CLK_SEL) 494 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; 495 else 496 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 497 } 498 499 static void __init t1023_init_periph(struct clockgen *cg) 500 { 501 cg->fman[0] = cg->hwaccel[1]; 502 } 503 504 static void __init t1040_init_periph(struct clockgen *cg) 505 { 506 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; 507 } 508 509 static void __init t2080_init_periph(struct clockgen *cg) 510 { 511 cg->fman[0] = cg->hwaccel[0]; 512 } 513 514 static void __init t4240_init_periph(struct clockgen *cg) 515 { 516 cg->fman[0] = cg->hwaccel[3]; 517 cg->fman[1] = cg->hwaccel[4]; 518 } 519 520 static const struct clockgen_chipinfo chipinfo[] = { 521 { 522 .compat = "fsl,b4420-clockgen", 523 .guts_compat = "fsl,b4860-device-config", 524 .init_periph = t2080_init_periph, 525 .cmux_groups = { 526 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 527 }, 528 .hwaccel = { 529 &t2080_hwa1 530 }, 531 .cmux_to_group = { 532 0, 1, 1, 1, -1 533 }, 534 .pll_mask = 0x3f, 535 .flags = CG_PLL_8BIT, 536 }, 537 { 538 .compat = "fsl,b4860-clockgen", 539 .guts_compat = "fsl,b4860-device-config", 540 .init_periph = t2080_init_periph, 541 .cmux_groups = { 542 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 543 }, 544 .hwaccel = { 545 &t2080_hwa1 546 }, 547 .cmux_to_group = { 548 0, 1, 1, 1, -1 549 }, 550 .pll_mask = 0x3f, 551 .flags = CG_PLL_8BIT, 552 }, 553 { 554 .compat = "fsl,ls1021a-clockgen", 555 .cmux_groups = { 556 &t1023_cmux 557 }, 558 .cmux_to_group = { 559 0, -1 560 }, 561 .pll_mask = 0x03, 562 }, 563 { 564 .compat = "fsl,ls1028a-clockgen", 565 .cmux_groups = { 566 &clockgen2_cmux_cga12 567 }, 568 .hwaccel = { 569 &ls1028a_hwa1, &ls1028a_hwa2, 570 &ls1028a_hwa3, &ls1028a_hwa4 571 }, 572 .cmux_to_group = { 573 0, 0, 0, 0, -1 574 }, 575 .pll_mask = 0x07, 576 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 577 }, 578 { 579 .compat = "fsl,ls1043a-clockgen", 580 .init_periph = t2080_init_periph, 581 .cmux_groups = { 582 &t1040_cmux 583 }, 584 .hwaccel = { 585 &ls1043a_hwa1, &ls1043a_hwa2 586 }, 587 .cmux_to_group = { 588 0, -1 589 }, 590 .pll_mask = 0x07, 591 .flags = CG_PLL_8BIT, 592 }, 593 { 594 .compat = "fsl,ls1046a-clockgen", 595 .init_periph = t2080_init_periph, 596 .cmux_groups = { 597 &t1040_cmux 598 }, 599 .hwaccel = { 600 &ls1046a_hwa1, &ls1046a_hwa2 601 }, 602 .cmux_to_group = { 603 0, -1 604 }, 605 .pll_mask = 0x07, 606 .flags = CG_PLL_8BIT, 607 }, 608 { 609 .compat = "fsl,ls1088a-clockgen", 610 .cmux_groups = { 611 &clockgen2_cmux_cga12 612 }, 613 .cmux_to_group = { 614 0, 0, -1 615 }, 616 .pll_mask = 0x07, 617 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 618 }, 619 { 620 .compat = "fsl,ls1012a-clockgen", 621 .cmux_groups = { 622 &ls1012a_cmux 623 }, 624 .cmux_to_group = { 625 0, -1 626 }, 627 .pll_mask = 0x03, 628 }, 629 { 630 .compat = "fsl,ls2080a-clockgen", 631 .cmux_groups = { 632 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb 633 }, 634 .cmux_to_group = { 635 0, 0, 1, 1, -1 636 }, 637 .pll_mask = 0x37, 638 .flags = CG_VER3 | CG_LITTLE_ENDIAN, 639 }, 640 { 641 .compat = "fsl,p2041-clockgen", 642 .guts_compat = "fsl,qoriq-device-config-1.0", 643 .init_periph = p2041_init_periph, 644 .cmux_groups = { 645 &p2041_cmux_grp1, &p2041_cmux_grp2 646 }, 647 .cmux_to_group = { 648 0, 0, 1, 1, -1 649 }, 650 .pll_mask = 0x07, 651 }, 652 { 653 .compat = "fsl,p3041-clockgen", 654 .guts_compat = "fsl,qoriq-device-config-1.0", 655 .init_periph = p2041_init_periph, 656 .cmux_groups = { 657 &p2041_cmux_grp1, &p2041_cmux_grp2 658 }, 659 .cmux_to_group = { 660 0, 0, 1, 1, -1 661 }, 662 .pll_mask = 0x07, 663 }, 664 { 665 .compat = "fsl,p4080-clockgen", 666 .guts_compat = "fsl,qoriq-device-config-1.0", 667 .init_periph = p4080_init_periph, 668 .cmux_groups = { 669 &p4080_cmux_grp1, &p4080_cmux_grp2 670 }, 671 .cmux_to_group = { 672 0, 0, 0, 0, 1, 1, 1, 1, -1 673 }, 674 .pll_mask = 0x1f, 675 }, 676 { 677 .compat = "fsl,p5020-clockgen", 678 .guts_compat = "fsl,qoriq-device-config-1.0", 679 .init_periph = p5020_init_periph, 680 .cmux_groups = { 681 &p2041_cmux_grp1, &p2041_cmux_grp2 682 }, 683 .cmux_to_group = { 684 0, 1, -1 685 }, 686 .pll_mask = 0x07, 687 }, 688 { 689 .compat = "fsl,p5040-clockgen", 690 .guts_compat = "fsl,p5040-device-config", 691 .init_periph = p5040_init_periph, 692 .cmux_groups = { 693 &p5040_cmux_grp1, &p5040_cmux_grp2 694 }, 695 .cmux_to_group = { 696 0, 0, 1, 1, -1 697 }, 698 .pll_mask = 0x0f, 699 }, 700 { 701 .compat = "fsl,t1023-clockgen", 702 .guts_compat = "fsl,t1023-device-config", 703 .init_periph = t1023_init_periph, 704 .cmux_groups = { 705 &t1023_cmux 706 }, 707 .hwaccel = { 708 &t1023_hwa1, &t1023_hwa2 709 }, 710 .cmux_to_group = { 711 0, 0, -1 712 }, 713 .pll_mask = 0x03, 714 .flags = CG_PLL_8BIT, 715 }, 716 { 717 .compat = "fsl,t1040-clockgen", 718 .guts_compat = "fsl,t1040-device-config", 719 .init_periph = t1040_init_periph, 720 .cmux_groups = { 721 &t1040_cmux 722 }, 723 .cmux_to_group = { 724 0, 0, 0, 0, -1 725 }, 726 .pll_mask = 0x07, 727 .flags = CG_PLL_8BIT, 728 }, 729 { 730 .compat = "fsl,t2080-clockgen", 731 .guts_compat = "fsl,t2080-device-config", 732 .init_periph = t2080_init_periph, 733 .cmux_groups = { 734 &clockgen2_cmux_cga12 735 }, 736 .hwaccel = { 737 &t2080_hwa1, &t2080_hwa2 738 }, 739 .cmux_to_group = { 740 0, -1 741 }, 742 .pll_mask = 0x07, 743 .flags = CG_PLL_8BIT, 744 }, 745 { 746 .compat = "fsl,t4240-clockgen", 747 .guts_compat = "fsl,t4240-device-config", 748 .init_periph = t4240_init_periph, 749 .cmux_groups = { 750 &clockgen2_cmux_cga, &clockgen2_cmux_cgb 751 }, 752 .hwaccel = { 753 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5 754 }, 755 .cmux_to_group = { 756 0, 0, 1, -1 757 }, 758 .pll_mask = 0x3f, 759 .flags = CG_PLL_8BIT, 760 }, 761 {}, 762 }; 763 764 struct mux_hwclock { 765 struct clk_hw hw; 766 struct clockgen *cg; 767 const struct clockgen_muxinfo *info; 768 u32 __iomem *reg; 769 u8 parent_to_clksel[NUM_MUX_PARENTS]; 770 s8 clksel_to_parent[NUM_MUX_PARENTS]; 771 int num_parents; 772 }; 773 774 #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw) 775 #define CLKSEL_MASK 0x78000000 776 #define CLKSEL_SHIFT 27 777 778 static int mux_set_parent(struct clk_hw *hw, u8 idx) 779 { 780 struct mux_hwclock *hwc = to_mux_hwclock(hw); 781 u32 clksel; 782 783 if (idx >= hwc->num_parents) 784 return -EINVAL; 785 786 clksel = hwc->parent_to_clksel[idx]; 787 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); 788 789 return 0; 790 } 791 792 static u8 mux_get_parent(struct clk_hw *hw) 793 { 794 struct mux_hwclock *hwc = to_mux_hwclock(hw); 795 u32 clksel; 796 s8 ret; 797 798 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; 799 800 ret = hwc->clksel_to_parent[clksel]; 801 if (ret < 0) { 802 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); 803 return 0; 804 } 805 806 return ret; 807 } 808 809 static const struct clk_ops cmux_ops = { 810 .get_parent = mux_get_parent, 811 .set_parent = mux_set_parent, 812 }; 813 814 /* 815 * Don't allow setting for now, as the clock options haven't been 816 * sanitized for additional restrictions. 817 */ 818 static const struct clk_ops hwaccel_ops = { 819 .get_parent = mux_get_parent, 820 }; 821 822 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, 823 struct mux_hwclock *hwc, 824 int idx) 825 { 826 int pll, div; 827 828 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) 829 return NULL; 830 831 pll = hwc->info->clksel[idx].pll; 832 div = hwc->info->clksel[idx].div; 833 834 return &cg->pll[pll].div[div]; 835 } 836 837 static struct clk * __init create_mux_common(struct clockgen *cg, 838 struct mux_hwclock *hwc, 839 const struct clk_ops *ops, 840 unsigned long min_rate, 841 unsigned long max_rate, 842 unsigned long pct80_rate, 843 const char *fmt, int idx) 844 { 845 struct clk_init_data init = {}; 846 struct clk *clk; 847 const struct clockgen_pll_div *div; 848 const char *parent_names[NUM_MUX_PARENTS]; 849 char name[32]; 850 int i, j; 851 852 snprintf(name, sizeof(name), fmt, idx); 853 854 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) { 855 unsigned long rate; 856 857 hwc->clksel_to_parent[i] = -1; 858 859 div = get_pll_div(cg, hwc, i); 860 if (!div) 861 continue; 862 863 rate = clk_get_rate(div->clk); 864 865 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && 866 rate > pct80_rate) 867 continue; 868 if (rate < min_rate) 869 continue; 870 if (rate > max_rate) 871 continue; 872 873 parent_names[j] = div->name; 874 hwc->parent_to_clksel[j] = i; 875 hwc->clksel_to_parent[i] = j; 876 j++; 877 } 878 879 init.name = name; 880 init.ops = ops; 881 init.parent_names = parent_names; 882 init.num_parents = hwc->num_parents = j; 883 init.flags = 0; 884 hwc->hw.init = &init; 885 hwc->cg = cg; 886 887 clk = clk_register(NULL, &hwc->hw); 888 if (IS_ERR(clk)) { 889 pr_err("%s: Couldn't register %s: %ld\n", __func__, name, 890 PTR_ERR(clk)); 891 kfree(hwc); 892 return NULL; 893 } 894 895 return clk; 896 } 897 898 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) 899 { 900 struct mux_hwclock *hwc; 901 const struct clockgen_pll_div *div; 902 unsigned long plat_rate, min_rate; 903 u64 max_rate, pct80_rate; 904 u32 clksel; 905 906 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); 907 if (!hwc) 908 return NULL; 909 910 if (cg->info.flags & CG_VER3) 911 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; 912 else 913 hwc->reg = cg->regs + 0x20 * idx; 914 915 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; 916 917 /* 918 * Find the rate for the default clksel, and treat it as the 919 * maximum rated core frequency. If this is an incorrect 920 * assumption, certain clock options (possibly including the 921 * default clksel) may be inappropriately excluded on certain 922 * chips. 923 */ 924 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; 925 div = get_pll_div(cg, hwc, clksel); 926 if (!div) { 927 kfree(hwc); 928 return NULL; 929 } 930 931 max_rate = clk_get_rate(div->clk); 932 pct80_rate = max_rate * 8; 933 do_div(pct80_rate, 10); 934 935 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); 936 937 if (cg->info.flags & CG_CMUX_GE_PLAT) 938 min_rate = plat_rate; 939 else 940 min_rate = plat_rate / 2; 941 942 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate, 943 pct80_rate, "cg-cmux%d", idx); 944 } 945 946 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) 947 { 948 struct mux_hwclock *hwc; 949 950 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); 951 if (!hwc) 952 return NULL; 953 954 hwc->reg = cg->regs + 0x20 * idx + 0x10; 955 hwc->info = cg->info.hwaccel[idx]; 956 957 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0, 958 "cg-hwaccel%d", idx); 959 } 960 961 static void __init create_muxes(struct clockgen *cg) 962 { 963 int i; 964 965 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { 966 if (cg->info.cmux_to_group[i] < 0) 967 break; 968 if (cg->info.cmux_to_group[i] >= 969 ARRAY_SIZE(cg->info.cmux_groups)) { 970 WARN_ON_ONCE(1); 971 continue; 972 } 973 974 cg->cmux[i] = create_one_cmux(cg, i); 975 } 976 977 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { 978 if (!cg->info.hwaccel[i]) 979 continue; 980 981 cg->hwaccel[i] = create_one_hwaccel(cg, i); 982 } 983 } 984 985 static void __init clockgen_init(struct device_node *np); 986 987 /* 988 * Legacy nodes may get probed before the parent clockgen node. 989 * It is assumed that device trees with legacy nodes will not 990 * contain a "clocks" property -- otherwise the input clocks may 991 * not be initialized at this point. 992 */ 993 static void __init legacy_init_clockgen(struct device_node *np) 994 { 995 if (!clockgen.node) 996 clockgen_init(of_get_parent(np)); 997 } 998 999 /* Legacy node */ 1000 static void __init core_mux_init(struct device_node *np) 1001 { 1002 struct clk *clk; 1003 struct resource res; 1004 int idx, rc; 1005 1006 legacy_init_clockgen(np); 1007 1008 if (of_address_to_resource(np, 0, &res)) 1009 return; 1010 1011 idx = (res.start & 0xf0) >> 5; 1012 clk = clockgen.cmux[idx]; 1013 1014 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); 1015 if (rc) { 1016 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1017 __func__, np, rc); 1018 return; 1019 } 1020 } 1021 1022 static struct clk __init 1023 *sysclk_from_fixed(struct device_node *node, const char *name) 1024 { 1025 u32 rate; 1026 1027 if (of_property_read_u32(node, "clock-frequency", &rate)) 1028 return ERR_PTR(-ENODEV); 1029 1030 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 1031 } 1032 1033 static struct clk __init *input_clock(const char *name, struct clk *clk) 1034 { 1035 const char *input_name; 1036 1037 /* Register the input clock under the desired name. */ 1038 input_name = __clk_get_name(clk); 1039 clk = clk_register_fixed_factor(NULL, name, input_name, 1040 0, 1, 1); 1041 if (IS_ERR(clk)) 1042 pr_err("%s: Couldn't register %s: %ld\n", __func__, name, 1043 PTR_ERR(clk)); 1044 1045 return clk; 1046 } 1047 1048 static struct clk __init *input_clock_by_name(const char *name, 1049 const char *dtname) 1050 { 1051 struct clk *clk; 1052 1053 clk = of_clk_get_by_name(clockgen.node, dtname); 1054 if (IS_ERR(clk)) 1055 return clk; 1056 1057 return input_clock(name, clk); 1058 } 1059 1060 static struct clk __init *input_clock_by_index(const char *name, int idx) 1061 { 1062 struct clk *clk; 1063 1064 clk = of_clk_get(clockgen.node, 0); 1065 if (IS_ERR(clk)) 1066 return clk; 1067 1068 return input_clock(name, clk); 1069 } 1070 1071 static struct clk * __init create_sysclk(const char *name) 1072 { 1073 struct device_node *sysclk; 1074 struct clk *clk; 1075 1076 clk = sysclk_from_fixed(clockgen.node, name); 1077 if (!IS_ERR(clk)) 1078 return clk; 1079 1080 clk = input_clock_by_name(name, "sysclk"); 1081 if (!IS_ERR(clk)) 1082 return clk; 1083 1084 clk = input_clock_by_index(name, 0); 1085 if (!IS_ERR(clk)) 1086 return clk; 1087 1088 sysclk = of_get_child_by_name(clockgen.node, "sysclk"); 1089 if (sysclk) { 1090 clk = sysclk_from_fixed(sysclk, name); 1091 if (!IS_ERR(clk)) 1092 return clk; 1093 } 1094 1095 pr_err("%s: No input sysclk\n", __func__); 1096 return NULL; 1097 } 1098 1099 static struct clk * __init create_coreclk(const char *name) 1100 { 1101 struct clk *clk; 1102 1103 clk = input_clock_by_name(name, "coreclk"); 1104 if (!IS_ERR(clk)) 1105 return clk; 1106 1107 /* 1108 * This indicates a mix of legacy nodes with the new coreclk 1109 * mechanism, which should never happen. If this error occurs, 1110 * don't use the wrong input clock just because coreclk isn't 1111 * ready yet. 1112 */ 1113 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER)) 1114 return clk; 1115 1116 return NULL; 1117 } 1118 1119 /* Legacy node */ 1120 static void __init sysclk_init(struct device_node *node) 1121 { 1122 struct clk *clk; 1123 1124 legacy_init_clockgen(node); 1125 1126 clk = clockgen.sysclk; 1127 if (clk) 1128 of_clk_add_provider(node, of_clk_src_simple_get, clk); 1129 } 1130 1131 #define PLL_KILL BIT(31) 1132 1133 static void __init create_one_pll(struct clockgen *cg, int idx) 1134 { 1135 u32 __iomem *reg; 1136 u32 mult; 1137 struct clockgen_pll *pll = &cg->pll[idx]; 1138 const char *input = "cg-sysclk"; 1139 int i; 1140 1141 if (!(cg->info.pll_mask & (1 << idx))) 1142 return; 1143 1144 if (cg->coreclk && idx != PLATFORM_PLL) { 1145 if (IS_ERR(cg->coreclk)) 1146 return; 1147 1148 input = "cg-coreclk"; 1149 } 1150 1151 if (cg->info.flags & CG_VER3) { 1152 switch (idx) { 1153 case PLATFORM_PLL: 1154 reg = cg->regs + 0x60080; 1155 break; 1156 case CGA_PLL1: 1157 reg = cg->regs + 0x80; 1158 break; 1159 case CGA_PLL2: 1160 reg = cg->regs + 0xa0; 1161 break; 1162 case CGB_PLL1: 1163 reg = cg->regs + 0x10080; 1164 break; 1165 case CGB_PLL2: 1166 reg = cg->regs + 0x100a0; 1167 break; 1168 default: 1169 WARN_ONCE(1, "index %d\n", idx); 1170 return; 1171 } 1172 } else { 1173 if (idx == PLATFORM_PLL) 1174 reg = cg->regs + 0xc00; 1175 else 1176 reg = cg->regs + 0x800 + 0x20 * (idx - 1); 1177 } 1178 1179 /* Get the multiple of PLL */ 1180 mult = cg_in(cg, reg); 1181 1182 /* Check if this PLL is disabled */ 1183 if (mult & PLL_KILL) { 1184 pr_debug("%s(): pll %p disabled\n", __func__, reg); 1185 return; 1186 } 1187 1188 if ((cg->info.flags & CG_VER3) || 1189 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) 1190 mult = (mult & GENMASK(8, 1)) >> 1; 1191 else 1192 mult = (mult & GENMASK(6, 1)) >> 1; 1193 1194 for (i = 0; i < ARRAY_SIZE(pll->div); i++) { 1195 struct clk *clk; 1196 int ret; 1197 1198 /* 1199 * For platform PLL, there are MAX_PLL_DIV divider clocks. 1200 * For core PLL, there are 4 divider clocks at most. 1201 */ 1202 if (idx != PLATFORM_PLL && i >= 4) 1203 break; 1204 1205 snprintf(pll->div[i].name, sizeof(pll->div[i].name), 1206 "cg-pll%d-div%d", idx, i + 1); 1207 1208 clk = clk_register_fixed_factor(NULL, 1209 pll->div[i].name, input, 0, mult, i + 1); 1210 if (IS_ERR(clk)) { 1211 pr_err("%s: %s: register failed %ld\n", 1212 __func__, pll->div[i].name, PTR_ERR(clk)); 1213 continue; 1214 } 1215 1216 pll->div[i].clk = clk; 1217 ret = clk_register_clkdev(clk, pll->div[i].name, NULL); 1218 if (ret != 0) 1219 pr_err("%s: %s: register to lookup table failed %d\n", 1220 __func__, pll->div[i].name, ret); 1221 1222 } 1223 } 1224 1225 static void __init create_plls(struct clockgen *cg) 1226 { 1227 int i; 1228 1229 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) 1230 create_one_pll(cg, i); 1231 } 1232 1233 static void __init legacy_pll_init(struct device_node *np, int idx) 1234 { 1235 struct clockgen_pll *pll; 1236 struct clk_onecell_data *onecell_data; 1237 struct clk **subclks; 1238 int count, rc; 1239 1240 legacy_init_clockgen(np); 1241 1242 pll = &clockgen.pll[idx]; 1243 count = of_property_count_strings(np, "clock-output-names"); 1244 1245 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); 1246 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); 1247 if (!subclks) 1248 return; 1249 1250 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL); 1251 if (!onecell_data) 1252 goto err_clks; 1253 1254 if (count <= 3) { 1255 subclks[0] = pll->div[0].clk; 1256 subclks[1] = pll->div[1].clk; 1257 subclks[2] = pll->div[3].clk; 1258 } else { 1259 subclks[0] = pll->div[0].clk; 1260 subclks[1] = pll->div[1].clk; 1261 subclks[2] = pll->div[2].clk; 1262 subclks[3] = pll->div[3].clk; 1263 } 1264 1265 onecell_data->clks = subclks; 1266 onecell_data->clk_num = count; 1267 1268 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); 1269 if (rc) { 1270 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1271 __func__, np, rc); 1272 goto err_cell; 1273 } 1274 1275 return; 1276 err_cell: 1277 kfree(onecell_data); 1278 err_clks: 1279 kfree(subclks); 1280 } 1281 1282 /* Legacy node */ 1283 static void __init pltfrm_pll_init(struct device_node *np) 1284 { 1285 legacy_pll_init(np, PLATFORM_PLL); 1286 } 1287 1288 /* Legacy node */ 1289 static void __init core_pll_init(struct device_node *np) 1290 { 1291 struct resource res; 1292 int idx; 1293 1294 if (of_address_to_resource(np, 0, &res)) 1295 return; 1296 1297 if ((res.start & 0xfff) == 0xc00) { 1298 /* 1299 * ls1021a devtree labels the platform PLL 1300 * with the core PLL compatible 1301 */ 1302 pltfrm_pll_init(np); 1303 } else { 1304 idx = (res.start & 0xf0) >> 5; 1305 legacy_pll_init(np, CGA_PLL1 + idx); 1306 } 1307 } 1308 1309 static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) 1310 { 1311 struct clockgen *cg = data; 1312 struct clk *clk; 1313 struct clockgen_pll *pll; 1314 u32 type, idx; 1315 1316 if (clkspec->args_count < 2) { 1317 pr_err("%s: insufficient phandle args\n", __func__); 1318 return ERR_PTR(-EINVAL); 1319 } 1320 1321 type = clkspec->args[0]; 1322 idx = clkspec->args[1]; 1323 1324 switch (type) { 1325 case 0: 1326 if (idx != 0) 1327 goto bad_args; 1328 clk = cg->sysclk; 1329 break; 1330 case 1: 1331 if (idx >= ARRAY_SIZE(cg->cmux)) 1332 goto bad_args; 1333 clk = cg->cmux[idx]; 1334 break; 1335 case 2: 1336 if (idx >= ARRAY_SIZE(cg->hwaccel)) 1337 goto bad_args; 1338 clk = cg->hwaccel[idx]; 1339 break; 1340 case 3: 1341 if (idx >= ARRAY_SIZE(cg->fman)) 1342 goto bad_args; 1343 clk = cg->fman[idx]; 1344 break; 1345 case 4: 1346 pll = &cg->pll[PLATFORM_PLL]; 1347 if (idx >= ARRAY_SIZE(pll->div)) 1348 goto bad_args; 1349 clk = pll->div[idx].clk; 1350 break; 1351 case 5: 1352 if (idx != 0) 1353 goto bad_args; 1354 clk = cg->coreclk; 1355 if (IS_ERR(clk)) 1356 clk = NULL; 1357 break; 1358 default: 1359 goto bad_args; 1360 } 1361 1362 if (!clk) 1363 return ERR_PTR(-ENOENT); 1364 return clk; 1365 1366 bad_args: 1367 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx); 1368 return ERR_PTR(-EINVAL); 1369 } 1370 1371 #ifdef CONFIG_PPC 1372 #include <asm/mpc85xx.h> 1373 1374 static const u32 a4510_svrs[] __initconst = { 1375 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ 1376 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */ 1377 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */ 1378 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */ 1379 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */ 1380 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */ 1381 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */ 1382 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */ 1383 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */ 1384 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */ 1385 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */ 1386 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */ 1387 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */ 1388 }; 1389 1390 #define SVR_SECURITY 0x80000 /* The Security (E) bit */ 1391 1392 static bool __init has_erratum_a4510(void) 1393 { 1394 u32 svr = mfspr(SPRN_SVR); 1395 int i; 1396 1397 svr &= ~SVR_SECURITY; 1398 1399 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) { 1400 if (svr == a4510_svrs[i]) 1401 return true; 1402 } 1403 1404 return false; 1405 } 1406 #else 1407 static bool __init has_erratum_a4510(void) 1408 { 1409 return false; 1410 } 1411 #endif 1412 1413 static void __init clockgen_init(struct device_node *np) 1414 { 1415 int i, ret; 1416 bool is_old_ls1021a = false; 1417 1418 /* May have already been called by a legacy probe */ 1419 if (clockgen.node) 1420 return; 1421 1422 clockgen.node = np; 1423 clockgen.regs = of_iomap(np, 0); 1424 if (!clockgen.regs && 1425 of_device_is_compatible(of_root, "fsl,ls1021a")) { 1426 /* Compatibility hack for old, broken device trees */ 1427 clockgen.regs = ioremap(0x1ee1000, 0x1000); 1428 is_old_ls1021a = true; 1429 } 1430 if (!clockgen.regs) { 1431 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np); 1432 return; 1433 } 1434 1435 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) { 1436 if (of_device_is_compatible(np, chipinfo[i].compat)) 1437 break; 1438 if (is_old_ls1021a && 1439 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) 1440 break; 1441 } 1442 1443 if (i == ARRAY_SIZE(chipinfo)) { 1444 pr_err("%s: unknown clockgen node %pOF\n", __func__, np); 1445 goto err; 1446 } 1447 clockgen.info = chipinfo[i]; 1448 1449 if (clockgen.info.guts_compat) { 1450 struct device_node *guts; 1451 1452 guts = of_find_compatible_node(NULL, NULL, 1453 clockgen.info.guts_compat); 1454 if (guts) { 1455 clockgen.guts = of_iomap(guts, 0); 1456 if (!clockgen.guts) { 1457 pr_err("%s: Couldn't map %pOF regs\n", __func__, 1458 guts); 1459 } 1460 of_node_put(guts); 1461 } 1462 1463 } 1464 1465 if (has_erratum_a4510()) 1466 clockgen.info.flags |= CG_CMUX_GE_PLAT; 1467 1468 clockgen.sysclk = create_sysclk("cg-sysclk"); 1469 clockgen.coreclk = create_coreclk("cg-coreclk"); 1470 create_plls(&clockgen); 1471 create_muxes(&clockgen); 1472 1473 if (clockgen.info.init_periph) 1474 clockgen.info.init_periph(&clockgen); 1475 1476 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen); 1477 if (ret) { 1478 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n", 1479 __func__, np, ret); 1480 } 1481 1482 return; 1483 err: 1484 iounmap(clockgen.regs); 1485 clockgen.regs = NULL; 1486 } 1487 1488 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); 1489 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); 1490 CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init); 1491 CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init); 1492 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); 1493 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); 1494 CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init); 1495 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); 1496 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); 1497 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init); 1498 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); 1499 CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init); 1500 CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init); 1501 CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init); 1502 CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init); 1503 CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init); 1504 CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init); 1505 CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init); 1506 CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init); 1507 CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init); 1508 1509 /* Legacy nodes */ 1510 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); 1511 CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); 1512 CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); 1513 CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); 1514 CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); 1515 CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); 1516 CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); 1517 CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init); 1518