1 /* 2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> 4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Simple multiplexer clock implementation 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 #include <linux/err.h> 18 19 /* 20 * DOC: basic adjustable multiplexer clock that cannot gate 21 * 22 * Traits of this clock: 23 * prepare - clk_prepare only ensures that parents are prepared 24 * enable - clk_enable only ensures that parents are enabled 25 * rate - rate is only affected by parent switching. No clk_set_rate support 26 * parent - parent is adjustable through clk_set_parent 27 */ 28 29 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 30 31 static u8 clk_mux_get_parent(struct clk_hw *hw) 32 { 33 struct clk_mux *mux = to_clk_mux(hw); 34 int num_parents = clk_hw_get_num_parents(hw); 35 u32 val; 36 37 /* 38 * FIXME need a mux-specific flag to determine if val is bitwise or numeric 39 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 40 * to 0x7 (index starts at one) 41 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so 42 * val = 0x4 really means "bit 2, index starts at bit 0" 43 */ 44 val = clk_readl(mux->reg) >> mux->shift; 45 val &= mux->mask; 46 47 if (mux->table) { 48 int i; 49 50 for (i = 0; i < num_parents; i++) 51 if (mux->table[i] == val) 52 return i; 53 return -EINVAL; 54 } 55 56 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) 57 val = ffs(val) - 1; 58 59 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) 60 val--; 61 62 if (val >= num_parents) 63 return -EINVAL; 64 65 return val; 66 } 67 68 static int clk_mux_set_parent(struct clk_hw *hw, u8 index) 69 { 70 struct clk_mux *mux = to_clk_mux(hw); 71 u32 val; 72 unsigned long flags = 0; 73 74 if (mux->table) 75 index = mux->table[index]; 76 77 else { 78 if (mux->flags & CLK_MUX_INDEX_BIT) 79 index = 1 << index; 80 81 if (mux->flags & CLK_MUX_INDEX_ONE) 82 index++; 83 } 84 85 if (mux->lock) 86 spin_lock_irqsave(mux->lock, flags); 87 else 88 __acquire(mux->lock); 89 90 if (mux->flags & CLK_MUX_HIWORD_MASK) { 91 val = mux->mask << (mux->shift + 16); 92 } else { 93 val = clk_readl(mux->reg); 94 val &= ~(mux->mask << mux->shift); 95 } 96 val |= index << mux->shift; 97 clk_writel(val, mux->reg); 98 99 if (mux->lock) 100 spin_unlock_irqrestore(mux->lock, flags); 101 else 102 __release(mux->lock); 103 104 return 0; 105 } 106 107 const struct clk_ops clk_mux_ops = { 108 .get_parent = clk_mux_get_parent, 109 .set_parent = clk_mux_set_parent, 110 .determine_rate = __clk_mux_determine_rate, 111 }; 112 EXPORT_SYMBOL_GPL(clk_mux_ops); 113 114 const struct clk_ops clk_mux_ro_ops = { 115 .get_parent = clk_mux_get_parent, 116 }; 117 EXPORT_SYMBOL_GPL(clk_mux_ro_ops); 118 119 struct clk *clk_register_mux_table(struct device *dev, const char *name, 120 const char * const *parent_names, u8 num_parents, 121 unsigned long flags, 122 void __iomem *reg, u8 shift, u32 mask, 123 u8 clk_mux_flags, u32 *table, spinlock_t *lock) 124 { 125 struct clk_mux *mux; 126 struct clk *clk; 127 struct clk_init_data init; 128 u8 width = 0; 129 130 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { 131 width = fls(mask) - ffs(mask) + 1; 132 if (width + shift > 16) { 133 pr_err("mux value exceeds LOWORD field\n"); 134 return ERR_PTR(-EINVAL); 135 } 136 } 137 138 /* allocate the mux */ 139 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 140 if (!mux) { 141 pr_err("%s: could not allocate mux clk\n", __func__); 142 return ERR_PTR(-ENOMEM); 143 } 144 145 init.name = name; 146 if (clk_mux_flags & CLK_MUX_READ_ONLY) 147 init.ops = &clk_mux_ro_ops; 148 else 149 init.ops = &clk_mux_ops; 150 init.flags = flags | CLK_IS_BASIC; 151 init.parent_names = parent_names; 152 init.num_parents = num_parents; 153 154 /* struct clk_mux assignments */ 155 mux->reg = reg; 156 mux->shift = shift; 157 mux->mask = mask; 158 mux->flags = clk_mux_flags; 159 mux->lock = lock; 160 mux->table = table; 161 mux->hw.init = &init; 162 163 clk = clk_register(dev, &mux->hw); 164 165 if (IS_ERR(clk)) 166 kfree(mux); 167 168 return clk; 169 } 170 EXPORT_SYMBOL_GPL(clk_register_mux_table); 171 172 struct clk *clk_register_mux(struct device *dev, const char *name, 173 const char * const *parent_names, u8 num_parents, 174 unsigned long flags, 175 void __iomem *reg, u8 shift, u8 width, 176 u8 clk_mux_flags, spinlock_t *lock) 177 { 178 u32 mask = BIT(width) - 1; 179 180 return clk_register_mux_table(dev, name, parent_names, num_parents, 181 flags, reg, shift, mask, clk_mux_flags, 182 NULL, lock); 183 } 184 EXPORT_SYMBOL_GPL(clk_register_mux); 185 186 void clk_unregister_mux(struct clk *clk) 187 { 188 struct clk_mux *mux; 189 struct clk_hw *hw; 190 191 hw = __clk_get_hw(clk); 192 if (!hw) 193 return; 194 195 mux = to_clk_mux(hw); 196 197 clk_unregister(clk); 198 kfree(mux); 199 } 200 EXPORT_SYMBOL_GPL(clk_unregister_mux); 201