19d9f78edSMike Turquette /* 29d9f78edSMike Turquette * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 39d9f78edSMike Turquette * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> 49d9f78edSMike Turquette * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 59d9f78edSMike Turquette * 69d9f78edSMike Turquette * This program is free software; you can redistribute it and/or modify 79d9f78edSMike Turquette * it under the terms of the GNU General Public License version 2 as 89d9f78edSMike Turquette * published by the Free Software Foundation. 99d9f78edSMike Turquette * 109d9f78edSMike Turquette * Simple multiplexer clock implementation 119d9f78edSMike Turquette */ 129d9f78edSMike Turquette 139d9f78edSMike Turquette #include <linux/clk.h> 149d9f78edSMike Turquette #include <linux/clk-provider.h> 159d9f78edSMike Turquette #include <linux/module.h> 169d9f78edSMike Turquette #include <linux/slab.h> 179d9f78edSMike Turquette #include <linux/io.h> 189d9f78edSMike Turquette #include <linux/err.h> 199d9f78edSMike Turquette 209d9f78edSMike Turquette /* 219d9f78edSMike Turquette * DOC: basic adjustable multiplexer clock that cannot gate 229d9f78edSMike Turquette * 239d9f78edSMike Turquette * Traits of this clock: 249d9f78edSMike Turquette * prepare - clk_prepare only ensures that parents are prepared 259d9f78edSMike Turquette * enable - clk_enable only ensures that parents are enabled 269d9f78edSMike Turquette * rate - rate is only affected by parent switching. No clk_set_rate support 279d9f78edSMike Turquette * parent - parent is adjustable through clk_set_parent 289d9f78edSMike Turquette */ 299d9f78edSMike Turquette 309d9f78edSMike Turquette #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 319d9f78edSMike Turquette 329d9f78edSMike Turquette static u8 clk_mux_get_parent(struct clk_hw *hw) 339d9f78edSMike Turquette { 349d9f78edSMike Turquette struct clk_mux *mux = to_clk_mux(hw); 35ce4f3313SPeter De Schrijver int num_parents = __clk_get_num_parents(hw->clk); 369d9f78edSMike Turquette u32 val; 379d9f78edSMike Turquette 389d9f78edSMike Turquette /* 399d9f78edSMike Turquette * FIXME need a mux-specific flag to determine if val is bitwise or numeric 409d9f78edSMike Turquette * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 419d9f78edSMike Turquette * to 0x7 (index starts at one) 429d9f78edSMike Turquette * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so 439d9f78edSMike Turquette * val = 0x4 really means "bit 2, index starts at bit 0" 449d9f78edSMike Turquette */ 459d9f78edSMike Turquette val = readl(mux->reg) >> mux->shift; 46ce4f3313SPeter De Schrijver val &= mux->mask; 47ce4f3313SPeter De Schrijver 48ce4f3313SPeter De Schrijver if (mux->table) { 49ce4f3313SPeter De Schrijver int i; 50ce4f3313SPeter De Schrijver 51ce4f3313SPeter De Schrijver for (i = 0; i < num_parents; i++) 52ce4f3313SPeter De Schrijver if (mux->table[i] == val) 53ce4f3313SPeter De Schrijver return i; 54ce4f3313SPeter De Schrijver return -EINVAL; 55ce4f3313SPeter De Schrijver } 569d9f78edSMike Turquette 579d9f78edSMike Turquette if (val && (mux->flags & CLK_MUX_INDEX_BIT)) 589d9f78edSMike Turquette val = ffs(val) - 1; 599d9f78edSMike Turquette 609d9f78edSMike Turquette if (val && (mux->flags & CLK_MUX_INDEX_ONE)) 619d9f78edSMike Turquette val--; 629d9f78edSMike Turquette 63ce4f3313SPeter De Schrijver if (val >= num_parents) 649d9f78edSMike Turquette return -EINVAL; 659d9f78edSMike Turquette 669d9f78edSMike Turquette return val; 679d9f78edSMike Turquette } 689d9f78edSMike Turquette 699d9f78edSMike Turquette static int clk_mux_set_parent(struct clk_hw *hw, u8 index) 709d9f78edSMike Turquette { 719d9f78edSMike Turquette struct clk_mux *mux = to_clk_mux(hw); 729d9f78edSMike Turquette u32 val; 739d9f78edSMike Turquette unsigned long flags = 0; 749d9f78edSMike Turquette 75ce4f3313SPeter De Schrijver if (mux->table) 76ce4f3313SPeter De Schrijver index = mux->table[index]; 77ce4f3313SPeter De Schrijver 78ce4f3313SPeter De Schrijver else { 799d9f78edSMike Turquette if (mux->flags & CLK_MUX_INDEX_BIT) 809d9f78edSMike Turquette index = (1 << ffs(index)); 819d9f78edSMike Turquette 829d9f78edSMike Turquette if (mux->flags & CLK_MUX_INDEX_ONE) 839d9f78edSMike Turquette index++; 84ce4f3313SPeter De Schrijver } 859d9f78edSMike Turquette 869d9f78edSMike Turquette if (mux->lock) 879d9f78edSMike Turquette spin_lock_irqsave(mux->lock, flags); 889d9f78edSMike Turquette 899d9f78edSMike Turquette val = readl(mux->reg); 90ce4f3313SPeter De Schrijver val &= ~(mux->mask << mux->shift); 919d9f78edSMike Turquette val |= index << mux->shift; 929d9f78edSMike Turquette writel(val, mux->reg); 939d9f78edSMike Turquette 949d9f78edSMike Turquette if (mux->lock) 959d9f78edSMike Turquette spin_unlock_irqrestore(mux->lock, flags); 969d9f78edSMike Turquette 979d9f78edSMike Turquette return 0; 989d9f78edSMike Turquette } 999d9f78edSMike Turquette 100822c250eSShawn Guo const struct clk_ops clk_mux_ops = { 1019d9f78edSMike Turquette .get_parent = clk_mux_get_parent, 1029d9f78edSMike Turquette .set_parent = clk_mux_set_parent, 1039d9f78edSMike Turquette }; 1049d9f78edSMike Turquette EXPORT_SYMBOL_GPL(clk_mux_ops); 1059d9f78edSMike Turquette 106ce4f3313SPeter De Schrijver struct clk *clk_register_mux_table(struct device *dev, const char *name, 107d305fb78SMark Brown const char **parent_names, u8 num_parents, unsigned long flags, 108ce4f3313SPeter De Schrijver void __iomem *reg, u8 shift, u32 mask, 109ce4f3313SPeter De Schrijver u8 clk_mux_flags, u32 *table, spinlock_t *lock) 1109d9f78edSMike Turquette { 1119d9f78edSMike Turquette struct clk_mux *mux; 11227d54591SMike Turquette struct clk *clk; 1130197b3eaSSaravana Kannan struct clk_init_data init; 1149d9f78edSMike Turquette 11527d54591SMike Turquette /* allocate the mux */ 11610363b58SShawn Guo mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 1179d9f78edSMike Turquette if (!mux) { 1189d9f78edSMike Turquette pr_err("%s: could not allocate mux clk\n", __func__); 1199d9f78edSMike Turquette return ERR_PTR(-ENOMEM); 1209d9f78edSMike Turquette } 1219d9f78edSMike Turquette 1220197b3eaSSaravana Kannan init.name = name; 1230197b3eaSSaravana Kannan init.ops = &clk_mux_ops; 124f7d8caadSRajendra Nayak init.flags = flags | CLK_IS_BASIC; 1250197b3eaSSaravana Kannan init.parent_names = parent_names; 1260197b3eaSSaravana Kannan init.num_parents = num_parents; 1270197b3eaSSaravana Kannan 1289d9f78edSMike Turquette /* struct clk_mux assignments */ 1299d9f78edSMike Turquette mux->reg = reg; 1309d9f78edSMike Turquette mux->shift = shift; 131ce4f3313SPeter De Schrijver mux->mask = mask; 1329d9f78edSMike Turquette mux->flags = clk_mux_flags; 1339d9f78edSMike Turquette mux->lock = lock; 134ce4f3313SPeter De Schrijver mux->table = table; 13531df9db9SMike Turquette mux->hw.init = &init; 1369d9f78edSMike Turquette 1370197b3eaSSaravana Kannan clk = clk_register(dev, &mux->hw); 13827d54591SMike Turquette 13927d54591SMike Turquette if (IS_ERR(clk)) 14027d54591SMike Turquette kfree(mux); 14127d54591SMike Turquette 14227d54591SMike Turquette return clk; 1439d9f78edSMike Turquette } 144ce4f3313SPeter De Schrijver 145ce4f3313SPeter De Schrijver struct clk *clk_register_mux(struct device *dev, const char *name, 146ce4f3313SPeter De Schrijver const char **parent_names, u8 num_parents, unsigned long flags, 147ce4f3313SPeter De Schrijver void __iomem *reg, u8 shift, u8 width, 148ce4f3313SPeter De Schrijver u8 clk_mux_flags, spinlock_t *lock) 149ce4f3313SPeter De Schrijver { 150ce4f3313SPeter De Schrijver u32 mask = BIT(width) - 1; 151ce4f3313SPeter De Schrijver 152ce4f3313SPeter De Schrijver return clk_register_mux_table(dev, name, parent_names, num_parents, 153ce4f3313SPeter De Schrijver flags, reg, shift, mask, clk_mux_flags, 154ce4f3313SPeter De Schrijver NULL, lock); 155ce4f3313SPeter De Schrijver } 156