1 /* 2 * Cortina Gemini SoC Clock Controller driver 3 * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org> 4 */ 5 6 #define pr_fmt(fmt) "clk-gemini: " fmt 7 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/clk-provider.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/regmap.h> 19 #include <linux/spinlock.h> 20 #include <linux/reset-controller.h> 21 #include <dt-bindings/reset/cortina,gemini-reset.h> 22 #include <dt-bindings/clock/cortina,gemini-clock.h> 23 24 /* Globally visible clocks */ 25 static DEFINE_SPINLOCK(gemini_clk_lock); 26 27 #define GEMINI_GLOBAL_STATUS 0x04 28 #define PLL_OSC_SEL BIT(30) 29 #define AHBSPEED_SHIFT (15) 30 #define AHBSPEED_MASK 0x07 31 #define CPU_AHB_RATIO_SHIFT (18) 32 #define CPU_AHB_RATIO_MASK 0x03 33 34 #define GEMINI_GLOBAL_PLL_CONTROL 0x08 35 36 #define GEMINI_GLOBAL_SOFT_RESET 0x0c 37 38 #define GEMINI_GLOBAL_MISC_CONTROL 0x30 39 #define PCI_CLK_66MHZ BIT(18) 40 41 #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34 42 #define PCI_CLKRUN_EN BIT(16) 43 #define TVC_HALFDIV_SHIFT (24) 44 #define TVC_HALFDIV_MASK 0x1f 45 #define SECURITY_CLK_SEL BIT(29) 46 47 #define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44 48 #define PCI_DLL_BYPASS BIT(31) 49 #define PCI_DLL_TAP_SEL_MASK 0x1f 50 51 /** 52 * struct gemini_data_data - Gemini gated clocks 53 * @bit_idx: the bit used to gate this clock in the clock register 54 * @name: the clock name 55 * @parent_name: the name of the parent clock 56 * @flags: standard clock framework flags 57 */ 58 struct gemini_gate_data { 59 u8 bit_idx; 60 const char *name; 61 const char *parent_name; 62 unsigned long flags; 63 }; 64 65 /** 66 * struct clk_gemini_pci - Gemini PCI clock 67 * @hw: corresponding clock hardware entry 68 * @map: regmap to access the registers 69 * @rate: current rate 70 */ 71 struct clk_gemini_pci { 72 struct clk_hw hw; 73 struct regmap *map; 74 unsigned long rate; 75 }; 76 77 /** 78 * struct gemini_reset - gemini reset controller 79 * @map: regmap to access the containing system controller 80 * @rcdev: reset controller device 81 */ 82 struct gemini_reset { 83 struct regmap *map; 84 struct reset_controller_dev rcdev; 85 }; 86 87 /* Keeps track of all clocks */ 88 static struct clk_hw_onecell_data *gemini_clk_data; 89 90 static const struct gemini_gate_data gemini_gates[] = { 91 { 1, "security-gate", "secdiv", 0 }, 92 { 2, "gmac0-gate", "ahb", 0 }, 93 { 3, "gmac1-gate", "ahb", 0 }, 94 { 4, "sata0-gate", "ahb", 0 }, 95 { 5, "sata1-gate", "ahb", 0 }, 96 { 6, "usb0-gate", "ahb", 0 }, 97 { 7, "usb1-gate", "ahb", 0 }, 98 { 8, "ide-gate", "ahb", 0 }, 99 { 9, "pci-gate", "ahb", 0 }, 100 /* 101 * The DDR controller may never have a driver, but certainly must 102 * not be gated off. 103 */ 104 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL }, 105 /* 106 * The flash controller must be on to access NOR flash through the 107 * memory map. 108 */ 109 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED }, 110 { 12, "tvc-gate", "ahb", 0 }, 111 { 13, "boot-gate", "apb", 0 }, 112 }; 113 114 #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw) 115 116 #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev) 117 118 static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw, 119 unsigned long parent_rate) 120 { 121 struct clk_gemini_pci *pciclk = to_pciclk(hw); 122 u32 val; 123 124 regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val); 125 if (val & PCI_CLK_66MHZ) 126 return 66000000; 127 return 33000000; 128 } 129 130 static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate, 131 unsigned long *prate) 132 { 133 /* We support 33 and 66 MHz */ 134 if (rate < 48000000) 135 return 33000000; 136 return 66000000; 137 } 138 139 static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate, 140 unsigned long parent_rate) 141 { 142 struct clk_gemini_pci *pciclk = to_pciclk(hw); 143 144 if (rate == 33000000) 145 return regmap_update_bits(pciclk->map, 146 GEMINI_GLOBAL_MISC_CONTROL, 147 PCI_CLK_66MHZ, 0); 148 if (rate == 66000000) 149 return regmap_update_bits(pciclk->map, 150 GEMINI_GLOBAL_MISC_CONTROL, 151 0, PCI_CLK_66MHZ); 152 return -EINVAL; 153 } 154 155 static int gemini_pci_enable(struct clk_hw *hw) 156 { 157 struct clk_gemini_pci *pciclk = to_pciclk(hw); 158 159 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, 160 0, PCI_CLKRUN_EN); 161 return 0; 162 } 163 164 static void gemini_pci_disable(struct clk_hw *hw) 165 { 166 struct clk_gemini_pci *pciclk = to_pciclk(hw); 167 168 regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, 169 PCI_CLKRUN_EN, 0); 170 } 171 172 static int gemini_pci_is_enabled(struct clk_hw *hw) 173 { 174 struct clk_gemini_pci *pciclk = to_pciclk(hw); 175 unsigned int val; 176 177 regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); 178 return !!(val & PCI_CLKRUN_EN); 179 } 180 181 static const struct clk_ops gemini_pci_clk_ops = { 182 .recalc_rate = gemini_pci_recalc_rate, 183 .round_rate = gemini_pci_round_rate, 184 .set_rate = gemini_pci_set_rate, 185 .enable = gemini_pci_enable, 186 .disable = gemini_pci_disable, 187 .is_enabled = gemini_pci_is_enabled, 188 }; 189 190 static struct clk_hw *gemini_pci_clk_setup(const char *name, 191 const char *parent_name, 192 struct regmap *map) 193 { 194 struct clk_gemini_pci *pciclk; 195 struct clk_init_data init; 196 int ret; 197 198 pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL); 199 if (!pciclk) 200 return ERR_PTR(-ENOMEM); 201 202 init.name = name; 203 init.ops = &gemini_pci_clk_ops; 204 init.flags = 0; 205 init.parent_names = &parent_name; 206 init.num_parents = 1; 207 pciclk->map = map; 208 pciclk->hw.init = &init; 209 210 ret = clk_hw_register(NULL, &pciclk->hw); 211 if (ret) { 212 kfree(pciclk); 213 return ERR_PTR(ret); 214 } 215 216 return &pciclk->hw; 217 } 218 219 /* 220 * This is a self-deasserting reset controller. 221 */ 222 static int gemini_reset(struct reset_controller_dev *rcdev, 223 unsigned long id) 224 { 225 struct gemini_reset *gr = to_gemini_reset(rcdev); 226 227 /* Manual says to always set BIT 30 (CPU1) to 1 */ 228 return regmap_write(gr->map, 229 GEMINI_GLOBAL_SOFT_RESET, 230 BIT(GEMINI_RESET_CPU1) | BIT(id)); 231 } 232 233 static int gemini_reset_assert(struct reset_controller_dev *rcdev, 234 unsigned long id) 235 { 236 return 0; 237 } 238 239 static int gemini_reset_deassert(struct reset_controller_dev *rcdev, 240 unsigned long id) 241 { 242 return 0; 243 } 244 245 static int gemini_reset_status(struct reset_controller_dev *rcdev, 246 unsigned long id) 247 { 248 struct gemini_reset *gr = to_gemini_reset(rcdev); 249 u32 val; 250 int ret; 251 252 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); 253 if (ret) 254 return ret; 255 256 return !!(val & BIT(id)); 257 } 258 259 static const struct reset_control_ops gemini_reset_ops = { 260 .reset = gemini_reset, 261 .assert = gemini_reset_assert, 262 .deassert = gemini_reset_deassert, 263 .status = gemini_reset_status, 264 }; 265 266 static int gemini_clk_probe(struct platform_device *pdev) 267 { 268 /* Gives the fracions 1x, 1.5x, 1.85x and 2x */ 269 unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 }; 270 unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 }; 271 void __iomem *base; 272 struct gemini_reset *gr; 273 struct regmap *map; 274 struct clk_hw *hw; 275 struct device *dev = &pdev->dev; 276 struct device_node *np = dev->of_node; 277 unsigned int mult, div; 278 struct resource *res; 279 u32 val; 280 int ret; 281 int i; 282 283 gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL); 284 if (!gr) 285 return -ENOMEM; 286 287 /* Remap the system controller for the exclusive register */ 288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 289 base = devm_ioremap_resource(dev, res); 290 if (IS_ERR(base)) 291 return PTR_ERR(base); 292 293 map = syscon_node_to_regmap(np); 294 if (IS_ERR(map)) { 295 dev_err(dev, "no syscon regmap\n"); 296 return PTR_ERR(map); 297 } 298 299 gr->map = map; 300 gr->rcdev.owner = THIS_MODULE; 301 gr->rcdev.nr_resets = 32; 302 gr->rcdev.ops = &gemini_reset_ops; 303 gr->rcdev.of_node = np; 304 305 ret = devm_reset_controller_register(dev, &gr->rcdev); 306 if (ret) { 307 dev_err(dev, "could not register reset controller\n"); 308 return ret; 309 } 310 311 /* RTC clock 32768 Hz */ 312 hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768); 313 gemini_clk_data->hws[GEMINI_CLK_RTC] = hw; 314 315 /* CPU clock derived as a fixed ratio from the AHB clock */ 316 regmap_read(map, GEMINI_GLOBAL_STATUS, &val); 317 val >>= CPU_AHB_RATIO_SHIFT; 318 val &= CPU_AHB_RATIO_MASK; 319 hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0, 320 cpu_ahb_mult[val], 321 cpu_ahb_div[val]); 322 gemini_clk_data->hws[GEMINI_CLK_CPU] = hw; 323 324 /* Security clock is 1:1 or 0.75 of APB */ 325 regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); 326 if (val & SECURITY_CLK_SEL) { 327 mult = 1; 328 div = 1; 329 } else { 330 mult = 3; 331 div = 4; 332 } 333 hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div); 334 335 /* 336 * These are the leaf gates, at boot no clocks are gated. 337 */ 338 for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) { 339 const struct gemini_gate_data *gd; 340 341 gd = &gemini_gates[i]; 342 gemini_clk_data->hws[GEMINI_CLK_GATES + i] = 343 clk_hw_register_gate(NULL, gd->name, 344 gd->parent_name, 345 gd->flags, 346 base + GEMINI_GLOBAL_CLOCK_CONTROL, 347 gd->bit_idx, 348 CLK_GATE_SET_TO_DISABLE, 349 &gemini_clk_lock); 350 } 351 352 /* 353 * The TV Interface Controller has a 5-bit half divider register. 354 * This clock is supposed to be 27MHz as this is an exact multiple 355 * of PAL and NTSC frequencies. The register is undocumented :( 356 * FIXME: figure out the parent and how the divider works. 357 */ 358 mult = 1; 359 div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK); 360 dev_dbg(dev, "TVC half divider value = %d\n", div); 361 div += 1; 362 hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000); 363 gemini_clk_data->hws[GEMINI_CLK_TVC] = hw; 364 365 /* FIXME: very unclear what the parent is */ 366 hw = gemini_pci_clk_setup("PCI", "xtal", map); 367 gemini_clk_data->hws[GEMINI_CLK_PCI] = hw; 368 369 /* FIXME: very unclear what the parent is */ 370 hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000); 371 gemini_clk_data->hws[GEMINI_CLK_UART] = hw; 372 373 return 0; 374 } 375 376 static const struct of_device_id gemini_clk_dt_ids[] = { 377 { .compatible = "cortina,gemini-syscon", }, 378 { /* sentinel */ }, 379 }; 380 381 static struct platform_driver gemini_clk_driver = { 382 .probe = gemini_clk_probe, 383 .driver = { 384 .name = "gemini-clk", 385 .of_match_table = gemini_clk_dt_ids, 386 .suppress_bind_attrs = true, 387 }, 388 }; 389 builtin_platform_driver(gemini_clk_driver); 390 391 static void __init gemini_cc_init(struct device_node *np) 392 { 393 struct regmap *map; 394 struct clk_hw *hw; 395 unsigned long freq; 396 unsigned int mult, div; 397 u32 val; 398 int ret; 399 int i; 400 401 gemini_clk_data = kzalloc(sizeof(*gemini_clk_data) + 402 sizeof(*gemini_clk_data->hws) * GEMINI_NUM_CLKS, 403 GFP_KERNEL); 404 if (!gemini_clk_data) 405 return; 406 407 /* 408 * This way all clock fetched before the platform device probes, 409 * except those we assign here for early use, will be deferred. 410 */ 411 for (i = 0; i < GEMINI_NUM_CLKS; i++) 412 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 413 414 map = syscon_node_to_regmap(np); 415 if (IS_ERR(map)) { 416 pr_err("no syscon regmap\n"); 417 return; 418 } 419 /* 420 * We check that the regmap works on this very first access, 421 * but as this is an MMIO-backed regmap, subsequent regmap 422 * access is not going to fail and we skip error checks from 423 * this point. 424 */ 425 ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val); 426 if (ret) { 427 pr_err("failed to read global status register\n"); 428 return; 429 } 430 431 /* 432 * XTAL is the crystal oscillator, 60 or 30 MHz selected from 433 * strap pin E6 434 */ 435 if (val & PLL_OSC_SEL) 436 freq = 30000000; 437 else 438 freq = 60000000; 439 hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq); 440 pr_debug("main crystal @%lu MHz\n", freq / 1000000); 441 442 /* VCO clock derived from the crystal */ 443 mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK); 444 div = 2; 445 /* If we run on 30 MHz crystal we have to multiply with two */ 446 if (val & PLL_OSC_SEL) 447 mult *= 2; 448 hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div); 449 450 /* The AHB clock is always 1/3 of the VCO */ 451 hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3); 452 gemini_clk_data->hws[GEMINI_CLK_AHB] = hw; 453 454 /* The APB clock is always 1/6 of the AHB */ 455 hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6); 456 gemini_clk_data->hws[GEMINI_CLK_APB] = hw; 457 458 /* Register the clocks to be accessed by the device tree */ 459 gemini_clk_data->num = GEMINI_NUM_CLKS; 460 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data); 461 } 462 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init); 463