1 /* 2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> 3 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Gated clock implementation 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/io.h> 16 #include <linux/err.h> 17 #include <linux/string.h> 18 19 /** 20 * DOC: basic gatable clock which can gate and ungate it's ouput 21 * 22 * Traits of this clock: 23 * prepare - clk_(un)prepare only ensures parent is (un)prepared 24 * enable - clk_enable and clk_disable are functional & control gating 25 * rate - inherits rate from parent. No clk_set_rate support 26 * parent - fixed parent. No clk_set_parent support 27 */ 28 29 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 30 31 /* 32 * It works on following logic: 33 * 34 * For enabling clock, enable = 1 35 * set2dis = 1 -> clear bit -> set = 0 36 * set2dis = 0 -> set bit -> set = 1 37 * 38 * For disabling clock, enable = 0 39 * set2dis = 1 -> set bit -> set = 1 40 * set2dis = 0 -> clear bit -> set = 0 41 * 42 * So, result is always: enable xor set2dis. 43 */ 44 static void clk_gate_endisable(struct clk_hw *hw, int enable) 45 { 46 struct clk_gate *gate = to_clk_gate(hw); 47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; 48 unsigned long uninitialized_var(flags); 49 u32 reg; 50 51 set ^= enable; 52 53 if (gate->lock) 54 spin_lock_irqsave(gate->lock, flags); 55 56 if (gate->flags & CLK_GATE_HIWORD_MASK) { 57 reg = BIT(gate->bit_idx + 16); 58 if (set) 59 reg |= BIT(gate->bit_idx); 60 } else { 61 reg = clk_readl(gate->reg); 62 63 if (set) 64 reg |= BIT(gate->bit_idx); 65 else 66 reg &= ~BIT(gate->bit_idx); 67 } 68 69 clk_writel(reg, gate->reg); 70 71 if (gate->lock) 72 spin_unlock_irqrestore(gate->lock, flags); 73 } 74 75 static int clk_gate_enable(struct clk_hw *hw) 76 { 77 clk_gate_endisable(hw, 1); 78 79 return 0; 80 } 81 82 static void clk_gate_disable(struct clk_hw *hw) 83 { 84 clk_gate_endisable(hw, 0); 85 } 86 87 static int clk_gate_is_enabled(struct clk_hw *hw) 88 { 89 u32 reg; 90 struct clk_gate *gate = to_clk_gate(hw); 91 92 reg = clk_readl(gate->reg); 93 94 /* if a set bit disables this clk, flip it before masking */ 95 if (gate->flags & CLK_GATE_SET_TO_DISABLE) 96 reg ^= BIT(gate->bit_idx); 97 98 reg &= BIT(gate->bit_idx); 99 100 return reg ? 1 : 0; 101 } 102 103 const struct clk_ops clk_gate_ops = { 104 .enable = clk_gate_enable, 105 .disable = clk_gate_disable, 106 .is_enabled = clk_gate_is_enabled, 107 }; 108 EXPORT_SYMBOL_GPL(clk_gate_ops); 109 110 /** 111 * clk_register_gate - register a gate clock with the clock framework 112 * @dev: device that is registering this clock 113 * @name: name of this clock 114 * @parent_name: name of this clock's parent 115 * @flags: framework-specific flags for this clock 116 * @reg: register address to control gating of this clock 117 * @bit_idx: which bit in the register controls gating of this clock 118 * @clk_gate_flags: gate-specific flags for this clock 119 * @lock: shared register lock for this clock 120 */ 121 struct clk *clk_register_gate(struct device *dev, const char *name, 122 const char *parent_name, unsigned long flags, 123 void __iomem *reg, u8 bit_idx, 124 u8 clk_gate_flags, spinlock_t *lock) 125 { 126 struct clk_gate *gate; 127 struct clk *clk; 128 struct clk_init_data init; 129 130 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { 131 if (bit_idx > 16) { 132 pr_err("gate bit exceeds LOWORD field\n"); 133 return ERR_PTR(-EINVAL); 134 } 135 } 136 137 /* allocate the gate */ 138 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 139 if (!gate) { 140 pr_err("%s: could not allocate gated clk\n", __func__); 141 return ERR_PTR(-ENOMEM); 142 } 143 144 init.name = name; 145 init.ops = &clk_gate_ops; 146 init.flags = flags | CLK_IS_BASIC; 147 init.parent_names = (parent_name ? &parent_name: NULL); 148 init.num_parents = (parent_name ? 1 : 0); 149 150 /* struct clk_gate assignments */ 151 gate->reg = reg; 152 gate->bit_idx = bit_idx; 153 gate->flags = clk_gate_flags; 154 gate->lock = lock; 155 gate->hw.init = &init; 156 157 clk = clk_register(dev, &gate->hw); 158 159 if (IS_ERR(clk)) 160 kfree(gate); 161 162 return clk; 163 } 164 EXPORT_SYMBOL_GPL(clk_register_gate); 165