1 /* 2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> 4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Adjustable divider clock implementation 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 #include <linux/err.h> 18 #include <linux/string.h> 19 #include <linux/log2.h> 20 21 /* 22 * DOC: basic adjustable divider clock that cannot gate 23 * 24 * Traits of this clock: 25 * prepare - clk_prepare only ensures that parents are prepared 26 * enable - clk_enable only ensures that parents are enabled 27 * rate - rate is adjustable. clk->rate = parent->rate / divisor 28 * parent - fixed parent. No clk_set_parent support 29 */ 30 31 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 32 33 #define div_mask(d) ((1 << ((d)->width)) - 1) 34 35 static unsigned int _get_table_maxdiv(const struct clk_div_table *table) 36 { 37 unsigned int maxdiv = 0; 38 const struct clk_div_table *clkt; 39 40 for (clkt = table; clkt->div; clkt++) 41 if (clkt->div > maxdiv) 42 maxdiv = clkt->div; 43 return maxdiv; 44 } 45 46 static unsigned int _get_maxdiv(struct clk_divider *divider) 47 { 48 if (divider->flags & CLK_DIVIDER_ONE_BASED) 49 return div_mask(divider); 50 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 51 return 1 << div_mask(divider); 52 if (divider->table) 53 return _get_table_maxdiv(divider->table); 54 return div_mask(divider) + 1; 55 } 56 57 static unsigned int _get_table_div(const struct clk_div_table *table, 58 unsigned int val) 59 { 60 const struct clk_div_table *clkt; 61 62 for (clkt = table; clkt->div; clkt++) 63 if (clkt->val == val) 64 return clkt->div; 65 return 0; 66 } 67 68 static unsigned int _get_div(struct clk_divider *divider, unsigned int val) 69 { 70 if (divider->flags & CLK_DIVIDER_ONE_BASED) 71 return val; 72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 73 return 1 << val; 74 if (divider->table) 75 return _get_table_div(divider->table, val); 76 return val + 1; 77 } 78 79 static unsigned int _get_table_val(const struct clk_div_table *table, 80 unsigned int div) 81 { 82 const struct clk_div_table *clkt; 83 84 for (clkt = table; clkt->div; clkt++) 85 if (clkt->div == div) 86 return clkt->val; 87 return 0; 88 } 89 90 static unsigned int _get_val(struct clk_divider *divider, u8 div) 91 { 92 if (divider->flags & CLK_DIVIDER_ONE_BASED) 93 return div; 94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 95 return __ffs(div); 96 if (divider->table) 97 return _get_table_val(divider->table, div); 98 return div - 1; 99 } 100 101 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 102 unsigned long parent_rate) 103 { 104 struct clk_divider *divider = to_clk_divider(hw); 105 unsigned int div, val; 106 107 val = clk_readl(divider->reg) >> divider->shift; 108 val &= div_mask(divider); 109 110 div = _get_div(divider, val); 111 if (!div) { 112 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 113 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 114 __clk_get_name(hw->clk)); 115 return parent_rate; 116 } 117 118 return parent_rate / div; 119 } 120 121 /* 122 * The reverse of DIV_ROUND_UP: The maximum number which 123 * divided by m is r 124 */ 125 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) 126 127 static bool _is_valid_table_div(const struct clk_div_table *table, 128 unsigned int div) 129 { 130 const struct clk_div_table *clkt; 131 132 for (clkt = table; clkt->div; clkt++) 133 if (clkt->div == div) 134 return true; 135 return false; 136 } 137 138 static bool _is_valid_div(struct clk_divider *divider, unsigned int div) 139 { 140 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 141 return is_power_of_2(div); 142 if (divider->table) 143 return _is_valid_table_div(divider->table, div); 144 return true; 145 } 146 147 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 148 unsigned long *best_parent_rate) 149 { 150 struct clk_divider *divider = to_clk_divider(hw); 151 int i, bestdiv = 0; 152 unsigned long parent_rate, best = 0, now, maxdiv; 153 unsigned long parent_rate_saved = *best_parent_rate; 154 155 if (!rate) 156 rate = 1; 157 158 maxdiv = _get_maxdiv(divider); 159 160 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { 161 parent_rate = *best_parent_rate; 162 bestdiv = DIV_ROUND_UP(parent_rate, rate); 163 bestdiv = bestdiv == 0 ? 1 : bestdiv; 164 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 165 return bestdiv; 166 } 167 168 /* 169 * The maximum divider we can use without overflowing 170 * unsigned long in rate * i below 171 */ 172 maxdiv = min(ULONG_MAX / rate, maxdiv); 173 174 for (i = 1; i <= maxdiv; i++) { 175 if (!_is_valid_div(divider, i)) 176 continue; 177 if (rate * i == parent_rate_saved) { 178 /* 179 * It's the most ideal case if the requested rate can be 180 * divided from parent clock without needing to change 181 * parent rate, so return the divider immediately. 182 */ 183 *best_parent_rate = parent_rate_saved; 184 return i; 185 } 186 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 187 MULT_ROUND_UP(rate, i)); 188 now = parent_rate / i; 189 if (now <= rate && now > best) { 190 bestdiv = i; 191 best = now; 192 *best_parent_rate = parent_rate; 193 } 194 } 195 196 if (!bestdiv) { 197 bestdiv = _get_maxdiv(divider); 198 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); 199 } 200 201 return bestdiv; 202 } 203 204 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 205 unsigned long *prate) 206 { 207 int div; 208 div = clk_divider_bestdiv(hw, rate, prate); 209 210 return *prate / div; 211 } 212 213 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 214 unsigned long parent_rate) 215 { 216 struct clk_divider *divider = to_clk_divider(hw); 217 unsigned int div, value; 218 unsigned long flags = 0; 219 u32 val; 220 221 div = parent_rate / rate; 222 value = _get_val(divider, div); 223 224 if (value > div_mask(divider)) 225 value = div_mask(divider); 226 227 if (divider->lock) 228 spin_lock_irqsave(divider->lock, flags); 229 230 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { 231 val = div_mask(divider) << (divider->shift + 16); 232 } else { 233 val = clk_readl(divider->reg); 234 val &= ~(div_mask(divider) << divider->shift); 235 } 236 val |= value << divider->shift; 237 clk_writel(val, divider->reg); 238 239 if (divider->lock) 240 spin_unlock_irqrestore(divider->lock, flags); 241 242 return 0; 243 } 244 245 const struct clk_ops clk_divider_ops = { 246 .recalc_rate = clk_divider_recalc_rate, 247 .round_rate = clk_divider_round_rate, 248 .set_rate = clk_divider_set_rate, 249 }; 250 EXPORT_SYMBOL_GPL(clk_divider_ops); 251 252 static struct clk *_register_divider(struct device *dev, const char *name, 253 const char *parent_name, unsigned long flags, 254 void __iomem *reg, u8 shift, u8 width, 255 u8 clk_divider_flags, const struct clk_div_table *table, 256 spinlock_t *lock) 257 { 258 struct clk_divider *div; 259 struct clk *clk; 260 struct clk_init_data init; 261 262 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { 263 if (width + shift > 16) { 264 pr_warn("divider value exceeds LOWORD field\n"); 265 return ERR_PTR(-EINVAL); 266 } 267 } 268 269 /* allocate the divider */ 270 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); 271 if (!div) { 272 pr_err("%s: could not allocate divider clk\n", __func__); 273 return ERR_PTR(-ENOMEM); 274 } 275 276 init.name = name; 277 init.ops = &clk_divider_ops; 278 init.flags = flags | CLK_IS_BASIC; 279 init.parent_names = (parent_name ? &parent_name: NULL); 280 init.num_parents = (parent_name ? 1 : 0); 281 282 /* struct clk_divider assignments */ 283 div->reg = reg; 284 div->shift = shift; 285 div->width = width; 286 div->flags = clk_divider_flags; 287 div->lock = lock; 288 div->hw.init = &init; 289 div->table = table; 290 291 /* register the clock */ 292 clk = clk_register(dev, &div->hw); 293 294 if (IS_ERR(clk)) 295 kfree(div); 296 297 return clk; 298 } 299 300 /** 301 * clk_register_divider - register a divider clock with the clock framework 302 * @dev: device registering this clock 303 * @name: name of this clock 304 * @parent_name: name of clock's parent 305 * @flags: framework-specific flags 306 * @reg: register address to adjust divider 307 * @shift: number of bits to shift the bitfield 308 * @width: width of the bitfield 309 * @clk_divider_flags: divider-specific flags for this clock 310 * @lock: shared register lock for this clock 311 */ 312 struct clk *clk_register_divider(struct device *dev, const char *name, 313 const char *parent_name, unsigned long flags, 314 void __iomem *reg, u8 shift, u8 width, 315 u8 clk_divider_flags, spinlock_t *lock) 316 { 317 return _register_divider(dev, name, parent_name, flags, reg, shift, 318 width, clk_divider_flags, NULL, lock); 319 } 320 EXPORT_SYMBOL_GPL(clk_register_divider); 321 322 /** 323 * clk_register_divider_table - register a table based divider clock with 324 * the clock framework 325 * @dev: device registering this clock 326 * @name: name of this clock 327 * @parent_name: name of clock's parent 328 * @flags: framework-specific flags 329 * @reg: register address to adjust divider 330 * @shift: number of bits to shift the bitfield 331 * @width: width of the bitfield 332 * @clk_divider_flags: divider-specific flags for this clock 333 * @table: array of divider/value pairs ending with a div set to 0 334 * @lock: shared register lock for this clock 335 */ 336 struct clk *clk_register_divider_table(struct device *dev, const char *name, 337 const char *parent_name, unsigned long flags, 338 void __iomem *reg, u8 shift, u8 width, 339 u8 clk_divider_flags, const struct clk_div_table *table, 340 spinlock_t *lock) 341 { 342 return _register_divider(dev, name, parent_name, flags, reg, shift, 343 width, clk_divider_flags, table, lock); 344 } 345 EXPORT_SYMBOL_GPL(clk_register_divider_table); 346