xref: /openbmc/linux/drivers/clk/clk-conf.c (revision 62e7ca52)
1 /*
2  * Copyright (C) 2014 Samsung Electronics Co., Ltd.
3  * Sylwester Nawrocki <s.nawrocki@samsung.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
13 #include <linux/device.h>
14 #include <linux/of.h>
15 #include <linux/printk.h>
16 #include "clk.h"
17 
18 static int __set_clk_parents(struct device_node *node, bool clk_supplier)
19 {
20 	struct of_phandle_args clkspec;
21 	int index, rc, num_parents;
22 	struct clk *clk, *pclk;
23 
24 	num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
25 						 "#clock-cells");
26 	if (num_parents == -EINVAL)
27 		pr_err("clk: invalid value of clock-parents property at %s\n",
28 		       node->full_name);
29 
30 	for (index = 0; index < num_parents; index++) {
31 		rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
32 					"#clock-cells",	index, &clkspec);
33 		if (rc < 0) {
34 			/* skip empty (null) phandles */
35 			if (rc == -ENOENT)
36 				continue;
37 			else
38 				return rc;
39 		}
40 		if (clkspec.np == node && !clk_supplier)
41 			return 0;
42 		pclk = of_clk_get_by_clkspec(&clkspec);
43 		if (IS_ERR(pclk)) {
44 			pr_warn("clk: couldn't get parent clock %d for %s\n",
45 				index, node->full_name);
46 			return PTR_ERR(pclk);
47 		}
48 
49 		rc = of_parse_phandle_with_args(node, "assigned-clocks",
50 					"#clock-cells", index, &clkspec);
51 		if (rc < 0)
52 			goto err;
53 		if (clkspec.np == node && !clk_supplier) {
54 			rc = 0;
55 			goto err;
56 		}
57 		clk = of_clk_get_by_clkspec(&clkspec);
58 		if (IS_ERR(clk)) {
59 			pr_warn("clk: couldn't get parent clock %d for %s\n",
60 				index, node->full_name);
61 			rc = PTR_ERR(clk);
62 			goto err;
63 		}
64 
65 		rc = clk_set_parent(clk, pclk);
66 		if (rc < 0)
67 			pr_err("clk: failed to reparent %s to %s: %d\n",
68 			       __clk_get_name(clk), __clk_get_name(pclk), rc);
69 		clk_put(clk);
70 		clk_put(pclk);
71 	}
72 	return 0;
73 err:
74 	clk_put(pclk);
75 	return rc;
76 }
77 
78 static int __set_clk_rates(struct device_node *node, bool clk_supplier)
79 {
80 	struct of_phandle_args clkspec;
81 	struct property	*prop;
82 	const __be32 *cur;
83 	int rc, index = 0;
84 	struct clk *clk;
85 	u32 rate;
86 
87 	of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
88 		if (rate) {
89 			rc = of_parse_phandle_with_args(node, "assigned-clocks",
90 					"#clock-cells",	index, &clkspec);
91 			if (rc < 0) {
92 				/* skip empty (null) phandles */
93 				if (rc == -ENOENT)
94 					continue;
95 				else
96 					return rc;
97 			}
98 			if (clkspec.np == node && !clk_supplier)
99 				return 0;
100 
101 			clk = of_clk_get_by_clkspec(&clkspec);
102 			if (IS_ERR(clk)) {
103 				pr_warn("clk: couldn't get clock %d for %s\n",
104 					index, node->full_name);
105 				return PTR_ERR(clk);
106 			}
107 
108 			rc = clk_set_rate(clk, rate);
109 			if (rc < 0)
110 				pr_err("clk: couldn't set %s clock rate: %d\n",
111 				       __clk_get_name(clk), rc);
112 			clk_put(clk);
113 		}
114 		index++;
115 	}
116 	return 0;
117 }
118 
119 /**
120  * of_clk_set_defaults() - parse and set assigned clocks configuration
121  * @node: device node to apply clock settings for
122  * @clk_supplier: true if clocks supplied by @node should also be considered
123  *
124  * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
125  * and sets any specified clock parents and rates. The @clk_supplier argument
126  * should be set to true if @node may be also a clock supplier of any clock
127  * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
128  * If @clk_supplier is false the function exits returnning 0 as soon as it
129  * determines the @node is also a supplier of any of the clocks.
130  */
131 int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
132 {
133 	int rc;
134 
135 	if (!node)
136 		return 0;
137 
138 	rc = __set_clk_parents(node, clk_supplier);
139 	if (rc < 0)
140 		return rc;
141 
142 	return __set_clk_rates(node, clk_supplier);
143 }
144 EXPORT_SYMBOL_GPL(of_clk_set_defaults);
145