1 /* 2 * Cirrus Logic CLPS711X CLK driver 3 * 4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/clkdev.h> 14 #include <linux/io.h> 15 #include <linux/ioport.h> 16 #include <linux/of_address.h> 17 #include <linux/slab.h> 18 #include <linux/mfd/syscon/clps711x.h> 19 20 #include <dt-bindings/clock/clps711x-clock.h> 21 22 #define CLPS711X_SYSCON1 (0x0100) 23 #define CLPS711X_SYSCON2 (0x1100) 24 #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET) 25 #define CLPS711X_PLLR (0xa5a8) 26 27 #define CLPS711X_EXT_FREQ (13000000) 28 #define CLPS711X_OSC_FREQ (3686400) 29 30 static const struct clk_div_table spi_div_table[] = { 31 { .val = 0, .div = 32, }, 32 { .val = 1, .div = 8, }, 33 { .val = 2, .div = 2, }, 34 { .val = 3, .div = 1, }, 35 }; 36 37 static const struct clk_div_table timer_div_table[] = { 38 { .val = 0, .div = 256, }, 39 { .val = 1, .div = 1, }, 40 }; 41 42 struct clps711x_clk { 43 struct clk_onecell_data clk_data; 44 spinlock_t lock; 45 struct clk *clks[CLPS711X_CLK_MAX]; 46 }; 47 48 static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base, 49 u32 fref) 50 { 51 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi; 52 struct clps711x_clk *clps711x_clk; 53 unsigned i; 54 55 if (!base) 56 return ERR_PTR(-ENOMEM); 57 58 clps711x_clk = kzalloc(sizeof(*clps711x_clk), GFP_KERNEL); 59 if (!clps711x_clk) 60 return ERR_PTR(-ENOMEM); 61 62 spin_lock_init(&clps711x_clk->lock); 63 64 /* Read PLL multiplier value and sanity check */ 65 tmp = readl(base + CLPS711X_PLLR) >> 24; 66 if (((tmp >= 10) && (tmp <= 50)) || !fref) 67 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); 68 else 69 f_pll = fref; 70 71 tmp = readl(base + CLPS711X_SYSFLG2); 72 if (tmp & SYSFLG2_CKMODE) { 73 f_cpu = CLPS711X_EXT_FREQ; 74 f_bus = CLPS711X_EXT_FREQ; 75 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96); 76 f_pll = 0; 77 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128); 78 } else { 79 f_cpu = f_pll; 80 if (f_cpu > 36864000) 81 f_bus = DIV_ROUND_UP(f_cpu, 2); 82 else 83 f_bus = 36864000 / 2; 84 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576); 85 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768); 86 } 87 88 if (tmp & SYSFLG2_CKMODE) { 89 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) 90 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); 91 else 92 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); 93 } else 94 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144); 95 96 tmp = readl(base + CLPS711X_SYSCON1); 97 /* Timer1 in free running mode. 98 * Counter will wrap around to 0xffff when it underflows 99 * and will continue to count down. 100 */ 101 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); 102 /* Timer2 in prescale mode. 103 * Value writen is automatically re-loaded when 104 * the counter underflows. 105 */ 106 tmp |= SYSCON1_TC2M | SYSCON1_TC2S; 107 writel(tmp, base + CLPS711X_SYSCON1); 108 109 clps711x_clk->clks[CLPS711X_CLK_DUMMY] = 110 clk_register_fixed_rate(NULL, "dummy", NULL, 0, 0); 111 clps711x_clk->clks[CLPS711X_CLK_CPU] = 112 clk_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu); 113 clps711x_clk->clks[CLPS711X_CLK_BUS] = 114 clk_register_fixed_rate(NULL, "bus", NULL, 0, f_bus); 115 clps711x_clk->clks[CLPS711X_CLK_PLL] = 116 clk_register_fixed_rate(NULL, "pll", NULL, 0, f_pll); 117 clps711x_clk->clks[CLPS711X_CLK_TIMERREF] = 118 clk_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim); 119 clps711x_clk->clks[CLPS711X_CLK_TIMER1] = 120 clk_register_divider_table(NULL, "timer1", "timer_ref", 0, 121 base + CLPS711X_SYSCON1, 5, 1, 0, 122 timer_div_table, &clps711x_clk->lock); 123 clps711x_clk->clks[CLPS711X_CLK_TIMER2] = 124 clk_register_divider_table(NULL, "timer2", "timer_ref", 0, 125 base + CLPS711X_SYSCON1, 7, 1, 0, 126 timer_div_table, &clps711x_clk->lock); 127 clps711x_clk->clks[CLPS711X_CLK_PWM] = 128 clk_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm); 129 clps711x_clk->clks[CLPS711X_CLK_SPIREF] = 130 clk_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi); 131 clps711x_clk->clks[CLPS711X_CLK_SPI] = 132 clk_register_divider_table(NULL, "spi", "spi_ref", 0, 133 base + CLPS711X_SYSCON1, 16, 2, 0, 134 spi_div_table, &clps711x_clk->lock); 135 clps711x_clk->clks[CLPS711X_CLK_UART] = 136 clk_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10); 137 clps711x_clk->clks[CLPS711X_CLK_TICK] = 138 clk_register_fixed_rate(NULL, "tick", NULL, 0, 64); 139 for (i = 0; i < CLPS711X_CLK_MAX; i++) 140 if (IS_ERR(clps711x_clk->clks[i])) 141 pr_err("clk %i: register failed with %ld\n", 142 i, PTR_ERR(clps711x_clk->clks[i])); 143 144 return clps711x_clk; 145 } 146 147 void __init clps711x_clk_init(void __iomem *base) 148 { 149 struct clps711x_clk *clps711x_clk; 150 151 clps711x_clk = _clps711x_clk_init(base, 73728000); 152 153 BUG_ON(IS_ERR(clps711x_clk)); 154 155 /* Clocksource */ 156 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER1], 157 NULL, "clps711x-timer.0"); 158 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER2], 159 NULL, "clps711x-timer.1"); 160 161 /* Drivers */ 162 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_PWM], 163 NULL, "clps711x-pwm"); 164 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART], 165 NULL, "clps711x-uart.0"); 166 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART], 167 NULL, "clps711x-uart.1"); 168 } 169 170 #ifdef CONFIG_OF 171 static void __init clps711x_clk_init_dt(struct device_node *np) 172 { 173 void __iomem *base = of_iomap(np, 0); 174 struct clps711x_clk *clps711x_clk; 175 u32 fref = 0; 176 177 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref)); 178 179 clps711x_clk = _clps711x_clk_init(base, fref); 180 BUG_ON(IS_ERR(clps711x_clk)); 181 182 clps711x_clk->clk_data.clks = clps711x_clk->clks; 183 clps711x_clk->clk_data.clk_num = CLPS711X_CLK_MAX; 184 of_clk_add_provider(np, of_clk_src_onecell_get, 185 &clps711x_clk->clk_data); 186 } 187 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); 188 #endif 189